A submicron photolysis polymer temporary bonding with ultra-fast laser de-bonding process of less than 20 s has been demonstrated where both photolysis polymer and polyimide are served as release layer and adhesive layer, respectively. In addition, the bonded structure provides high chemical resistance and mechanical strength for handling process. By measuring the electrical characteristics of devices before and after de-bond, it shows promising performance without degradation. Thus it can be a potential candidate for temporary bonding and de-bonding in 3D integration.
{"title":"Wafer-level MOSFET with submicron photolysis polymer temporary bonding technology using ultra-fast laser ablation for 3DIC application","authors":"Chuan-An Cheng, Yu-Hsiang Huang, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen","doi":"10.1109/VLSI-TSA.2016.7480487","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480487","url":null,"abstract":"A submicron photolysis polymer temporary bonding with ultra-fast laser de-bonding process of less than 20 s has been demonstrated where both photolysis polymer and polyimide are served as release layer and adhesive layer, respectively. In addition, the bonded structure provides high chemical resistance and mechanical strength for handling process. By measuring the electrical characteristics of devices before and after de-bond, it shows promising performance without degradation. Thus it can be a potential candidate for temporary bonding and de-bonding in 3D integration.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121027241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480498
Hung-Yu Chen, H. Chen, Y. Kao, Ping-Yu Chen, Y. King, C. Lin
This study proposed a new manufacturing method for improving the fabrication yield of CRRAM in advanced 90nm CMOS logic process. The original CMOS compatible CRRAM is proposed to fabricate by the thickness and size control of contact etch process. Due to the variation of contact hole etch on different ILD topographies, the remained RRAM's TMO could result in uniformity and yield problems of memory arrays. In order to decline the production variation, a new refilling Contact RRAM process is firstly proposed and demonstrated in this paper.
{"title":"A new manufacturing method of CMOS logic compatible 1T-CRRAM","authors":"Hung-Yu Chen, H. Chen, Y. Kao, Ping-Yu Chen, Y. King, C. Lin","doi":"10.1109/VLSI-TSA.2016.7480498","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480498","url":null,"abstract":"This study proposed a new manufacturing method for improving the fabrication yield of CRRAM in advanced 90nm CMOS logic process. The original CMOS compatible CRRAM is proposed to fabricate by the thickness and size control of contact etch process. Due to the variation of contact hole etch on different ILD topographies, the remained RRAM's TMO could result in uniformity and yield problems of memory arrays. In order to decline the production variation, a new refilling Contact RRAM process is firstly proposed and demonstrated in this paper.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122970172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480523
S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim
In this paper, we discuss the impact of transistor technology on the power savings in monolithic 3D ICs over traditional 2D ICs. Our results are based on gate-level 3D IC partitioning and full RTL to GDSII design and analysis of a Low Density Parity Check (LDPC) benchmark circuit block with use of two different silicon validated foundry technologies. These two technologies have the same nominal operating voltage, but differ in terms of device performance, power, and gate capacitance. Our results show that monolithic 3D IC provides 37.5% more power savings for the technology with lower device power and input capacitance compared to that of a high power device technology.
{"title":"Impact of transistor technology on power savings in monolithic 3D ICs","authors":"S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim","doi":"10.1109/VLSI-TSA.2016.7480523","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480523","url":null,"abstract":"In this paper, we discuss the impact of transistor technology on the power savings in monolithic 3D ICs over traditional 2D ICs. Our results are based on gate-level 3D IC partitioning and full RTL to GDSII design and analysis of a Low Density Parity Check (LDPC) benchmark circuit block with use of two different silicon validated foundry technologies. These two technologies have the same nominal operating voltage, but differ in terms of device performance, power, and gate capacitance. Our results show that monolithic 3D IC provides 37.5% more power savings for the technology with lower device power and input capacitance compared to that of a high power device technology.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121867528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480525
Ming‐Jiue Yu, Ruei-Ping Lin, Yu-Hong Chang, T. Hou
The wide band-gap a-IGZO is a promising channel material to realize high-voltage transistors that can be easily integrated on logic ICs by low-temperature 3D stacking. This monolithic 3D integration would enable on-chip power management to improve power consumption and integration density. We report a high-voltage a-IGZO TFT with the high-k Al2O3 gate dielectric. By using a low-temperature process below 200 °C, excellent transistor characteristics, including a current on/off ratio of 109, steep subthreshold swing of 0.1 V/decade, high breakdown voltage of 45 V, and robust bias stress reliability have been demonstrated.
{"title":"Reliable high-voltage amorphous InGaZnO TFT for monolithic 3D integration","authors":"Ming‐Jiue Yu, Ruei-Ping Lin, Yu-Hong Chang, T. Hou","doi":"10.1109/VLSI-TSA.2016.7480525","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480525","url":null,"abstract":"The wide band-gap a-IGZO is a promising channel material to realize high-voltage transistors that can be easily integrated on logic ICs by low-temperature 3D stacking. This monolithic 3D integration would enable on-chip power management to improve power consumption and integration density. We report a high-voltage a-IGZO TFT with the high-k Al2O3 gate dielectric. By using a low-temperature process below 200 °C, excellent transistor characteristics, including a current on/off ratio of 109, steep subthreshold swing of 0.1 V/decade, high breakdown voltage of 45 V, and robust bias stress reliability have been demonstrated.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128191771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480509
Yuchen Du, Lingming Yang, Hong Zhou, P. Ye
In this work, a new approach to chemically dope black phosphorus (BP) is presented which significantly enhances device performance of few-layer BP field-effect transistors (FETs). By applying 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), low on-state resistance and high field-effect mobility are achieved, where the mobility has been increased from 181.1 cm2/Vs to 228.5 cm2/Vs and the on-state resistance has been decreased from 7.4 Ω·mm down to 3.2 Ω·mm achieving a record high drain current of 531.8 mA/mm with a moderate channel length of 1.5 μm. In addition, transfer length method (TLM) structure has demonstrated a 2.9 times reduction in sheet resistance, and nearly 1.3 times decrease in contact resistance upon p-type surface charge transfer doping of BP FETs.
{"title":"P-type surface charge transfer doping of black phosphorus field-effect transistors","authors":"Yuchen Du, Lingming Yang, Hong Zhou, P. Ye","doi":"10.1109/VLSI-TSA.2016.7480509","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480509","url":null,"abstract":"In this work, a new approach to chemically dope black phosphorus (BP) is presented which significantly enhances device performance of few-layer BP field-effect transistors (FETs). By applying 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), low on-state resistance and high field-effect mobility are achieved, where the mobility has been increased from 181.1 cm2/Vs to 228.5 cm2/Vs and the on-state resistance has been decreased from 7.4 Ω·mm down to 3.2 Ω·mm achieving a record high drain current of 531.8 mA/mm with a moderate channel length of 1.5 μm. In addition, transfer length method (TLM) structure has demonstrated a 2.9 times reduction in sheet resistance, and nearly 1.3 times decrease in contact resistance upon p-type surface charge transfer doping of BP FETs.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132576129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480527
K. Endo, Y. Lee, Y. Ishikawa, F. Hsueh, P. Sung, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, H. Yamauchi, M. Masahara
FinFETs with the low temperature microwave annealing process have been successfully fabricated and the superiority of the microwave annealing process has been precisely studied. For the first time, it is revealed that the microwave annealed FinFET exhibits less Vth variability and lower gate leakage.
{"title":"Low temperature microwave annealed FinFETs with less Vth variability","authors":"K. Endo, Y. Lee, Y. Ishikawa, F. Hsueh, P. Sung, Y. Liu, T. Matsukawa, S. O'Uchi, J. Tsukada, H. Yamauchi, M. Masahara","doi":"10.1109/VLSI-TSA.2016.7480527","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480527","url":null,"abstract":"FinFETs with the low temperature microwave annealing process have been successfully fabricated and the superiority of the microwave annealing process has been precisely studied. For the first time, it is revealed that the microwave annealed FinFET exhibits less Vth variability and lower gate leakage.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480491
S. Salahuddin
A ferroelectric material stores energy from phase transition and in doing so it lends itself to be biased at a state where its capacitance is negative [1,2]. When such a negative capacitance is added in series to the gate of a, subthreshold swing in a Field Effect Transistor (FET), it is possible to reduce the subthreshold swing below 60 mV/decade, without changing the transport physics of the FET. Not having to change the transport physics means that the ON current can be high while the supply voltage can be reduced significantly. Therefore, the negative capacitance effect has the potential to lead to very low voltage yet high performance electronic switches.
{"title":"Review of negative capacitance transistors","authors":"S. Salahuddin","doi":"10.1109/VLSI-TSA.2016.7480491","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480491","url":null,"abstract":"A ferroelectric material stores energy from phase transition and in doing so it lends itself to be biased at a state where its capacitance is negative [1,2]. When such a negative capacitance is added in series to the gate of a, subthreshold swing in a Field Effect Transistor (FET), it is possible to reduce the subthreshold swing below 60 mV/decade, without changing the transport physics of the FET. Not having to change the transport physics means that the ON current can be high while the supply voltage can be reduced significantly. Therefore, the negative capacitance effect has the potential to lead to very low voltage yet high performance electronic switches.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480530
Lei Zhu, Shuangke Liu, F. Allibert, E. Desbonnets, I. Radu, Xinen Zhu, Yumin Lu
Trap rich silicon-on-insulator (TR-SOI) substrates have been widely adopted for high performance RFICs in cellular front-ends over the past few years. With the more stringent loss and harmonic requirements for 4G and even 5G networks, TR-SOI substrate's quality has been improved continuously since its introduction. Two representative types of commercially available TR-SOI substrates are investigated in this paper to demonstrate both small and large signal performance up to 10 GHz. 50 Ohm CPW lines and spiral inductors were fabricated on HR-SOI, TR-SOI, and quartz substrates. The experiment results show that TR-SOI substrates present attenuation coefficient less than 0.2 dB/mm, which is close to that of quartz substrates, and much improved harmonic suppression than HR-SOI substrates.
{"title":"RF performance of passive components on state-of-art trap rich silicon-on-insulator substrates","authors":"Lei Zhu, Shuangke Liu, F. Allibert, E. Desbonnets, I. Radu, Xinen Zhu, Yumin Lu","doi":"10.1109/VLSI-TSA.2016.7480530","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480530","url":null,"abstract":"Trap rich silicon-on-insulator (TR-SOI) substrates have been widely adopted for high performance RFICs in cellular front-ends over the past few years. With the more stringent loss and harmonic requirements for 4G and even 5G networks, TR-SOI substrate's quality has been improved continuously since its introduction. Two representative types of commercially available TR-SOI substrates are investigated in this paper to demonstrate both small and large signal performance up to 10 GHz. 50 Ohm CPW lines and spiral inductors were fabricated on HR-SOI, TR-SOI, and quartz substrates. The experiment results show that TR-SOI substrates present attenuation coefficient less than 0.2 dB/mm, which is close to that of quartz substrates, and much improved harmonic suppression than HR-SOI substrates.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114366998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480524
M. Kao, Chih-Chao Yang, Tsung-Ta Wu, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, W. Yeh, Meng-Fan Chang, J. Shieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low Ioff and high Ion operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm2) under 450 lux indoor illumination, envisions self-power and low cost 3D+IC for internet of things.
{"title":"a-SiGeC thin film photovoltaic enabled self-power monolithic 3D IC under indoor illumination","authors":"M. Kao, Chih-Chao Yang, Tsung-Ta Wu, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, W. Yeh, Meng-Fan Chang, J. Shieh","doi":"10.1109/VLSI-TSA.2016.7480524","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480524","url":null,"abstract":"Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low Ioff and high Ion operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm2) under 450 lux indoor illumination, envisions self-power and low cost 3D+IC for internet of things.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480522
Shang-Chun Chen, P. Tzeng, Yu-Chen Hsm, Chung-Chih Wang, Po-Chih Chang, Jui-Chm Chen, Yiu-Hsiang Chang, Tsuen-Sung Chen, T. Hsu, Hsiang-Hung Chang, C. Zhan, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai, T. Ku, Pei-Hua Wang, W. Lo
Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.
{"title":"Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration","authors":"Shang-Chun Chen, P. Tzeng, Yu-Chen Hsm, Chung-Chih Wang, Po-Chih Chang, Jui-Chm Chen, Yiu-Hsiang Chang, Tsuen-Sung Chen, T. Hsu, Hsiang-Hung Chang, C. Zhan, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai, T. Ku, Pei-Hua Wang, W. Lo","doi":"10.1109/VLSI-TSA.2016.7480522","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480522","url":null,"abstract":"Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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