In this paper, multi-phonon transition model of RTN in FinFETs with statistical distribution is integrated into industry-standard BSIM-CMG, and read stability of SRAM is thoroughly examined. Different tendencies of SRAM failure probability plateau caused by RTN are found, which reflect real circuit operation situations. The impacts of RTN amplitude, bitline capacity, operation frequency on Vmin are investigated in detail. Statistical results with impacts of RTN and process variations are also presented, which can be helpful for stability design and guard band prediction for SRAM.
{"title":"Deep understanding of random telegraph noise (RTN) effects on SRAM stability","authors":"Dongyuan Mao, Shaofeng Guo, Runsheng Wang, Mulong Luo, Ru Huang","doi":"10.1109/VLSI-TSA.2016.7480513","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480513","url":null,"abstract":"In this paper, multi-phonon transition model of RTN in FinFETs with statistical distribution is integrated into industry-standard BSIM-CMG, and read stability of SRAM is thoroughly examined. Different tendencies of SRAM failure probability plateau caused by RTN are found, which reflect real circuit operation situations. The impacts of RTN amplitude, bitline capacity, operation frequency on Vmin are investigated in detail. Statistical results with impacts of RTN and process variations are also presented, which can be helpful for stability design and guard band prediction for SRAM.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116407006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480528
M. Edmonds, T. Kent, S. Wolf, K. Sardashti, M. Chang, J. Kachian, R. Droopad, E. Chagarov, A. Kummel
Metal oxide semiconductor field effect transistors (MOSFETs) are diverging from the exclusive use of silicon and germanium to the employment of compound semiconductors such as SiGe and InGaAs to further increase transistor performance. A broader range of channel materials allowing better carrier confinement and higher mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Silicon uniquely bonds strongly to all crystallographic faces of InGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may subsequently be passivated by atomic hydrogen. Subsequently, the surface may be functionalized with an oxidant such as HOOH(g) in order to create a UCM terminating Si-OH layer, or a nitriding agent such as N2H4(g) in order to create an Si-Nx diffusion barrier and surface protection layer. This study focuses on depositing saturated Si-Hx, and Si-OH seed layers via two separate self-limiting CVD processes on InGaAs(001)-(2x4), and depositing a Si-Nx seed layer on Si0.5Ge0.5(110) via an ALD process. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of these silicon containing control layers on InGaAs(001)-(2x4) and Si0.5Ge0.5(110) surfaces. MOSCAP device fabrication was performed on n-type InGaAs(001) substrates with and without a Si-Hx passivation control layer deposited by self-limiting CVD in order to determine the effects on Cmax, frequency dispersion, and midgap trap states.
{"title":"In0.53Ga0.47As(001)−(2x4) and Si0.5Ge0.5(110) surface passivation by self-limiting deposition of silicon containing control layers","authors":"M. Edmonds, T. Kent, S. Wolf, K. Sardashti, M. Chang, J. Kachian, R. Droopad, E. Chagarov, A. Kummel","doi":"10.1109/VLSI-TSA.2016.7480528","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480528","url":null,"abstract":"Metal oxide semiconductor field effect transistors (MOSFETs) are diverging from the exclusive use of silicon and germanium to the employment of compound semiconductors such as SiGe and InGaAs to further increase transistor performance. A broader range of channel materials allowing better carrier confinement and higher mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Silicon uniquely bonds strongly to all crystallographic faces of InGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may subsequently be passivated by atomic hydrogen. Subsequently, the surface may be functionalized with an oxidant such as HOOH(g) in order to create a UCM terminating Si-OH layer, or a nitriding agent such as N2H4(g) in order to create an Si-Nx diffusion barrier and surface protection layer. This study focuses on depositing saturated Si-Hx, and Si-OH seed layers via two separate self-limiting CVD processes on InGaAs(001)-(2x4), and depositing a Si-Nx seed layer on Si0.5Ge0.5(110) via an ALD process. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of these silicon containing control layers on InGaAs(001)-(2x4) and Si0.5Ge0.5(110) surfaces. MOSCAP device fabrication was performed on n-type InGaAs(001) substrates with and without a Si-Hx passivation control layer deposited by self-limiting CVD in order to determine the effects on Cmax, frequency dispersion, and midgap trap states.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480520
G. Molas, G. Piccolboni, M. Barci, B. Traoré, J. Guy, G. Palma, E. Vianello, P. Blaise, J. Portal, M. Bocquet, A. Levisse, B. Giraud, J. Noel, M. Harrand, M. Bernard, A. Roule, B. De Salvo, L. Perniola
Various RRAM concepts are currently being investigated (Oxide based RAM, Conductive Bridge RAM), all showing pros and cons depending on the architecture and memory stack. As the specifications are strongly application-dependent, it is likely that the RRAM technology will be bound to a specific market segment. In this paper, we discuss the potential of RRAM for non-volatile memory applications, among them: storage class memory, embedded memory, programmable logic, mass storage and neuromorphic applications. By means of experimental studies and simulations, we analyze the role of the integrated materials on the memory performances and reliability and try to propose optimized stacks suitable for each targeted application.
{"title":"Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications","authors":"G. Molas, G. Piccolboni, M. Barci, B. Traoré, J. Guy, G. Palma, E. Vianello, P. Blaise, J. Portal, M. Bocquet, A. Levisse, B. Giraud, J. Noel, M. Harrand, M. Bernard, A. Roule, B. De Salvo, L. Perniola","doi":"10.1109/VLSI-TSA.2016.7480520","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480520","url":null,"abstract":"Various RRAM concepts are currently being investigated (Oxide based RAM, Conductive Bridge RAM), all showing pros and cons depending on the architecture and memory stack. As the specifications are strongly application-dependent, it is likely that the RRAM technology will be bound to a specific market segment. In this paper, we discuss the potential of RRAM for non-volatile memory applications, among them: storage class memory, embedded memory, programmable logic, mass storage and neuromorphic applications. By means of experimental studies and simulations, we analyze the role of the integrated materials on the memory performances and reliability and try to propose optimized stacks suitable for each targeted application.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121135619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480534
R. Lyu, Yun-Hsuan Chiu, Horng-Chih Lin, Pei-Wen Li, Tiao-Yuan Huang
We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable Vth for high-gain BEOL logic gate inverters in a unique film-profile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4-0.8 μm) in a single step, leading to a wide-ranging tunability in Vth of -0.2-+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 μm IGZO TFT and 0.7μm IGZO drive-transistor, respectively, at operation voltage (Vdd) of 9V.
{"title":"High-gain, low-voltage BEOL logic gate inverter built with film profile engineered IGZO transistors","authors":"R. Lyu, Yun-Hsuan Chiu, Horng-Chih Lin, Pei-Wen Li, Tiao-Yuan Huang","doi":"10.1109/VLSI-TSA.2016.7480534","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480534","url":null,"abstract":"We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable Vth for high-gain BEOL logic gate inverters in a unique film-profile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4-0.8 μm) in a single step, leading to a wide-ranging tunability in Vth of -0.2-+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 μm IGZO TFT and 0.7μm IGZO drive-transistor, respectively, at operation voltage (Vdd) of 9V.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115481237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480508
I. Schulmeyer, L. Lechner, A. Gu, R. Estrada, D. Stewart, L. Stern, S. McVey, B. Goetze, U. Mantz, R. Jammy
Semiconductor devices and packages have firmly moved in to an era where scaling is driven by 3D architectures. However, most of the metrology and inspection technologies in use today were developed for 2D devices and are inadequate to deal with 3D structures. An additional complication is the need for specific structural and defect information that may be buried deep within a 3D structure. We present concepts and technologies that allow for 3D imaging as well as tomography, enabling engineers to view structural information with unprecedented clarity, detail and speed.
{"title":"Advanced metrology and inspection solutions for a 3D world","authors":"I. Schulmeyer, L. Lechner, A. Gu, R. Estrada, D. Stewart, L. Stern, S. McVey, B. Goetze, U. Mantz, R. Jammy","doi":"10.1109/VLSI-TSA.2016.7480508","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480508","url":null,"abstract":"Semiconductor devices and packages have firmly moved in to an era where scaling is driven by 3D architectures. However, most of the metrology and inspection technologies in use today were developed for 2D devices and are inadequate to deal with 3D structures. An additional complication is the need for specific structural and defect information that may be buried deep within a 3D structure. We present concepts and technologies that allow for 3D imaging as well as tomography, enabling engineers to view structural information with unprecedented clarity, detail and speed.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480503
Lingjun Dai, Huaqiang Wu, B. Gao, H. Qian
A physics-based compact model is developed to describe the parameter variations of oxide RRAM devices. The stochastic generation of oxygen vacancies and the variation of generation energy are considered in the model for the main reasons of the parameter fluctuation during SET process. The model is verified based on the measured data from 1kb 1T-1R RRAM array. Cycle-to-cycle variation and device-to-device variations of SET voltage and ON resistance are simulated by the model and compared with the experimental data. The model can be used for the simulation of large-scale memory arrays and logic or security circuits based on RRAM devices.
{"title":"A compact model for the SET parameter variations of oxide RRAM array","authors":"Lingjun Dai, Huaqiang Wu, B. Gao, H. Qian","doi":"10.1109/VLSI-TSA.2016.7480503","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480503","url":null,"abstract":"A physics-based compact model is developed to describe the parameter variations of oxide RRAM devices. The stochastic generation of oxygen vacancies and the variation of generation energy are considered in the model for the main reasons of the parameter fluctuation during SET process. The model is verified based on the measured data from 1kb 1T-1R RRAM array. Cycle-to-cycle variation and device-to-device variations of SET voltage and ON resistance are simulated by the model and compared with the experimental data. The model can be used for the simulation of large-scale memory arrays and logic or security circuits based on RRAM devices.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129557465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480494
B. Magyari-Kope, Dan Duncan, Liang Zhao, Y. Nishi
Resistive random-access memory (RRAM), one of the most promising candidates for next generation non-volatile memory technology, nowadays still faces a series of challenges including switching-parameter variability, cycling endurance, and data retention. In order to cope with these challenges, ionic doping techniques have been widely explored to achieve better performance and reliability, through fine-tuning the switching material properties. The major factors that potentially affect the forming characteristics of doped transition metal oxides were systematically evaluated with density functional theory (DFT) calculations in conjunction with experimental observations to address the opportunities and challenges in achieving tunable RRAM characteristics.
{"title":"Doping technology for RRAM — Opportunities and challenges","authors":"B. Magyari-Kope, Dan Duncan, Liang Zhao, Y. Nishi","doi":"10.1109/VLSI-TSA.2016.7480494","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480494","url":null,"abstract":"Resistive random-access memory (RRAM), one of the most promising candidates for next generation non-volatile memory technology, nowadays still faces a series of challenges including switching-parameter variability, cycling endurance, and data retention. In order to cope with these challenges, ionic doping techniques have been widely explored to achieve better performance and reliability, through fine-tuning the switching material properties. The major factors that potentially affect the forming characteristics of doped transition metal oxides were systematically evaluated with density functional theory (DFT) calculations in conjunction with experimental observations to address the opportunities and challenges in achieving tunable RRAM characteristics.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122467243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480514
L. Yin, Hai Jiang, Lei Shen, Juncheng Wang, G. Du, Xiaoyan Liu
FinFET is regarded as one of the most promising device structure for future scaling-down demands. However, heat dispassion is a severe problem for the device performance and reliability in nano-scale FinFETs. Germanium (Ge) is a novel channel material with its high carrier mobility, especially for PMOSFET. However, the bulk thermal conductivity of Ge (52.98Wm-1K-1) is almost 3 times smaller than that of Si (148.6Wm-1K-1)[1], which will lead to more serious heat dispassion problems in Ge devices. What's more, the phonon mean free path is largely decreased in nano-device structure due to increased surface scatterings, which leads to a largely reduced thermal conductivity. Hence, heat dissipation problems will have a large impact on the performance of Ge FinFETs. In this paper, we use 3D Full Band Self-consistent Ensemble Monte Carlo Simulator and 3D Fourier Heat Conduction Solver to study the local heating effects (LHE) and its impact on 14nm Ge SOI pFinFETs. The heat dissipation path is also evaluated. From the simulation results, we find that 14nm Ge SOI FinFETs will experience severe heating problems and heat effects will seriously affect the device performance.
FinFET被认为是未来小型化需求中最有前途的器件结构之一。然而，散热是影响器件性能和可靠性的一个严重问题。锗(Ge)是一种新型的沟道材料，具有很高的载流子迁移率，尤其适用于PMOSFET。然而，Ge的体热导率(52.98Wm-1K-1)比Si的体热导率(148.6Wm-1K-1)几乎小3倍[1]，这将导致Ge器件更严重的散热问题。此外，由于表面散射的增加，声子平均自由程在纳米器件结构中大大降低，从而导致热导率大大降低。因此，散热问题将对Ge finfet的性能产生很大的影响。本文利用三维全波段自一致集成蒙特卡罗模拟器和三维傅立叶热传导求解器研究了14nm Ge SOI pfinfet的局部加热效应(LHE)及其影响。并对散热路径进行了评估。从仿真结果来看，我们发现14nm Ge SOI finfet会遇到严重的发热问题，热效应会严重影响器件性能。
{"title":"Investigation of local heating effect for 14nm Ge pFinFETs based on Monte Carlo method","authors":"L. Yin, Hai Jiang, Lei Shen, Juncheng Wang, G. Du, Xiaoyan Liu","doi":"10.1109/VLSI-TSA.2016.7480514","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480514","url":null,"abstract":"FinFET is regarded as one of the most promising device structure for future scaling-down demands. However, heat dispassion is a severe problem for the device performance and reliability in nano-scale FinFETs. Germanium (Ge) is a novel channel material with its high carrier mobility, especially for PMOSFET. However, the bulk thermal conductivity of Ge (52.98Wm-1K-1) is almost 3 times smaller than that of Si (148.6Wm-1K-1)[1], which will lead to more serious heat dispassion problems in Ge devices. What's more, the phonon mean free path is largely decreased in nano-device structure due to increased surface scatterings, which leads to a largely reduced thermal conductivity. Hence, heat dissipation problems will have a large impact on the performance of Ge FinFETs. In this paper, we use 3D Full Band Self-consistent Ensemble Monte Carlo Simulator and 3D Fourier Heat Conduction Solver to study the local heating effects (LHE) and its impact on 14nm Ge SOI pFinFETs. The heat dissipation path is also evaluated. From the simulation results, we find that 14nm Ge SOI FinFETs will experience severe heating problems and heat effects will seriously affect the device performance.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126805274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/vlsi-dat.2016.7482588
P. Reynaert, Yuhe Cao, M. Vigilante, P. Indirayanti
5G poses severe challenges to PA design. In the first place, output power and efficiency are of prime importance because of battery lifetime. The tradeoff between linear output power and efficiency is typically challenged by the high PAPR due to QAM modulation and/or OFDM techniques. But this important trade-off is challenged even more in 5G due to the high bandwidth requirements. Furthermore, the shift to higher frequencies, where more unused spectrum is available, also puts a burden on the overall PA architecture.
{"title":"Doherty techniques for 5G RF and mm-wave power amplifiers","authors":"P. Reynaert, Yuhe Cao, M. Vigilante, P. Indirayanti","doi":"10.1109/vlsi-dat.2016.7482588","DOIUrl":"https://doi.org/10.1109/vlsi-dat.2016.7482588","url":null,"abstract":"5G poses severe challenges to PA design. In the first place, output power and efficiency are of prime importance because of battery lifetime. The tradeoff between linear output power and efficiency is typically challenged by the high PAPR due to QAM modulation and/or OFDM techniques. But this important trade-off is challenged even more in 5G due to the high bandwidth requirements. Furthermore, the shift to higher frequencies, where more unused spectrum is available, also puts a burden on the overall PA architecture.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/vlsi-tsa.2016.7480474
Chun-Nan Liu
With the mobile data traffic increasing, network operators are urgently looking for new technologies for improving capacity, user data-rates, spectrum reuse and latency to fulfill user experience and variant new applications. Small cells will play an important role in the high capacity, densely deployed networks for future 5G networks and the three major use cases: include enhanced mobile broadband, massive machine type communications and ultra-reliable and low latency communications. This work presents the trend, technologies and architecture of small cells in 5G and highlights key techniques such as carrier aggregation, licensed and un-licensed band, mmWave, new waveform, coding and modulation, multi-cell cooperation and advanced MIMO.
{"title":"Trend, technology and architecture of small cell in 5G era","authors":"Chun-Nan Liu","doi":"10.1109/vlsi-tsa.2016.7480474","DOIUrl":"https://doi.org/10.1109/vlsi-tsa.2016.7480474","url":null,"abstract":"With the mobile data traffic increasing, network operators are urgently looking for new technologies for improving capacity, user data-rates, spectrum reuse and latency to fulfill user experience and variant new applications. Small cells will play an important role in the high capacity, densely deployed networks for future 5G networks and the three major use cases: include enhanced mobile broadband, massive machine type communications and ultra-reliable and low latency communications. This work presents the trend, technologies and architecture of small cells in 5G and highlights key techniques such as carrier aggregation, licensed and un-licensed band, mmWave, new waveform, coding and modulation, multi-cell cooperation and advanced MIMO.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121725229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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