Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672323
H. Andrei, C. Cepisca, S. Grigorescu, P. Andrei
A new method for calculation of first order sensitivity and sensitivity groups for Multiple FeedBack (MFB) filter in non-sinusoidal regime is presented. Such a group of linear dependent parameters is defined the relative input values of current and voltage harmonics. The interdependence of the various network sensitivities for a given network needs special consideration. Numerical example for Butterworth low-pass filter is used for the discussion of some aspects related to the sensitivity groups' problems.
{"title":"Sensitivity analysis of the Multiple FeedBack filter in non-sinusoidal regime","authors":"H. Andrei, C. Cepisca, S. Grigorescu, P. Andrei","doi":"10.1109/SM2ACD.2010.5672323","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672323","url":null,"abstract":"A new method for calculation of first order sensitivity and sensitivity groups for Multiple FeedBack (MFB) filter in non-sinusoidal regime is presented. Such a group of linear dependent parameters is defined the relative input values of current and voltage harmonics. The interdependence of the various network sensitivities for a given network needs special consideration. Numerical example for Butterworth low-pass filter is used for the discussion of some aspects related to the sensitivity groups' problems.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116598605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672353
M. Kotti, A. Sallem, M. Fakhfakh, M. Loulou
This brief proposes a novel multi-objective heuristic. It is a transformation of a mono-objective heuristic into a multi-objective one by addition of an archive and some non dominance computing routines. Performances of the proposed heuristic are demonstrated thru test functions. An application to the optimal sizing of a class AB second generation CMOS current conveyor is presented. Comparison with NSGA-II is given.
{"title":"A novel multi-objective algorithm: application to the optimal sizing of current conveyors","authors":"M. Kotti, A. Sallem, M. Fakhfakh, M. Loulou","doi":"10.1109/SM2ACD.2010.5672353","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672353","url":null,"abstract":"This brief proposes a novel multi-objective heuristic. It is a transformation of a mono-objective heuristic into a multi-objective one by addition of an archive and some non dominance computing routines. Performances of the proposed heuristic are demonstrated thru test functions. An application to the optimal sizing of a class AB second generation CMOS current conveyor is presented. Comparison with NSGA-II is given.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128092048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672341
A. Ebrahimi, H. M. Naimi, M. Gholami
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25µw quiescent power with 2GHz bandwidth and 1.5% THD.
{"title":"Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier","authors":"A. Ebrahimi, H. M. Naimi, M. Gholami","doi":"10.1109/SM2ACD.2010.5672341","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672341","url":null,"abstract":"In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25µw quiescent power with 2GHz bandwidth and 1.5% THD.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125630147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672304
F. Ykhlef
Frequency domain speech enhancement method is often defined in terms of the a priori SNR (Signal to Noise Ratio). A widely used method to determine the a priori SNR from noisy speech is the decision-directed approach. This paper presents a time-varying smoothing factor in the calculation of the decision-directed approach to improve the speech enhancement. Objective and subjective evaluation confirm superiority in noise suppression and quality of the enhanced speech.
{"title":"A time-varying smoothing factor for the decision-directed approach in speech enhancement","authors":"F. Ykhlef","doi":"10.1109/SM2ACD.2010.5672304","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672304","url":null,"abstract":"Frequency domain speech enhancement method is often defined in terms of the a priori SNR (Signal to Noise Ratio). A widely used method to determine the a priori SNR from noisy speech is the decision-directed approach. This paper presents a time-varying smoothing factor in the calculation of the decision-directed approach to improve the speech enhancement. Objective and subjective evaluation confirm superiority in noise suppression and quality of the enhanced speech.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/SM2ACD.2010.5672290
F. Schwartz, Qing Sun, J. Michel, Y. Hervé
In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method.
{"title":"A robustness-oriented design tool for the topology selection in analog synthesis","authors":"F. Schwartz, Qing Sun, J. Michel, Y. Hervé","doi":"10.1109/SM2ACD.2010.5672290","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672290","url":null,"abstract":"In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/SM2ACD.2010.5672343
M. Gholami, M. Sharifkhani, S. Saeedi, M. Atarodi
This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions.
{"title":"A DLL-based frequency synthesizer for VHF DVB-H/T receivers","authors":"M. Gholami, M. Sharifkhani, S. Saeedi, M. Atarodi","doi":"10.1109/SM2ACD.2010.5672343","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672343","url":null,"abstract":"This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126938831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ICECS.2009.5410756
F. Balik
In this work a new method of linear circuit design in frequency domain by poles (zeros) distribution optimization is presented. The method which uses the relationship between poles and appropriate sums of circuit time - constants does not need the poles determination, explicitly. New relationships, allowing us to calculate time - constants matrix for circuits having capacitors and inductors as reactive elements, have been derived. In the first stage of the method the criterion function is generated in semi - symbolic form, while in the second stage the optimization process is performed. The optimization loop does not include circuit equations formulation and solution. Thanks to this fact the method proposed appears to be very efficient. The example for optimal capacitor and inductor choice in such a way to reach the required transfer characteristics has been also included.
{"title":"A semi - symbolic method of electronic circuit design by pole and zero distribution optimization using time - constants approximation including inductors","authors":"F. Balik","doi":"10.1109/ICECS.2009.5410756","DOIUrl":"https://doi.org/10.1109/ICECS.2009.5410756","url":null,"abstract":"In this work a new method of linear circuit design in frequency domain by poles (zeros) distribution optimization is presented. The method which uses the relationship between poles and appropriate sums of circuit time - constants does not need the poles determination, explicitly. New relationships, allowing us to calculate time - constants matrix for circuits having capacitors and inductors as reactive elements, have been derived. In the first stage of the method the criterion function is generated in semi - symbolic form, while in the second stage the optimization process is performed. The optimization loop does not include circuit equations formulation and solution. Thanks to this fact the method proposed appears to be very efficient. The example for optimal capacitor and inductor choice in such a way to reach the required transfer characteristics has been also included.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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