Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672336
A. Ebrahimi, H. M. Naimi
New analytical equations are proposed for oscillation amplitude of the MOS Colpitts oscillator. These equations are obtained from a large signal analysis. The analysis is based on a reasonable estimation for the output waveform. The estimated waveform should satisfy the nonlinear differential equations governing the circuit. The validity of the resulted equations is verified through simulations using TSMC 0.18 µm CMOS process. Simulation results show the accuracy of the proposed method for a wide range of circuit parameters.
{"title":"An improvement on the analytical methods for amplitude analysis of the MOS Colpitts oscillator","authors":"A. Ebrahimi, H. M. Naimi","doi":"10.1109/SM2ACD.2010.5672336","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672336","url":null,"abstract":"New analytical equations are proposed for oscillation amplitude of the MOS Colpitts oscillator. These equations are obtained from a large signal analysis. The analysis is based on a reasonable estimation for the output waveform. The estimated waveform should satisfy the nonlinear differential equations governing the circuit. The validity of the resulted equations is verified through simulations using TSMC 0.18 µm CMOS process. Simulation results show the accuracy of the proposed method for a wide range of circuit parameters.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134236516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672300
Hahanov Vladimir, C. Svetlana, Litvinova Eugenia
This article describes logical analysis infrastructure of associative tables (matrices), which enables to perform processing the interaction of the input vector with n-dimensional algebra-logical space, specified by using the ordered and structured tables of problem-oriented data, which represent the associative behavioral models of logical objects. To estimate the interaction of vectors in algebra-logical space the universal quality criterion is developed. It makes possible to find and evaluate the quasioptimal solution to the problems of associative logical information retrieval. Examples of the infrastructure and algebra-logical procedures, designed to solve the traditional logical analysis problems, which confirm the efficiency and practical orientation of algebraic models, are given.
{"title":"Logic vector analysis of associative tables","authors":"Hahanov Vladimir, C. Svetlana, Litvinova Eugenia","doi":"10.1109/SM2ACD.2010.5672300","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672300","url":null,"abstract":"This article describes logical analysis infrastructure of associative tables (matrices), which enables to perform processing the interaction of the input vector with n-dimensional algebra-logical space, specified by using the ordered and structured tables of problem-oriented data, which represent the associative behavioral models of logical objects. To estimate the interaction of vectors in algebra-logical space the universal quality criterion is developed. It makes possible to find and evaluate the quasioptimal solution to the problems of associative logical information retrieval. Examples of the infrastructure and algebra-logical procedures, designed to solve the traditional logical analysis problems, which confirm the efficiency and practical orientation of algebraic models, are given.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124946910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672322
E. Martínez-Romero, E. Tlelo-Cuautle, C. Sánchez-López, S. Tan
We present the calculation of noise expressions of low voltage amplifiers by applying symbolic nodal analysis and using nullors. The nullor equivalents of the MOSFETs include only the dominant parasitic elements in order to generate a simplified symbolic noise expression, which provides a good insight to improve the design of low voltage amplifiers. The generated symbolic noise expressions are compared with HSPICE simulations, so that one can appreciate the good agreement with our proposed symbolic noise analysis approach.
{"title":"Symbolic noise analysis of low voltage amplifiers by using nullors","authors":"E. Martínez-Romero, E. Tlelo-Cuautle, C. Sánchez-López, S. Tan","doi":"10.1109/SM2ACD.2010.5672322","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672322","url":null,"abstract":"We present the calculation of noise expressions of low voltage amplifiers by applying symbolic nodal analysis and using nullors. The nullor equivalents of the MOSFETs include only the dominant parasitic elements in order to generate a simplified symbolic noise expression, which provides a good insight to improve the design of low voltage amplifiers. The generated symbolic noise expressions are compared with HSPICE simulations, so that one can appreciate the good agreement with our proposed symbolic noise analysis approach.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672365
Cristian E. Onete, M. Onete
In this paper, we use a modified version of the incidence matrix of an un-oriented graph so as to enumerate all the spanning trees. In particular, we formally describe the problem and then enumerate the spanning trees, also Showing how to use this method in finding the symbolic determinant of a passive circuit.
{"title":"Enumerating all the spanning trees in an un-oriented graph - A novel approach","authors":"Cristian E. Onete, M. Onete","doi":"10.1109/SM2ACD.2010.5672365","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672365","url":null,"abstract":"In this paper, we use a modified version of the incidence matrix of an un-oriented graph so as to enumerate all the spanning trees. In particular, we formally describe the problem and then enumerate the spanning trees, also Showing how to use this method in finding the symbolic determinant of a passive circuit.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114434875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672344
E. Calandra, Daniele Lupo
In this work, an attempt is made toward the development of a systematic design method for the performance-driven dimensioning of the various elements comprising the structure of modern transistor-based microwave injection-locked oscillators with transmission-type topologies (TILOs). The proposed approach is based on the use of appropriate diakoptics of the various circuit blocks into a matched environment, and their behavioral modeling in the fundamental-frequency dynamical complex envelope domain with the help of standard circuit and E.M. simulation CAD tools. This will permit, in the end, to obtain closed-form expressions for the main TILO performances in terms of the design parameters, thus permitting their optimization as a function of system-level specifications. The practical validity of the method developed was tested by designing and building a single transistor 10.75GHz core-TILO with a wide locking bandwidth (>4MHz) at the low nominal input power level targeted (−20dBm).
{"title":"Approach to the design of transmission-type injection-locked microwave oscillators through behavioral block modeling","authors":"E. Calandra, Daniele Lupo","doi":"10.1109/SM2ACD.2010.5672344","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672344","url":null,"abstract":"In this work, an attempt is made toward the development of a systematic design method for the performance-driven dimensioning of the various elements comprising the structure of modern transistor-based microwave injection-locked oscillators with transmission-type topologies (TILOs). The proposed approach is based on the use of appropriate diakoptics of the various circuit blocks into a matched environment, and their behavioral modeling in the fundamental-frequency dynamical complex envelope domain with the help of standard circuit and E.M. simulation CAD tools. This will permit, in the end, to obtain closed-form expressions for the main TILO performances in terms of the design parameters, thus permitting their optimization as a function of system-level specifications. The practical validity of the method developed was tested by designing and building a single transistor 10.75GHz core-TILO with a wide locking bandwidth (>4MHz) at the low nominal input power level targeted (−20dBm).","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"301 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121270384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672310
E. Roca, Manuel Velasco-Jimenez, R. Castro-López, F. Fernández
The use of performance trade-off fronts, also known as Pareto fronts, in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the fronts neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We propose a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a Miller operational amplifier, and experimental results show that this is a promising approach to solve the issue.
{"title":"Context-independent performance modeling of operational amplifiers using Pareto fronts","authors":"E. Roca, Manuel Velasco-Jimenez, R. Castro-López, F. Fernández","doi":"10.1109/SM2ACD.2010.5672310","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672310","url":null,"abstract":"The use of performance trade-off fronts, also known as Pareto fronts, in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the fronts neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We propose a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a Miller operational amplifier, and experimental results show that this is a promising approach to solve the issue.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131655373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672342
F. Meddour, Z. Dibi, S. Kouda, M. Abdi, M. Ouarghi, O. Manck
In complementary input differential pair circuits, the topology CMOS uses both an nMOS differential pair and a pMOS differential pair connected in parallel however, it produces variations in the transconductance over the input common mode range. To avoid the problem of transconductance variations, a new structure, consists of two op-amps one n-type and the other p-type controlled by a digital control system, is proposed. In this paper we purpose a solution of the instability problem of a voltage driver in 40 mV, and to improve the stability we subtract a constant current through the current mirror added to the driver.
{"title":"A new stabilisation technique for the voltage driver using the rail to rail operation in CMOS 0, 25 µm technology","authors":"F. Meddour, Z. Dibi, S. Kouda, M. Abdi, M. Ouarghi, O. Manck","doi":"10.1109/SM2ACD.2010.5672342","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672342","url":null,"abstract":"In complementary input differential pair circuits, the topology CMOS uses both an nMOS differential pair and a pMOS differential pair connected in parallel however, it produces variations in the transconductance over the input common mode range. To avoid the problem of transconductance variations, a new structure, consists of two op-amps one n-type and the other p-type controlled by a digital control system, is proposed. In this paper we purpose a solution of the instability problem of a voltage driver in 40 mV, and to improve the stability we subtract a constant current through the current mirror added to the driver.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672352
K. Jaber, A. Fakhfakh, R. Neji
In this paper, an optimization is reported for the determination of time response (Tr) and power (P) of Electric Vehicle. The electric constant of back-electromotive-force, stator d- and q- axes inductances, switching period, battery voltage, stator resistance and torque gear ratio were selected as factors being able to influence the Tr and P. The optimization process was carried out with Doehlert experimental design.
{"title":"High level optimization of Electric Vehicle power-train with Doehlert experimental design","authors":"K. Jaber, A. Fakhfakh, R. Neji","doi":"10.1109/SM2ACD.2010.5672352","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672352","url":null,"abstract":"In this paper, an optimization is reported for the determination of time response (Tr) and power (P) of Electric Vehicle. The electric constant of back-electromotive-force, stator d- and q- axes inductances, switching period, battery voltage, stator resistance and torque gear ratio were selected as factors being able to influence the Tr and P. The optimization process was carried out with Doehlert experimental design.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133009235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672291
I. Asenova, D. Georgiev, M. Mihova
An algorithm for multiparameter sensitivity analysis of a synthesized network based on a nullor model of active devices is implemented. It is simplified by using the modified Coates flow-graph. Due to the suggested method, additional information for parameter influence upon transmission coefficients in the circuit is obtained, all partial transfer functions and their products can be found. An example on symbolic analysis of universal filter with the operational transresistance amplifier model is given in order to show the usefulness of the proposed symbolic method for multiparameter sensitivity analysis based on the nullor model.
{"title":"Multiparameter symbolic sensitivity analysis by using nullor model and Coates flow graphs","authors":"I. Asenova, D. Georgiev, M. Mihova","doi":"10.1109/SM2ACD.2010.5672291","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672291","url":null,"abstract":"An algorithm for multiparameter sensitivity analysis of a synthesized network based on a nullor model of active devices is implemented. It is simplified by using the modified Coates flow-graph. Due to the suggested method, additional information for parameter influence upon transmission coefficients in the circuit is obtained, all partial transfer functions and their products can be found. An example on symbolic analysis of universal filter with the operational transresistance amplifier model is given in order to show the usefulness of the proposed symbolic method for multiparameter sensitivity analysis based on the nullor model.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134575092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672334
A. Ebrahimi, H. M. Naimi
In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results in 0.18µm CMOS technology are presented. The results show 113µW power consumption with 1.2V single supply, 1.1% total harmonic distortion (THD) and 1GHz band-width.
{"title":"A 1.2V single supply and low power, CMOS four-quadrant analog multiplier","authors":"A. Ebrahimi, H. M. Naimi","doi":"10.1109/SM2ACD.2010.5672334","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672334","url":null,"abstract":"In this paper, a new low voltage topology for analog multiplier is presented. The circuit can be used with single low-power supply. The complete circuit has only twelve transistors; therefore, it satisfies the need for compact sub-circuit in analog VLSI systems. The mathematical discussion on the power consumption, total harmonic distortion and other features of the circuit and also simulation results in 0.18µm CMOS technology are presented. The results show 113µW power consumption with 1.2V single supply, 1.1% total harmonic distortion (THD) and 1GHz band-width.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124357103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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