Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802886
Jin-Fu Li, Cheng-Wen Wu
We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size.
{"title":"Testable and fault tolerant design for FFT networks","authors":"Jin-Fu Li, Cheng-Wen Wu","doi":"10.1109/DFTVS.1999.802886","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802886","url":null,"abstract":"We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802904
Wenyi Feng, Xiao-Tao Chen, F. Meyer, F. Lombardi
A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.
{"title":"Reconfiguration of one-time programmable FPGAs with faulty logic resources","authors":"Wenyi Feng, Xiao-Tao Chen, F. Meyer, F. Lombardi","doi":"10.1109/DFTVS.1999.802904","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802904","url":null,"abstract":"A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131330478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802865
G. Chapman, Y. Audet
A 36/spl times/24 mm active pixel sensor imaging area device is studied which would be ideal for use with standard 35 mm cameras. By applying multichip methods to active pixel sensors, the 39/spl times/30 mm system contains on board all the control circuitry and A/D converters, so the system outputs digital data. The large area requires a redundancy of design for a high yield. This starts with the active pixel cell, which able to withstand several defects and still be repairable, which CCD cells are not. The whole system is targeted at preventing bad rows or columns. By using spares in the row and column circuitry, as well as spare A/D converters the chip yield is only limited by a relatively small logic and control block. With repairs the yield of this 11.7 sq. cm system goes from almost nil to more than 80%-93% with modest defect densities of 1.5 to 0.5 per sq. cm. By being a retrofit for current 35 mm cameras, and having larger photodiode pixels than current APS's this CMOS device would be nearly as sensitive as CCD's but at much lower production costs and much higher yields.
{"title":"Creating 35 mm camera active pixel sensors","authors":"G. Chapman, Y. Audet","doi":"10.1109/DFTVS.1999.802865","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802865","url":null,"abstract":"A 36/spl times/24 mm active pixel sensor imaging area device is studied which would be ideal for use with standard 35 mm cameras. By applying multichip methods to active pixel sensors, the 39/spl times/30 mm system contains on board all the control circuitry and A/D converters, so the system outputs digital data. The large area requires a redundancy of design for a high yield. This starts with the active pixel cell, which able to withstand several defects and still be repairable, which CCD cells are not. The whole system is targeted at preventing bad rows or columns. By using spares in the row and column circuitry, as well as spare A/D converters the chip yield is only limited by a relatively small logic and control block. With repairs the yield of this 11.7 sq. cm system goes from almost nil to more than 80%-93% with modest defect densities of 1.5 to 0.5 per sq. cm. By being a retrofit for current 35 mm cameras, and having larger photodiode pixels than current APS's this CMOS device would be nearly as sensitive as CCD's but at much lower production costs and much higher yields.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129022744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802892
W. Gallagher, E. Swartzlander
The Newton-Raphson algorithm and Goldschmidt's algorithm (series expansion) are two popular methods of implementing division. Both are based on multiplication and converge quadratically to the result over several iterations. Applying time shared triple modular redundancy (TSTMR), a fault tolerance technique, to such a divider requires using a smaller multiplier and triplicating the divider circuit. To reduce division latency, the division algorithm can be modified to use lower precision multiplications during early iterations. This work summarizes and compares several important properties of these dividers: latency, area, average power dissipation and energy per divide.
{"title":"Power consumption in fast dividers using time shared TMR","authors":"W. Gallagher, E. Swartzlander","doi":"10.1109/DFTVS.1999.802892","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802892","url":null,"abstract":"The Newton-Raphson algorithm and Goldschmidt's algorithm (series expansion) are two popular methods of implementing division. Both are based on multiplication and converge quadratically to the result over several iterations. Applying time shared triple modular redundancy (TSTMR), a fault tolerance technique, to such a divider requires using a smaller multiplier and triplicating the divider circuit. To reduce division latency, the division algorithm can be modified to use lower precision multiplications during early iterations. This work summarizes and compares several important properties of these dividers: latency, area, average power dissipation and energy per divide.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802884
F. Khadour, Xiaoling Sun
This paper presents a novel technique to compute the signatures of multiple-input shift-registers (MISRs) in computer simulation when used in conjunction with parallel pattern single fault propagation (PPSFP) simulators. We first use a look-up table technique similar to compute a set of signatures, one for each input data stream of a MISR, at a common input tap position. Then we present an algorithm that modifies these signatures to reflect their actual input positions and obtain the final signature. Our experimental results show that the proposed signature simulation technique outperforms some existing methods with minimal memory requirements.
{"title":"Fast signature simulation for PPSFP simulators","authors":"F. Khadour, Xiaoling Sun","doi":"10.1109/DFTVS.1999.802884","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802884","url":null,"abstract":"This paper presents a novel technique to compute the signatures of multiple-input shift-registers (MISRs) in computer simulation when used in conjunction with parallel pattern single fault propagation (PPSFP) simulators. We first use a look-up table technique similar to compute a set of signatures, one for each input data stream of a MISR, at a common input tap position. Then we present an algorithm that modifies these signatures to reflect their actual input positions and obtain the final signature. Our experimental results show that the proposed signature simulation technique outperforms some existing methods with minimal memory requirements.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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