Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802898
Y. Katayama, E. Stuckey, S. Morioka, Z. Wu
A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to ensure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100X) reducing the refresh power. Experimental results of a test system are presented.
{"title":"Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention","authors":"Y. Katayama, E. Stuckey, S. Morioka, Z. Wu","doi":"10.1109/DFTVS.1999.802898","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802898","url":null,"abstract":"A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to ensure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100X) reducing the refresh power. Experimental results of a test system are presented.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117283101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802872
Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, W. Jone
Because domino logic design offers smaller area and higher speed than conventional CMOS design, it is very popular in high performance processor design. However, domino logic suffers from several design problems and one of the most notable is the charge sharing problem. In domino logic, there are two operations: the pre-charge phase and the evaluation phase. The charge sharing problem occurs when the charge which is stored at the output node in the pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level or even cause an erroneous output value. In this paper, we describe a method to measure the sensitivity of the charge sharing problem for a domino gate. For each domino gate, we compute a value called CS-vulnerability which describes the degree of sensitivity for a domino gate to have the charge sharing problem. In addition, our algorithm also generates test vectors to activate the worst case of the charge sharing problem. We have performed experiments on a large set of MCNC benchmark circuits.
{"title":"Charge sharing fault detection for CMOS domino logic circuits","authors":"Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, W. Jone","doi":"10.1109/DFTVS.1999.802872","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802872","url":null,"abstract":"Because domino logic design offers smaller area and higher speed than conventional CMOS design, it is very popular in high performance processor design. However, domino logic suffers from several design problems and one of the most notable is the charge sharing problem. In domino logic, there are two operations: the pre-charge phase and the evaluation phase. The charge sharing problem occurs when the charge which is stored at the output node in the pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level or even cause an erroneous output value. In this paper, we describe a method to measure the sensitivity of the charge sharing problem for a domino gate. For each domino gate, we compute a value called CS-vulnerability which describes the degree of sensitivity for a domino gate to have the charge sharing problem. In addition, our algorithm also generates test vectors to activate the worst case of the charge sharing problem. We have performed experiments on a large set of MCNC benchmark circuits.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116060516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802893
V. Piuri, E. Swartzlander
This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.
{"title":"Time-shared modular redundancy for fault-tolerant FFT processors","authors":"V. Piuri, E. Swartzlander","doi":"10.1109/DFTVS.1999.802893","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802893","url":null,"abstract":"This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802877
X. Kavousianos, D. Bakalis, H. T. Vergos, D. Nikolos, G. Alexiou
Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small.
{"title":"Low power dissipation in BIST schemes for modified Booth multipliers","authors":"X. Kavousianos, D. Bakalis, H. T. Vergos, D. Nikolos, G. Alexiou","doi":"10.1109/DFTVS.1999.802877","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802877","url":null,"abstract":"Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124768761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802881
S. Bertazzoni, G. Cardarilli, D. Piergentili, M. Salmeri, A. Salsano, D. D. Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. D. Francesco, P. Picozza, A. Rovelli
In this paper we analyze the failures of Commercial Off The Shelf (COTS) 64 Mb Synchronous DRAM (SDRAM) in a radiation environment. The experimental setup, the test procedure, and the results of three different test runs at the Catania LNS-INFN cyclotron are described in some detail. Three kinds of heavy ions were used to test devices under different conditions of energy release that generates different amount of charge inside the chip. In particular, 30 MeV/AMU /sup 93/Nb (LET/sub Si//spl sim/21 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/397 /spl mu/m), 30 MeV/AMU /sup 120/Sn (LET/sub Si//spl sim/30 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/370 /spl mu/m) and 15 MeV/AMU /sup 197/Au (LET/sub Si//spl sim/90 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/95 /spl mu/m) were used. In all cases, the bare dies were directly bonded on an AF4 carrier to avoid plastic and lead-frame shielding. Different failure types that could affect the operations of a system based on this device were registered. To verify that the characteristics of the events depend on the zone struck by the particle, a specific test was performed.
{"title":"Failure tests on 64 Mb SDRAM in radiation environment","authors":"S. Bertazzoni, G. Cardarilli, D. Piergentili, M. Salmeri, A. Salsano, D. D. Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. D. Francesco, P. Picozza, A. Rovelli","doi":"10.1109/DFTVS.1999.802881","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802881","url":null,"abstract":"In this paper we analyze the failures of Commercial Off The Shelf (COTS) 64 Mb Synchronous DRAM (SDRAM) in a radiation environment. The experimental setup, the test procedure, and the results of three different test runs at the Catania LNS-INFN cyclotron are described in some detail. Three kinds of heavy ions were used to test devices under different conditions of energy release that generates different amount of charge inside the chip. In particular, 30 MeV/AMU /sup 93/Nb (LET/sub Si//spl sim/21 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/397 /spl mu/m), 30 MeV/AMU /sup 120/Sn (LET/sub Si//spl sim/30 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/370 /spl mu/m) and 15 MeV/AMU /sup 197/Au (LET/sub Si//spl sim/90 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/95 /spl mu/m) were used. In all cases, the bare dies were directly bonded on an AF4 carrier to avoid plastic and lead-frame shielding. Different failure types that could affect the operations of a system based on this device were registered. To verify that the characteristics of the events depend on the zone struck by the particle, a specific test was performed.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"27 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802873
S. Tragoudas, N. Denny
Path delay fault testing is often difficult due to the large number of paths that must be tested. Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of paths that need to be tested in a circuit. Test points allow the tester to test subpaths of the circuit and then draw conclusions of the operability of the circuit based upon the delays of subpaths. We illustrate some of the limitations of current subpath testing procedures and illustrate some of the difficulties associated with unstructured test point placement. We give an implementation of test points embedded in a scan chain and present a new testing technique that is more accurate than the previous method. We also present a novel test point insertion approach that has reasonable test times and minimal impact on the hardware size and the operational clock.
{"title":"Testing for path delay faults using test points","authors":"S. Tragoudas, N. Denny","doi":"10.1109/DFTVS.1999.802873","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802873","url":null,"abstract":"Path delay fault testing is often difficult due to the large number of paths that must be tested. Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of paths that need to be tested in a circuit. Test points allow the tester to test subpaths of the circuit and then draw conclusions of the operability of the circuit based upon the delays of subpaths. We illustrate some of the limitations of current subpath testing procedures and illustrate some of the difficulties associated with unstructured test point placement. We give an implementation of test points embedded in a scan chain and present a new testing technique that is more accurate than the previous method. We also present a novel test point insertion approach that has reasonable test times and minimal impact on the hardware size and the operational clock.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129034446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802906
J. Lach, W. Mangione-Smith, M. Potkonjak
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault recovery techniques. An algorithm for efficient runtime recovery from permanent logic faults in the Xilinx 4000 architecture has been expanded to include interconnect fault recovery and has been applied to a diverse set of FPGA architectures. The post-fault-detection system downtime is minimized, and the end user need not have access to computer-aided design (CAD) tools, making the algorithm completely transparent to system users. Although some architectural features allow for a more efficient implementation, high levels of fault recovery with low timing and resource overhead can be achieved on these diverse architectures.
{"title":"Algorithms for efficient runtime fault recovery on diverse FPGA architectures","authors":"J. Lach, W. Mangione-Smith, M. Potkonjak","doi":"10.1109/DFTVS.1999.802906","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802906","url":null,"abstract":"The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault recovery techniques. An algorithm for efficient runtime recovery from permanent logic faults in the Xilinx 4000 architecture has been expanded to include interconnect fault recovery and has been applied to a diverse set of FPGA architectures. The post-fault-detection system downtime is minimized, and the end user need not have access to computer-aided design (CAD) tools, making the algorithm completely transparent to system users. Although some architectural features allow for a more efficient implementation, high levels of fault recovery with low timing and resource overhead can be achieved on these diverse architectures.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802882
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N/sup 3/) to O(N/sup 2/), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.
{"title":"RAMSES: a fast memory fault simulator","authors":"Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu","doi":"10.1109/DFTVS.1999.802882","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802882","url":null,"abstract":"In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N/sup 3/) to O(N/sup 2/), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802889
M. Seuring, M. Gössel
In this paper a new structural method for linear output space compaction for synchronous sequential circuits is presented. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions are determined without fault simulation. The method is developed for concurrent checking, but as the experimental results show, it is also effectively applicable in pseudo-random test mode.
{"title":"A structural approach for space compaction for sequential circuits","authors":"M. Seuring, M. Gössel","doi":"10.1109/DFTVS.1999.802889","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802889","url":null,"abstract":"In this paper a new structural method for linear output space compaction for synchronous sequential circuits is presented. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions are determined without fault simulation. The method is developed for concurrent checking, but as the experimental results show, it is also effectively applicable in pseudo-random test mode.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126863536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802903
S. Cherubal, A. Chatterjee
In this paper we present a novel approach for fast fault simulation of digital faults in mixed-signal systems without resorting to expensive mixed-signal simulation for every fault. The approach is based on partitioning the mixed-signal circuit and representing digital fault effects using error waveforms. We propose methods to compress a large number of digital fault effects into a few fault syndromes. This results in significant savings in fault simulation effort. We demonstrate the ability to differentiate fault syndromes of different partitions of the circuit.
{"title":"A methodology for efficient simulation and diagnosis of mixed-signal systems using error waveforms","authors":"S. Cherubal, A. Chatterjee","doi":"10.1109/DFTVS.1999.802903","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802903","url":null,"abstract":"In this paper we present a novel approach for fast fault simulation of digital faults in mixed-signal systems without resorting to expensive mixed-signal simulation for every fault. The approach is based on partitioning the mixed-signal circuit and representing digital fault effects using error waveforms. We propose methods to compress a large number of digital fault effects into a few fault syndromes. This results in significant savings in fault simulation effort. We demonstrate the ability to differentiate fault syndromes of different partitions of the circuit.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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