Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802899
C. Wickman, D. Elliott, B. Cockburn
We present cost models appropriate for large file memory DRAMs that exploit error-correcting codes, redundant elements and bad block marking in order to reduce the average cost per working bit. Many different fault-tolerance methods have been considered previously for DRAMs but, because of the constraints of conventional commodity memory, only a few methods, such as redundant rows and columns, have entered wide-spread use. Our research on file memory breaks from past work by relaxing the requirements that random-access be fast and that shipped devices contain 100% of the nominal working bit capacity. We show that, under the relaxed requirements of file memory, the greater potential efficiencies of large ECC codewords and bad block marking may become cost-effective. These file memory techniques may thus be a way of accelerating the economic production of 256 Mbit and 1 Gbit DRAMs.
{"title":"Cost models for large file memory DRAMs with ECC and bad block marking","authors":"C. Wickman, D. Elliott, B. Cockburn","doi":"10.1109/DFTVS.1999.802899","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802899","url":null,"abstract":"We present cost models appropriate for large file memory DRAMs that exploit error-correcting codes, redundant elements and bad block marking in order to reduce the average cost per working bit. Many different fault-tolerance methods have been considered previously for DRAMs but, because of the constraints of conventional commodity memory, only a few methods, such as redundant rows and columns, have entered wide-spread use. Our research on file memory breaks from past work by relaxing the requirements that random-access be fast and that shipped devices contain 100% of the nominal working bit capacity. We show that, under the relaxed requirements of file memory, the greater potential efficiencies of large ECC codewords and bad block marking may become cost-effective. These file memory techniques may thus be a way of accelerating the economic production of 256 Mbit and 1 Gbit DRAMs.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132737229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802875
S. Ozev, A. Orailoglu
This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.
{"title":"Low-cost test for large analog IC's","authors":"S. Ozev, A. Orailoglu","doi":"10.1109/DFTVS.1999.802875","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802875","url":null,"abstract":"This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve effective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational effectiveness. Experimental results show that test translation reduces DFT overhead significantly while satisfying coverage requirements.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124313709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802867
N. Tomabechi
In designing defect-tolerant WSI systems, introducing subsystem-dividing in which an overall system is divided into subsystems and defect recovery is performed for every subsystem, results in reduced chip area of redundant interconnection lines and reduced delay time through redundant interconnection lines. On the other hand, subsystem-dividing results in reduced defect recovery ability. This paper presents a novel subsystem-dividing method called "the multi-dimensional subsystem-dividing", in which a system is divided into subsystems in multiple dimensions, i.e. multiple directions intersecting each other. Since spare circuits from different directions can be provided to an area, the defect recovery ability of WSI systems under the presented method can be improved, i.e. the yield of the system can be enhanced to a greater extent than conventional subsystem-dividing which is single dimensional.
{"title":"Multi-dimensional subsystem-dividing for yield enhancement in defect-tolerant WSI systems","authors":"N. Tomabechi","doi":"10.1109/DFTVS.1999.802867","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802867","url":null,"abstract":"In designing defect-tolerant WSI systems, introducing subsystem-dividing in which an overall system is divided into subsystems and defect recovery is performed for every subsystem, results in reduced chip area of redundant interconnection lines and reduced delay time through redundant interconnection lines. On the other hand, subsystem-dividing results in reduced defect recovery ability. This paper presents a novel subsystem-dividing method called \"the multi-dimensional subsystem-dividing\", in which a system is divided into subsystems in multiple dimensions, i.e. multiple directions intersecting each other. Since spare circuits from different directions can be provided to an area, the defect recovery ability of WSI systems under the presented method can be improved, i.e. the yield of the system can be enhanced to a greater extent than conventional subsystem-dividing which is single dimensional.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802883
Marco Brera, Fabrizio Ferrandi, D. Sciuto, F. Fummi
This paper describes an approach for enhancing the effectiveness of behavioral test generation by considering high-level and logic synthesis information to increase the correlation between the behavioral fault model and the stuck-at-fault model. In particular we mainly consider two types of information: the mapping between high-level operators and RTL modules and the type of gate level implementation adopted by the RTL modules.
{"title":"Increase the behavioral fault model accuracy using high-level synthesis information","authors":"Marco Brera, Fabrizio Ferrandi, D. Sciuto, F. Fummi","doi":"10.1109/DFTVS.1999.802883","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802883","url":null,"abstract":"This paper describes an approach for enhancing the effectiveness of behavioral test generation by considering high-level and logic synthesis information to increase the correlation between the behavioral fault model and the stuck-at-fault model. In particular we mainly consider two types of information: the mapping between high-level operators and RTL modules and the type of gate level implementation adopted by the RTL modules.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802901
Y. Makris, A. Orailoglu
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process characterization and yield enhancement. At the same time, hierarchical test approaches are becoming the prevalent means for addressing the size and complexity of large designs and for accommodating the varying individual test needs of each design module. In this paper, we discuss a module diagnosis and design-for-debug methodology through hierarchical test paths. Based on debug information inherently attainable from hierarchical test paths, we outline a diagnosis algorithm that identifies the minimal set of faulty module candidates, under the single faulty module model. We further provide a disambiguation rule to ensure unfailing identification of the single faulty module. Low-cost, design-for-debug techniques are subsequently proposed for establishing the disambiguation rule and for providing a module diagnosis capability.
{"title":"A module diagnosis and design-for-debug methodology based on hierarchical test paths","authors":"Y. Makris, A. Orailoglu","doi":"10.1109/DFTVS.1999.802901","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802901","url":null,"abstract":"Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process characterization and yield enhancement. At the same time, hierarchical test approaches are becoming the prevalent means for addressing the size and complexity of large designs and for accommodating the varying individual test needs of each design module. In this paper, we discuss a module diagnosis and design-for-debug methodology through hierarchical test paths. Based on debug information inherently attainable from hierarchical test paths, we outline a diagnosis algorithm that identifies the minimal set of faulty module candidates, under the single faulty module model. We further provide a disambiguation rule to ensure unfailing identification of the single faulty module. Low-cost, design-for-debug techniques are subsequently proposed for establishing the disambiguation rule and for providing a module diagnosis capability.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802868
S. Riley
To estimate yield loss based on data from in-line defect measurements, certain assumptions must be made so the data can be made to fit a given yield model. For the assumptions to be credible, inherent limitations due to detection, review sampling, and classification groupings must be understood and dealt with. Methodologies such as correlations of in-line measurement data to test data can be misinterpreted if issues such as multiple-failed die are not considered. This paper discusses some of the inherent limitations of in-line measurements and how they can affect the intended outcome of yield estimations.
{"title":"Limitations to estimating yield based on in-line defect measurements","authors":"S. Riley","doi":"10.1109/DFTVS.1999.802868","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802868","url":null,"abstract":"To estimate yield loss based on data from in-line defect measurements, certain assumptions must be made so the data can be made to fit a given yield model. For the assumptions to be credible, inherent limitations due to detection, review sampling, and classification groupings must be understood and dealt with. Methodologies such as correlations of in-line measurement data to test data can be misinterpreted if issues such as multiple-failed die are not considered. This paper discusses some of the inherent limitations of in-line measurements and how they can affect the intended outcome of yield estimations.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115102142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802874
Y. Tsiatouhas, T. Haniotakis
A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults.
{"title":"A zero aliasing built-in self test technique for delay fault testing","authors":"Y. Tsiatouhas, T. Haniotakis","doi":"10.1109/DFTVS.1999.802874","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802874","url":null,"abstract":"A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130243968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802869
W. Pleskacz
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.
{"title":"Yield estimation of VLSI circuits with downscaled layouts","authors":"W. Pleskacz","doi":"10.1109/DFTVS.1999.802869","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802869","url":null,"abstract":"This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find a scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows us to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"799 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123006625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802864
J. Segal, S. Bakarian, R. Ross
Monte Carlo critical area extraction routines are controlled by a number of parameters that impact the accuracy and speed of the simulation. In this paper, the effects of the following parameters are explored experimentally: defect shape, rounding of corners in the layout, merging of redundant contacts, consideration of the netlist extracted from layout, and varying the number of defects simulated.
{"title":"Impact of simulation parameters on critical area analysis","authors":"J. Segal, S. Bakarian, R. Ross","doi":"10.1109/DFTVS.1999.802864","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802864","url":null,"abstract":"Monte Carlo critical area extraction routines are controlled by a number of parameters that impact the accuracy and speed of the simulation. In this paper, the effects of the following parameters are explored experimentally: defect shape, rounding of corners in the layout, merging of redundant contacts, consideration of the netlist extracted from layout, and varying the number of defects simulated.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129628757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-01DOI: 10.1109/DFTVS.1999.802866
M. Rudack, D. Niggemeyer
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 /spl mu/m logic/embedded DRAM process. It integrates four processing elements, a total of 16 Mbit DRAM, and application specific interfaces. A hierarchical test strategy has been developed to test the different structures of the system such as processing elements and embedded DRAM. Logic testing is controlled by a fault tolerant BIST controller. The DRAM macrocells are supplied with integrated test facilities and word line redundancy, resulting in a yield of 99.0% for a 4 Mbit DRAM macro. To avoid soft failures, an SEC-DED error correction code (ECC) scheme for the DRAM has been realized. Even though the implementation of the ECC results in an area overhead of about 12%, the overall system yield is not decreased due to the effects of the the ECC on defect tolerance of the memory. The 4 cm/sup 2/ multiprocessor system is suitable for utilization as a building block of a Large Area Integrated Circuit (LAIC).
{"title":"Yield enhancement considerations for a single-chip multiprocessor system with embedded DRAM","authors":"M. Rudack, D. Niggemeyer","doi":"10.1109/DFTVS.1999.802866","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802866","url":null,"abstract":"A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 /spl mu/m logic/embedded DRAM process. It integrates four processing elements, a total of 16 Mbit DRAM, and application specific interfaces. A hierarchical test strategy has been developed to test the different structures of the system such as processing elements and embedded DRAM. Logic testing is controlled by a fault tolerant BIST controller. The DRAM macrocells are supplied with integrated test facilities and word line redundancy, resulting in a yield of 99.0% for a 4 Mbit DRAM macro. To avoid soft failures, an SEC-DED error correction code (ECC) scheme for the DRAM has been realized. Even though the implementation of the ECC results in an area overhead of about 12%, the overall system yield is not decreased due to the effects of the the ECC on defect tolerance of the memory. The 4 cm/sup 2/ multiprocessor system is suitable for utilization as a building block of a Large Area Integrated Circuit (LAIC).","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131226994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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