Microprocessors and Microsystems最新文献

This article studies the ISA-extension and application-specific soft error sensitivity of the RISC-V VeeR EH1 commercial processor core from Western Digital. To this end, a modified VeeRwolf SoC from Chips Alliance was deployed in a Digilent Nexys-A7 FPGA. Then, a fault injection platform was created for injecting soft errors in all architectural and micro-architectural registers of the VeeR EH1, without modifying the original processor core, when executing a set of commonly used space-related algorithms. Errors were categorized according to the consequences that they had on the normal execution of the processor, as well as to the unit of the core they were injected in. By changing compiling targets, four different combinations of RISC-V ISA extensions were also tested and compared, in the same processor IP, for a typical dot product algorithm, a hyperspectral imaging difference calculation and a SHA-256 hash. Experimental results will show how, for each one of these three case studies, the functionally equal binaries issued when compiling these programs using different ISA extensions are affected in different ways by error injections, opening the possibility to selectively compile functions based on a desired reliability/speed factor. The results additionally identify the specific units and subUnits within the processor’s structure that have been affected, pinpointing the exact element where the bitflip occurred, after detecting an error.

To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 $\mu m^2$), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.

This paper presents a scalable, efficient, and real-time intra H.264 video encoder architecture designed for FPGAs. The system achieves up to 2.3 Gbit/s throughput using parallel and pipelined architecture described in VHDL. The architecture prioritizes hardware efficiency, with all modules optimized for minimal resource usage. It proposes a parametrized encoding system and a flexible design with varying size and power requirements. As a baseline, the encoder utilizes 18K logic gates with no compression while the experimental compression ratios up to 2.7 require around 51.5K logic gates. The encoder operates efficiently at frequencies between 115 and 183 MHz. This study is important as it offers a high-speed, hardware-optimized video encoding on FPGA devices. It satisfies the demands of multi-channel encoding applications. Current encoders consume significant hardware resources, constraining the possibility of deploying multiple encoders on a single FPGA device for simultaneous encoding of multiple video channels.

Hyperspectral imagery (HSI) is widely used in remote sensing for target classification; however, its accurate classification remains challenging due to the scarcity of labeled data. Graph Neural Networks (GNNs) have emerged as a popular method for semi-supervised classification, attracting significant interest in the context of HSI analysis. Nevertheless, conventional GNN-based approaches often rely on a single graph filter to extract HSI characteristics, failing to fully exploit the potential benefits of different graph filters. Additionally, oversmoothing issues plague classical GNNs, further affecting classification performance. To address these drawbacks, we propose a novel approach called Spectral and Autoregressive Moving Average Graph Filter for the Multi-Graph Neural Network (SAM-GNN). This approach leverages two distinct graph filters: one specialized in extracting the spectral characteristics of nodes and the other effectively suppressing graph distortion. Through extensive evaluations, we compare the performance of SAM-GNN with other state-of-the-art methods, employing metrics such as overall accuracy (OA), individual class accuracy (IA), and Kappa coefficient (KC). The results shows that the SAM-GNN provides an improvement in KC, IA, and OA of 6.71%, 5.7%, and 3.93% for the Pavia University dataset and 4.67%, 3.67%, and 3.49% for the Cuprite dataset respectively. Furthermore, we implement SAM-GNN on the Virtex-7 field-programmable gate array (FPGA), demonstrating that the method achieves highly accurate target localization results, bringing us closer to real-world applications in HSI classification.

One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an 8 × 8 S-Box is used 16 times. The substitution layer provides confusion and makes the algorithm resistant to cryptanalysis techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing 8 × 8 S-Box on FPGA platforms is considerably higher than other layers of the algorithm. Since S-Boxes are repeatedly used in the algorithm, the cost of the algorithm highly comes from the substitution layer. In 2005, Canright used different extension fields to represent AES S-Box to get FPGA-friendly compact designs. The best optimization proposed by Canright reduced the gate-area of the AES S-Box implementation by 20%.

In this study, we use the same optimization methods that Canright used to optimize AES S-Box on hardware platforms. Our purpose is not to optimize AES S-Box; we aim to create another 8 × 8 S-Box which is strong and compact enough for FPGA platforms. We create an 8 × 8 S-Box using the inverse field operation as in the case of AES S-Box. We use another irreducible polynomial to represent the finite field and get an FPGA-friendly compact and efficient 8 × 8 S-Box. The finite field we propose provides the same level of security against cryptanalysis techniques with a 3.125% less gate-area on Virtex-7 and Artix-7 FPGAs compared to Canright’s results. Moreover, our proposed S-Box requires 11.76% less gate on Virtex-4 FPGAs. These gate-area improvements are beneficial for resource-constraint IoT devices and allow more copies of the S-Box for algorithm parallelism. Therefore, we claim that our proposed S-Box is more compact and efficient than AES S-Box. Cryptographers who need an 8 × 8 S-Box can use our proposed S-Box in their designs instead of AES S-Box with the same level of security but better efficiency.

Internet of things (IoT) gaining more importance due to its crucial role in pervasive computing and also Industry 4.0. Since the number of IoT devices is scaling up to multiple dozens of billions, the importance of energy efficiency is significantly increased. With the consideration of huge variety of IoT device hardware and software, a comprehensive model and estimation methodology on energy consumption is necessary as an enabler. IoT devices are also frequently updated, upgraded and maintained because of the evolving nature of the requirements and market demands. Each and every such operation has an effect on the power consumption and arose the necessity for a new energy consumption modeling and estimation. This process is applicable for development of IoT devices, as well as the maintenance phase. Since the variety of designs is unlimited, and battery capacity is usually fixed, or a cost factor, a generic, fully simulated, model-based energy consumption estimation of IoT devices is crucial. In this study, we aim to address this problem via proposing fully simulated, model-based, system-level power estimation approaches, as well as their success rate in typical real-life scenarios. It can be seen that the proposed methodology has high accuracy over %97. For the realization of the best-proposed approach, we used Open Virtual Platform (OVP) as an instruction set accurate simulator.

In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.

We present the first hardware design that supports operations over the Fano–Elias encoding (FE-encoding). Our design is a combinational circuit (i.e., single clock cycle) that supports insertions, deletions, and queries. FE-encoding allows one to store $f$ binary strings, each of length $\ell +logm$ using a string that is $m+f+f\ell$ bits long (rather than $f(\ell +logm)$). The asymptotic gate-count of the circuit is $\Theta ((m+f)\cdot lgm+f\cdot \ell )$. The asymptotic delay is $\Theta (lgm+lgf+lg\ell )$. We implemented our design on an FPGA with four combinations of parameters in which the FE-encoding fits in 512 or 1024 bits.

We present the first hardware design for a dynamic filter that maintains a set subject to insertions, deletions, and approximate membership queries. The design contains four main blocks: two memory banks that store FE-encodings and two combinational circuits for FE-encoding. Additional logic deals with double buffering and forwarding.

We implemented the dynamic filter on an FPGA with the following parameters: (1) Elements in the dataset are 32-bit strings. (2) The supported dataset can contain up to $n_{max}=45\cdot 2^{14}=737,280$ elements. (3) The latency is 2-4 clock cycles. (4) Fixed (i.e., constant and stable) throughput. A new operation can be issued every clock cycle. (5) We prove that the probability of a false-positive error is bounded by $0.385\cdot 10^{-2}$. (6) We prove that the expected number of insertion failures is less than 1 for every 75 million insertions.

Synthesis of our filter on a Xilinx Alveo U250 FPGA achieves a clock rate of 100 MHz (the critical path is due to the memory access). We measure a fixed throughput of 97.7 million operations per second (the loss of 2.3% in the throughput is due to instabilities in the bandwidth of the AXI4 Lite I/O channel).

A unique feature of our filter implementation is that the throughput is stable and constant for all benchmarks and loads