Microprocessors and Microsystems最新文献_第4页

Implementation and characterization of a fault-tolerant CCSDS 123 hardware accelerator under neutron radiation 中子辐射容错CCSDS 123硬件加速器的实现与特性研究

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-07-30 DOI: 10.1016/j.micpro.2025.105184

Wesley Grignani , Douglas A. Santos , Maria Kastriotou , Carlo Cazzaniga , Luigi Dilillo , Douglas R. Melo

In space applications, remote sensing relies on HSIs (Hyperspectral Images) to capture extensive Earth observation data. However, the substantial data volumes generated by HSIs present significant challenges for onboard storage and processing in space systems, underscoring the importance of efficient compression strategies. Additionally, the harsh conditions of the space environment expose these systems to potential faults, making the integration of fault-tolerant mechanisms crucial for maintaining reliable operation. In this context, this article presents the implementation of a low-cost and fault-tolerant CCSDS 123 HSI compressor. The compressor is present in different configurations employing hardening techniques such as TMR (Triple Modular Redundancy) and Hamming ECC (Error Correcting Code) to mitigate SEUs (Single-Event Upsets). We implemented techniques to enhance observability and evaluated the compressor reliability through fault injection simulations and physical tests at the ChipIr neutron irradiation facility. We present the resource utilization and performance results of each version with a comparative analysis with related work. The results highlight the lowest resource utilization achieved in the unhardened version, capable of processing 20.57 MSa/s and accelerating the application in 24

\times

compared to a software solution. The reliability results demonstrate a high error rate of 97.9% in the unhardened version, significantly reduced in partially hardened versions, with no error propagation in the fully hardened design. Furthermore, we present an analysis of the main components of the accelerator affected by the radiation-induced events observed in the particle accelerator test.

在空间应用中，遥感依靠高光谱图像（hsi）来获取广泛的地球观测数据。然而，hsi产生的大量数据量对空间系统的机载存储和处理提出了重大挑战，强调了有效压缩策略的重要性。此外，空间环境的恶劣条件使这些系统暴露于潜在故障，使得容错机制的集成对于保持可靠运行至关重要。在这种情况下，本文介绍了一种低成本、容错的CCSDS 123 HSI压缩机的实现。压缩机采用不同的配置，采用强化技术，如TMR（三模冗余）和Hamming ECC（纠错码），以减轻SEUs（单事件故障）。通过故障注入模拟和ChipIr中子辐照设施的物理测试，我们实施了增强可观测性的技术，并评估了压缩机的可靠性。我们给出了每个版本的资源利用率和性能结果，并与相关工作进行了比较分析。结果显示，未加固版本的资源利用率最低，处理速度为20.57 MSa/s，与软件解决方案相比，应用程序的速度提高了24倍。可靠性结果表明，在未硬化版本中错误率高达97.9%，在部分硬化版本中显著降低，在完全硬化设计中没有错误传播。此外，我们还分析了粒子加速器试验中观测到的辐射诱导事件对加速器主要部件的影响。

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引用次数: 0

Scala defined hardware generators for Chisel Scala为Chisel定义了硬件生成器

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-07-21 DOI: 10.1016/j.micpro.2025.105182

Martin Schoeberl , Hans Jakob Damsgaard , Luca Pezzarossa , Oliver Keszocze , Erling Rennemo Jellum , Scott Beamer

We describe digital hardware designs in hardware description languages such as VHDL and SystemVerilog. Both languages were developed in the 1980s and, although regularly updated, are still in the style of their time. They lack the constructs to write more configurable generators than just the number of bits for an operation. Based on Scala, Chisel is a hardware construction language that helps to write hardware generators.

Hardware generators are not a new idea. Scripting languages, such as Perl and TCL, are often used to generate VHDL or Verilog code from other sources of system description. However, mixing two languages and embedding VHDL or Verilog strings in generator code is not scalable.

As Chisel is embedded in Scala, we can write the generators using the same language/environment as we use to describe the digital logic. This paper explores different examples and patterns to describe parameterizable hardware generators. We are confident that practices from software development can improve the productivity of hardware designers to build and test the next billion transistor chips.

我们用硬件描述语言如VHDL和SystemVerilog来描述数字硬件设计。这两种语言都是在20世纪80年代发展起来的，尽管定期更新，但仍然保持着当时的风格。它们缺乏编写更多可配置生成器的结构，而不仅仅是操作的位数。Chisel是一种基于Scala的硬件构造语言，可以帮助编写硬件生成器。硬件生成器并不是一个新概念。脚本语言，如Perl和TCL，通常用于从其他系统描述源生成VHDL或Verilog代码。然而，混合两种语言并在生成器代码中嵌入VHDL或Verilog字符串是不可扩展的。由于Chisel嵌入在Scala中，我们可以使用与描述数字逻辑相同的语言/环境来编写生成器。本文探讨了不同的例子和模式来描述可参数化的硬件生成器。我们相信，软件开发的实践可以提高硬件设计人员的生产力，以构建和测试下一个十亿晶体管芯片。

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引用次数: 0

Real-time neural network-based thermal stress compensation for pressure sensors in precision localization systems 基于实时神经网络的精密定位系统压力传感器热应力补偿

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-07-07 DOI: 10.1016/j.micpro.2025.105183

Paola Vitolo , Rosalba Liguori , Luigi Di Benedetto , Alfredo Rubino , Danilo Pau , Gian Domenico Licciardo

This article presents a real-time Artificial Intelligence-based Reconfigurable Self-Calibration Unit (AI-ReSCU) for piezoresistive MEMS pressure sensors, designed to mitigate long-term drift effects induced by thermal stress. The system integrates a compact and reconfigurable neural network to dynamically estimate and correct sensor inaccuracies with minimal energy and area overhead. The architecture comprises a trigger module for detecting deviations from nominal behavior and a compensation engine driven by a quantized neural network optimized for hardware efficiency. The network processes temporal input windows and operates using 24-bit activations and 1-bit weights, enabling real-time inference with ultra-low power consumption. The fully digital system was prototyped in STMicroelectronics’ BCD8 technology, occupying 0.55 mm² and achieving a dynamic power consumption of 4.46 nW under typical conditions, thanks to extensive resource reuse and clock gating strategies. Offline experimental validation on LPS22HH pressure sensors demonstrated the system’s ability to recover up to 1.6 hPa of drift-induced error with a recovery latency of approximately 50 input samples, while maintaining measurement deviations within ±0.5 hPa across multiple stress scenarios.

本文介绍了一种用于压阻式MEMS压力传感器的基于人工智能的实时可重构自校准单元（AI-ReSCU），旨在减轻热应力引起的长期漂移效应。该系统集成了一个紧凑且可重构的神经网络，以最小的能量和面积开销动态估计和纠正传感器的不准确性。该体系结构包括一个用于检测偏离标称行为的触发模块和一个由优化硬件效率的量化神经网络驱动的补偿引擎。该网络处理临时输入窗口，并使用24位激活和1位权重进行操作，从而以超低功耗实现实时推理。全数字系统的原型采用意法半导体的BCD8技术，占地0.55 mm2，在典型条件下，由于广泛的资源重用和时钟门控策略，动态功耗为4.46 nW。在LPS22HH压力传感器上进行的离线实验验证表明，该系统能够恢复高达1.6 hPa的漂移误差，恢复延迟约为50个输入样本，同时在多种应力情况下保持±0.5 hPa的测量偏差。

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引用次数: 0

High throughput DLP and mixed radix based architectures of Viterbi decoder 高吞吐量DLP和基于混合基数的维特比解码器架构

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-06-23 DOI: 10.1016/j.micpro.2025.105181

Mohamed Asan Basiri M.

Viterbi decoders play an important role in digital communication. This manuscript proposes two high throughput VLSI architectures of Viterbi decoder. In the first proposed architecture, the data level parallelism (DLP) based Viterbi decoder of rate

\frac{1}{N}

can be used to perform 1, 2, 4, 8, …parallel decodings of rates

\frac{1}{N}

,

\frac{1}{(N / 2)}

,

\frac{1}{(N / 4)}

,

\frac{1}{(N / 8)}

, …respectively. The second proposed mixed radix Viterbi decoder architecture is to perform four numbers of radix-

2^{k - 1}

decodings in parallel using one radix-

2^{k}

Viterbi decoder, where

k \geq 1

. All the conventional and proposed Viterbi decoders are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the proposed designs achieve high throughput as compared with the conventional designs. According to the synthesis results, the proposed mixed radix-2&4 decoder achieves 73.9% of improvement in maximum throughput as compared with the conventional radix-4 design.

维特比解码器在数字通信中起着重要的作用。本文提出了两种高吞吐量Viterbi译码器的VLSI架构。在第一种结构中，基于数据级并行（DLP）的1N速率的Viterbi解码器可以分别进行速率为1N、1（N/2）、1（N/4）、1（N/8）、…的1、2、4、8、…的并行解码。第二种提出的混合基数Viterbi解码器架构是使用一个基数2k的Viterbi解码器并行执行四个数的基数2k−1解码，其中k≥1。所有传统的和提出的维特比解码器都是使用Cadence在45纳米CMOS技术上实现的。综合结果表明，与传统设计相比，所提出的设计具有较高的通量。综合结果表明，所提出的混合radix-2&；4解码器与传统的radix-4设计相比，最大吞吐量提高了73.9%。

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引用次数: 0

High throughput event filtering: The interpolation-based DIF algorithm hardware architecture 高吞吐量事件过滤：基于插值的DIF算法硬件架构

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-06-11 DOI: 10.1016/j.micpro.2025.105171

Marcin Kowalczyk, Tomasz Kryjak

In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.

近年来，事件视觉领域得到了迅速发展。它既体现在技术方面，随着越来越好的事件传感器的出现，也体现在算法方面，随着越来越多的技术应用的提出和科学论文的发表。然而，来自这些传感器的数据流通常包含大量的噪声，这取决于诸如观察场景中的照明程度或传感器的温度等因素。我们提出了一种基于距离的频率权重插值（DIF）滤波器的硬件架构，并在FPGA上实现。为了评估算法并将其与其他解决方案进行比较，我们准备了一个新的高分辨率事件数据集，我们也向社区发布了该数据集。我们的架构在传感器分辨率为1280 × 720时实现了每秒40339万事件（MEPS）的吞吐量，在分辨率为640 × 480时实现了428.45 MEPS。接收器工作特性下面积（AUROC）指数的平均值从0.844到0.999不等，具体取决于数据集，这与最先进的滤波解决方案相当，但在大范围的噪声水平下具有更高的吞吐量和更好的操作。

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引用次数: 0

Evaluating the performance of TinyML singular and ensemble techniques for intrusion detection in IoT networks 评估TinyML奇异和集成技术在物联网网络中入侵检测的性能

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-06-03 DOI: 10.1016/j.micpro.2025.105172

Abderahmane Hamdouchi , Ali Idri

As the Internet of Things (IoT) expands, safeguarding IoT networks from vulnerabilities becomes critical. Intrusion detection systems (IDS) leveraging machine learning (ML) techniques are essential for enhancing security and preventing unauthorized access. However, transmitting data to the cloud can introduce latency, impeding real-time attack detection. This research evaluates three TinyML ensemble techniques (random forest, XGBoost, and extra trees) and three singular techniques (decision tree, Gaussian naive Bayes, and multilayer perceptron) using two feature selection methods (maximum relevance minimum redundancy and analysis of variance) on the NF-ToN-IoT-v2 and NF-BoT-IoT-v2 datasets for cyberattack detection. Evaluations on the Arduino UNO used the prediction performance criteria (Cohen’s kappa and Matthew’s correlation coefficient), device metrics (latency, static RAM, and flash memory), and the Scott-Knott test and Borda count voting system to assess the statistical significance and to rank the models. Results show that singular TinyML models outperformed ensemble models for multiclass classification in the IDS-IoT context. The best models are: (1) MLP with 20 features and a hidden layer size of 56 for NF-ToN-IoT-v2; and (2) ET with 13 features, 2 estimators, and a tree depth of 16 for NF-BoT-IoT-v2.

随着物联网（IoT）的扩展，保护物联网网络免受漏洞的侵害变得至关重要。利用机器学习（ML）技术的入侵检测系统（IDS）对于增强安全性和防止未经授权的访问至关重要。然而，将数据传输到云可能会引入延迟，从而阻碍实时攻击检测。本研究评估了三种TinyML集成技术（随机森林、XGBoost和额外树）和三种奇异技术（决策树、高斯朴素贝叶斯和多层感知器），使用两种特征选择方法（最大相关最小冗余和方差分析）在NF-ToN-IoT-v2和NF-BoT-IoT-v2数据集上进行网络攻击检测。对Arduino UNO的评估使用了预测性能标准（Cohen’s kappa和Matthew’s相关系数）、设备指标（延迟、静态RAM和闪存）、Scott-Knott测试和Borda计数投票系统来评估统计显著性并对模型进行排名。结果表明，在IDS-IoT环境下，单一TinyML模型在多类分类方面优于集成模型。最佳模型是：(1)NF-ToN-IoT-v2的MLP具有20个特征，隐藏层大小为56；(2) NF-BoT-IoT-v2的ET具有13个特征，2个估计器，树深度为16。

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引用次数: 0

A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications 基于多路复用器的可重构PUF和TRNG设计，用于保护物联网应用

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-05-30 DOI: 10.1016/j.micpro.2025.105170

Zhiyuan Pan , Jiafeng Cheng , Nengyuan Sun , Jinghe Wang , Kai Shi , Jianghong Li , Zhaoyi Niu , Jiaqi Wang , Jiawei Zhang , Linhan Wang , Weize Yu

Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) are two important hardware security primitives in modern cryptography. A regular arbiter PUF can be broken by machine learning (ML) attacks without much effort since a high linear relationship exists between the input data and the output response of the PUF. In this paper, an ML-resistant reconfigurable PUF and TRNG (RePT) architecture is proposed for the first time. Within this RePT design, a non-linearization technique by masking the linear relationship between the input data and the output response is proposed to greatly reinforce the robustness of an arbiter PUF against ML attacks without significantly increasing its area and power overhead. So as to further reuse the existing hardware resource within the arbiter PUF to build another hardware security primitive: TRNG, a novel algorithm is proposed to efficiently determine the selection signal value of each multiplexer within the arbiter PUF. As shown in the result, the proposed RePT design is able to achieve a 38 Mbps PUF (260 Mbps TRNG) throughput with 32,621

μ

m

^{2}

area, under the synthesis of SMIC 55 nm process design kits (PDK). Additionally, when ML attacks are performed on the proposed RePT circuit, it cannot be cracked even if 100,000 training data are enabled.

物理不可克隆函数（PUF）和真随机数生成器（TRNG）是现代密码学中两个重要的硬件安全原语。由于PUF的输入数据和输出响应之间存在高度线性关系，因此机器学习（ML）攻击可以毫不费力地破坏常规的仲裁PUF。本文首次提出了一种抗ml的可重构PUF和TRNG （RePT）体系结构。在这个RePT设计中，提出了一种非线性化技术，通过掩盖输入数据和输出响应之间的线性关系，大大增强了仲裁PUF对ML攻击的鲁棒性，而不会显着增加其面积和功率开销。为了进一步重用仲裁PUF内的现有硬件资源，构建另一种硬件安全原语：TRNG，提出了一种新的算法来有效地确定仲裁PUF内各多路复用器的选择信号值。结果表明，在中芯国际55纳米工艺设计套件（PDK）的合成下，所提出的RePT设计能够在32,621 μm2的面积上实现38 Mbps的PUF （260 Mbps的TRNG）吞吐量。此外，当对建议的RePT电路进行ML攻击时，即使启用100,000个训练数据也无法破解。

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引用次数: 0

STRATUM project: AI-based point of care computing for neurosurgical 3D decision support tools STRATUM项目：基于人工智能的神经外科三维决策支持工具护理点计算

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-05-14 DOI: 10.1016/j.micpro.2025.105157

Himar Fabelo , Raquel Leon , Emanuele Torti , Santiago Marco , Asaf Badouh , Max Verbers , Carlos Vega , Javier Santana-Nunez , Yann Falevoz , Yolanda Ramallo-Fariña , Christian Weis , Ana M Wägner , Eduardo Juarez , Claudio Rial , Alfonso Lagares , Gustav Burström , Francesco Leporati , Luis Jimenez-Roldan , Elisa Marenzi , Teresa Cervero , Gustavo M. Callico

Integrated digital diagnostics are transforming complex surgical procedures, with brain tumour surgery being among the most challenging. STRATUM, a five-year Horizon Europe-funded project, aims to develop an advanced 3D decision support system leveraging real-time multimodal data processing powered by artificial intelligence. A key innovation of STRATUM is its design as an energy-efficient Point-of-Care computing system, seamlessly integrated into neurosurgical workflows. This system will provide surgeons with real-time, AI-driven insights, enhancing decision-making accuracy and efficiency. By optimizing surgical precision and reducing procedure duration, STRATUM is expected to improve patient outcomes while streamlining resource utilization within European healthcare systems.

综合数字诊断正在改变复杂的外科手术，脑肿瘤手术是最具挑战性的手术之一。STRATUM是一项为期五年的Horizon欧洲资助项目，旨在开发一种先进的3D决策支持系统，利用人工智能驱动的实时多模式数据处理。STRATUM的一个关键创新是它作为一个节能的护理点计算系统的设计，无缝集成到神经外科工作流程中。该系统将为外科医生提供实时的、人工智能驱动的见解，提高决策的准确性和效率。通过优化手术精度和缩短手术时间，STRATUM有望改善患者的结果，同时简化欧洲医疗保健系统内的资源利用。

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引用次数: 0

AAL-based smart cane system with security and privacy features for blind and visually impaired individuals 基于人工智能的智能手杖系统，为盲人和视障人士提供安全和隐私功能

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-04-24 DOI: 10.1016/j.micpro.2025.105155

Kyriaki Tsantikidou, Grigorios Delimpaltadakis, Damianos Diasakos, Nicolas Sklavos

Ambient Assisted Living (AAL) technologies aim at increasing the quality of life for people with impairments. Practicality, reliability, autonomy, ease-of-use, safety, and low cost are of the utmost importance and in some cases omitted or overlooked by the research community. In this paper, an AAL-based smart cane system with security and privacy features for blind and visually impaired individuals that aims at satisfying these requirements is proposed. Multiple services that facilitate the everyday life for both indoor and outdoor activities are implemented: obstacle detection for ground and head level via ultrasonic (US) sensors and vibrations, ascending and descending stair detection/recognition via computer vision, image processing through various sensors, an emergency button for additional safety, and a LoRa antenna with a security and privacy mechanism for safely communicating with the Health 4.0-based environment. The proposed system is implemented with an Arduino and Raspberry Pi Zero combination and provides more practical and economic services compared to other published related works, including head-level detection, an indoor-outdoor adjustment switch and security mechanisms that are in most cases dismissed. It achieves a 7.4 % accuracy increase for general obstacle detection and a 100 % consistent drop or wall detection accuracy compared to published works. The proposed system presents a 37.82 % increase of speed-adjusted recall and a 24.4 % performance increase in its stair detection feature compared to published works. It focuses on hardware efficiency, safety and real-world autonomy with cost efficient alternatives. The proposed architecture of the security mechanism achieves a small area consumption, minimum of 35.6 % decrease compared to published designs, and an efficient throughput, that is appropriate with the utilized antenna.

环境辅助生活（AAL）技术旨在提高残疾人的生活质量。实用性、可靠性、自主性、易用性、安全性和低成本是最重要的，在某些情况下被研究界忽略或忽视。本文针对这些需求，提出了一种基于人工智能的盲人和视障人士安全隐私智能手杖系统。实现了多种便利室内和室外日常生活的服务：通过超声波（US）传感器和振动对地面和头部进行障碍物检测，通过计算机视觉对上下楼梯进行检测/识别，通过各种传感器进行图像处理，用于额外安全的紧急按钮，以及具有安全和隐私机制的LoRa天线，用于与基于Health 4.0的环境进行安全通信。该系统采用Arduino和Raspberry Pi Zero的组合实现，与其他已发表的相关作品相比，该系统提供了更实用、更经济的服务，包括头位检测、室内外调节开关和安全机制，这些在大多数情况下都被忽略了。与已发表的作品相比，它在一般障碍物检测方面的准确率提高了7.4%，并且在跌落或墙壁检测方面的准确率达到了100%。与已发表的作品相比，该系统的速度调整召回率提高了37.82%，楼梯检测功能的性能提高了24.4%。它专注于硬件效率、安全性和具有成本效益替代方案的现实世界自主性。所提出的安全机制架构实现了较小的面积消耗，与已发表的设计相比至少减少了35.6%，并且具有与所使用的天线相适应的高效吞吐量。

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引用次数: 0

A novel machine learning-driven optimization methodology for faster and more efficient design space exploration in high-level synthesis 一种新的机器学习驱动的优化方法，用于在高级综合中更快、更有效的设计空间探索

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-04-16 DOI: 10.1016/j.micpro.2025.105154

Esra Celik, Deniz Dal

The optimization of digital circuits is a critical factor in determining the competitiveness of modern electronic systems, particularly in terms of area, performance, and power consumption. High-Level Synthesis (HLS) plays a pivotal role in this optimization process, enabling designers to define system requirements at a higher level of abstraction and providing opportunities to analyze and optimize digital circuits against various metrics prior to production. However, the design constraints inherent in the HLS process often lead to multi-objective optimization problems, which significantly complicate the exploration process. This complexity necessitates the development of novel synthesis methodologies enabling faster and more efficient design space exploration. In response to this need, within the scope of this study, we introduced an innovative and hybrid HLS methodology that combines metaheuristic and machine learning approaches. In this respect, two distinct synthesis tools were developed. The first tool, implemented in C++, utilizes the Simulated Annealing (SA) metaheuristic with a novel three-part solution representation. This representation, a key contribution of our study, aims to minimize the weighted sum of latency and area constraints for Data Flow Graph (DFG) designs. While effective, this approach resulted in extended execution times due to computationally intensive design variables. To address the performance bottleneck identified in the standard cost function evaluation, we developed a second tool that integrates machine learning with the traditional SA. This hybrid approach combines C++ and Python, incorporating a Support Vector Regression (SVR) model to estimate solution costs more efficiently, significantly reducing execution times. Our study also presents the detailed analyses of the experimental results conducted on seven benchmarks with varying node counts. The three-part solution representation in the traditional SA approach demonstrated up to a 53.38% improvement in performance compared to the single-part representation across all benchmarks. For benchmarks with fewer nodes (DiffEq, Lattice, Ellip, and FEWF), the model-based estimation implementation achieved results identical to the traditional approach but required longer execution times. For benchmarks characterized by higher node counts (MatMul, IntAux, and MCM), our novel approach demonstrated equivalent results to the traditional SA implementation with a time savings of up to 129 seconds. We leveraged these time savings to enhance the exploration process, achieving up to 5.4% improvement in solution quality without exceeding the execution time of the traditional approach.

数字电路的优化是决定现代电子系统竞争力的关键因素，特别是在面积、性能和功耗方面。高级综合（HLS）在优化过程中起着关键作用，使设计人员能够在更高的抽象层次上定义系统需求，并提供在生产之前根据各种指标分析和优化数字电路的机会。然而，HLS过程中固有的设计约束往往导致多目标优化问题，这大大复杂化了勘探过程。这种复杂性要求开发新的合成方法，以实现更快、更有效的设计空间探索。为了满足这一需求，在本研究的范围内，我们引入了一种创新的混合HLS方法，该方法结合了元启发式和机器学习方法。在这方面，开发了两种不同的合成工具。第一个工具是用c++实现的，它利用模拟退火（SA）元启发式算法和一种新颖的三部分解表示。这种表示是我们研究的一个关键贡献，旨在最小化数据流图（DFG）设计的延迟和面积约束的加权总和。这种方法虽然有效，但由于计算密集的设计变量，导致执行时间延长。为了解决在标准成本函数评估中发现的性能瓶颈，我们开发了第二种工具，将机器学习与传统SA集成在一起。这种混合方法结合了c++和Python，结合了支持向量回归（SVR）模型来更有效地估计解决方案的成本，大大减少了执行时间。我们的研究还详细分析了在七个具有不同节点计数的基准上进行的实验结果。在所有基准测试中，与单部分表示相比，传统SA方法中的三部分解决方案表示的性能提高了53.38%。对于节点较少的基准测试（DiffEq、Lattice、Ellip和FEWF），基于模型的估计实现获得了与传统方法相同的结果，但需要更长的执行时间。对于具有较高节点计数特征的基准测试（MatMul、inaux和MCM），我们的新方法证明了与传统SA实现相当的结果，并且节省了高达129秒的时间。我们利用这些节省的时间来增强勘探过程，在不超过传统方法执行时间的情况下，将解决方案质量提高了5.4%。

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