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Retraction notice to “Business English visualization system based on video surveillance and the internet of things” [Microprocessors and Microsystems 80 (2021) 103639] 基于视频监控和物联网的商务英语可视化系统》撤稿通知 [Microprocessors and Microsystems 80 (2021) 103639]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2024-01-04 DOI: 10.1016/j.micpro.2023.104996
Xiaolei Qin
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引用次数: 0
A Micro-architecture that supports the Fano–Elias encoding and a hardware accelerator for approximate membership queries 支持 Fano-Elias 编码的微体系结构和用于近似成员查询的硬件加速器
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2024-01-03 DOI: 10.1016/j.micpro.2023.104992
Guy Even, Gabriel Marques Domingues
<div><p><span>We present the first hardware design that supports operations over the Fano–Elias encoding (FE-encoding). Our design is a combinational circuit (i.e., single clock cycle) that supports insertions, deletions, and queries. FE-encoding allows one to store </span><span><math><mi>f</mi></math></span> binary strings, each of length <span><math><mrow><mi>ℓ</mi><mo>+</mo><mo>log</mo><mi>m</mi></mrow></math></span> using a string that is <span><math><mrow><mi>m</mi><mo>+</mo><mi>f</mi><mo>+</mo><mi>f</mi><mi>ℓ</mi></mrow></math></span> bits long (rather than <span><math><mrow><mi>f</mi><mrow><mo>(</mo><mi>ℓ</mi><mo>+</mo><mo>log</mo><mi>m</mi><mo>)</mo></mrow></mrow></math></span>). The asymptotic gate-count of the circuit is <span><math><mrow><mi>Θ</mi><mrow><mo>(</mo><mrow><mo>(</mo><mi>m</mi><mo>+</mo><mi>f</mi><mo>)</mo></mrow><mi>⋅</mi><mo>lg</mo><mi>m</mi><mo>+</mo><mi>f</mi><mi>⋅</mi><mi>ℓ</mi><mo>)</mo></mrow></mrow></math></span>. The asymptotic delay is <span><math><mrow><mi>Θ</mi><mrow><mo>(</mo><mo>lg</mo><mi>m</mi><mo>+</mo><mo>lg</mo><mi>f</mi><mo>+</mo><mo>lg</mo><mi>ℓ</mi><mo>)</mo></mrow></mrow></math></span><span>. We implemented our design on an FPGA with four combinations of parameters in which the FE-encoding fits in 512 or 1024 bits.</span></p><p>We present the first hardware design for a dynamic filter that maintains a set subject to insertions, deletions, and approximate membership queries. The design contains four main blocks: two memory banks that store FE-encodings and two combinational circuits for FE-encoding. Additional logic deals with double buffering and forwarding.</p><p>We implemented the dynamic filter on an FPGA with the following parameters: (1) Elements in the dataset are 32-bit strings. (2) The supported dataset can contain up to <span><math><mrow><msub><mrow><mi>n</mi></mrow><mrow><mi>m</mi><mi>a</mi><mi>x</mi></mrow></msub><mo>=</mo><mn>45</mn><mi>⋅</mi><msup><mrow><mn>2</mn></mrow><mrow><mn>14</mn></mrow></msup><mo>=</mo><mn>737</mn><mo>,</mo><mn>280</mn></mrow></math></span> elements. (3) The latency is 2-4 clock cycles. (4) Fixed (i.e., constant and stable) throughput. A new operation can be issued <em>every</em> clock cycle. (5) We prove that the probability of a false-positive error is bounded by <span><math><mrow><mn>0</mn><mo>.</mo><mn>385</mn><mi>⋅</mi><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></math></span>. (6) We prove that the expected number of insertion failures is less than 1 for every 75 million insertions.</p><p>Synthesis of our filter on a Xilinx Alveo U250 FPGA achieves a clock rate of 100 MHz (the critical path is due to the memory access). We measure a fixed throughput of 97.7 million operations per second (the loss of 2.3% in the throughput is due to instabilities in the bandwidth of the AXI4 Lite I/O channel).</p><p>A unique feature of our filter implementation is that the throughput is stable and constant for all benchmarks and loads
我们首次提出了支持对 Fano-Elias 编码（FE-encoding）进行操作的硬件设计。我们的设计是一个组合电路（即单时钟周期），支持插入、删除和查询。FE-encoding 允许使用 m+f+fℓ 位长（而不是 f(ℓ+logm)）的字符串来存储 f 个二进制字符串，每个字符串的长度为 ℓ+logm 。电路的渐近门数为Θ((m+f)⋅lgm+f⋅ℓ)。渐近延迟为 Θ(lgm+lgf+lgℓ)。我们在 FPGA 上用四种参数组合实现了我们的设计，其中 FE 编码适合 512 位或 1024 位。我们首次提出了动态滤波器的硬件设计，该滤波器可在插入、删除和近似成员查询的情况下维护一个集合。该设计包含四个主要模块：两个存储 FE 编码的内存库和两个用于 FE 编码的组合电路。我们在 FPGA 上实现了动态过滤器，参数如下：(1) 数据集中的元素是 32 位字符串。(2) 支持的数据集最多可包含 nmax=45⋅214=737 280 个元素。(3) 延迟为 2-4 个时钟周期。(4) 固定（即恒定稳定）的吞吐量。每个时钟周期可发出一个新操作。(5) 我们证明，假阳性错误的概率边界为 0.385⋅10-2 (6) 我们证明，每 7,500 万次插入中，插入失败的预期次数小于 1 次。在 Xilinx Alveo U250 FPGA 上合成我们的滤波器，可实现 100 MHz 的时钟速率（关键路径是内存访问）。我们测得的固定吞吐量为每秒 9770 万次操作（由于 AXI4 Lite I/O 通道带宽的不稳定性，吞吐量损失了 2.3%）。也就是说，操作的组合不会影响吞吐量，吞吐量也不取决于数据集的元素数量（只要数据集的卡入度以 nmax 为界）。以前在软件中实现的动态滤波器（在 x86 或 GPU 上实现）并没有表现出稳定恒定的吞吐量。
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FE-encoding allows one to store &lt;/span&gt;&lt;span&gt;&lt;math&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;/math&gt;&lt;/span&gt; binary strings, each of length &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;log&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; using a string that is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; bits long (rather than &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;log&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;). The asymptotic gate-count of the circuit is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;Θ&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;. The asymptotic delay is &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;Θ&lt;/mi&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;f&lt;/mi&gt;&lt;mo&gt;+&lt;/mo&gt;&lt;mo&gt;lg&lt;/mo&gt;&lt;mi&gt;ℓ&lt;/mi&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;&lt;span&gt;. We implemented our design on an FPGA with four combinations of parameters in which the FE-encoding fits in 512 or 1024 bits.&lt;/span&gt;&lt;/p&gt;&lt;p&gt;We present the first hardware design for a dynamic filter that maintains a set subject to insertions, deletions, and approximate membership queries. The design contains four main blocks: two memory banks that store FE-encodings and two combinational circuits for FE-encoding. Additional logic deals with double buffering and forwarding.&lt;/p&gt;&lt;p&gt;We implemented the dynamic filter on an FPGA with the following parameters: (1) Elements in the dataset are 32-bit strings. (2) The supported dataset can contain up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;n&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;mi&gt;a&lt;/mi&gt;&lt;mi&gt;x&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;mo&gt;=&lt;/mo&gt;&lt;mn&gt;45&lt;/mn&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mn&gt;14&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mo&gt;=&lt;/mo&gt;&lt;mn&gt;737&lt;/mn&gt;&lt;mo&gt;,&lt;/mo&gt;&lt;mn&gt;280&lt;/mn&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; elements. (3) The latency is 2-4 clock cycles. (4) Fixed (i.e., constant and stable) throughput. A new operation can be issued &lt;em&gt;every&lt;/em&gt; clock cycle. (5) We prove that the probability of a false-positive error is bounded by &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mn&gt;0&lt;/mn&gt;&lt;mo&gt;.&lt;/mo&gt;&lt;mn&gt;385&lt;/mn&gt;&lt;mi&gt;⋅&lt;/mi&gt;&lt;mn&gt;1&lt;/mn&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mn&gt;0&lt;/mn&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mo&gt;−&lt;/mo&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;. (6) We prove that the expected number of insertion failures is less than 1 for every 75 million insertions.&lt;/p&gt;&lt;p&gt;Synthesis of our filter on a Xilinx Alveo U250 FPGA achieves a clock rate of 100 MHz (the critical path is due to the memory access). We measure a fixed throughput of 97.7 million operations per second (the loss of 2.3% in the throughput is due to instabilities in the bandwidth of the AXI4 Lite I/O channel).&lt;/p&gt;&lt;p&gt;A unique feature of our filter implementation is that the throughput is stable and constant for all benchmarks and loads","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 104992"},"PeriodicalIF":2.6,"publicationDate":"2024-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
H2-RAID: Improving the reliability of SSD RAID with unified SSD and HDD hybrid architecture H2-RAID：利用统一的 SSD 和 HDD 混合架构提高 SSD RAID 的可靠性
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-30 DOI: 10.1016/j.micpro.2023.104993
Jiarong Liu , Tianyu Wang , Xiaowei Chen , Chao Li , Zhaoyan Shen , Zhiyong Zhang

With the increasing development of SSD (Solid-State Drives) technology, SSD RAID (Redundant Arrays of Independent Disks) has been widely deployed in enterprise data centers. However, the inherent write endurance issue of SSD seriously affects the reliability of the array. Meanwhile, compared with conventional HDD-based RAID, SSD RAID exhibits very different failure characteristics, such as correlated failure (Balakrishnan et al., 2010) under RAID-5. In this paper, we present a Hybrid High reliability RAID architecture, named H2-RAID, by equipping each SSD with an extra HDD as the backup to improve the reliability of SSD RAID. Considering the relatively longer write latency of HDD, in H2-RAID, we first propose an HDD-aware backup mechanism to smartly aggregate random writes into sequential writes to decrease performance degradation. In addition, to cope with the scenarios of SSD failure, an HDD-aware reconstruction method is further proposed to guarantee the reliability and the online transaction processing performance. We build a novel Markov process-based mathematical model to analyze the reliability of different architectures, and the theoretical results prove the reliability of H2-RAID is much higher than that of traditional SSD RAID. To more accurately evaluate the performance influence of HDD on H2-RAID, we develop a simulator based on Disksim and the experimental results show H2-RAID significantly increases the reliability compared with SSD array (under RAID-5) while with little performance loss on average.

随着 SSD（固态硬盘）技术的不断发展，SSD RAID（独立磁盘冗余阵列）已在企业数据中心得到广泛部署。然而，固态硬盘固有的写入耐用性问题严重影响了阵列的可靠性。同时，与传统的基于 HDD 的 RAID 相比，SSD RAID 表现出截然不同的故障特征，如 RAID-5 下的相关故障（Balakrishnan 等人，2010 年）。在本文中，我们提出了一种混合高可靠性 RAID 架构，命名为 H2-RAID，为每个固态硬盘配备一个额外的硬盘作为备份，以提高固态硬盘 RAID 的可靠性。考虑到硬盘的写入延迟相对较长，在H2-RAID中，我们首先提出了一种硬盘感知备份机制，将随机写入巧妙地聚合为顺序写入，以减少性能下降。此外，为了应对固态硬盘失效的情况，我们还进一步提出了一种硬盘感知重构方法，以保证可靠性和在线事务处理性能。我们建立了基于马尔可夫过程的新型数学模型来分析不同架构的可靠性，理论结果证明 H2-RAID 的可靠性远高于传统的 SSD RAID。为了更准确地评估硬盘对 H2-RAID 性能的影响，我们开发了基于 Disksim 的模拟器，实验结果表明 H2-RAID 比 SSD 阵列（RAID-5 下）显著提高了可靠性，而平均性能损失很小。
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引用次数: 0
Retraction notice to “Intelligent control for new topological structure of Z-Source inverter based on ARM” [Microprocessors and Microsystems 81 (2021) 103735] 基于 ARM 的新型 Z 源逆变器拓扑结构的智能控制》的撤稿通知 [Microprocessors and Microsystems 81 (2021) 103735]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-29 DOI: 10.1016/j.micpro.2023.105001
Hailong Liu , Jiaona Chen
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引用次数: 0
Retraction notice to “Searching and Learning English Translation Long Text Information Based on Heterogeneous Multiprocessors and Data Mining” [Microprocessors and Microsystems 82 (2021) 103895] 基于异构多处理器和数据挖掘的英语翻译长文本信息检索与学习》撤稿通知 [Microprocessors and Microsystems 82 (2021) 103895]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.104999
Xiaoping Shen, Runjuan Qin
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引用次数: 0
Retraction notice to “An Improved Multilayer Perceptron Approach for Detecting Sugarcane Yield Production in IoT based Smart Agriculture” [Microprocessors and Microsystems 82 (2021) 103822] 基于物联网的智能农业中检测甘蔗产量的改进型多层感知器方法》的撤稿通知 [Microprocessors and Microsystems 82 (2021) 103822]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.105002
Pengwen Wang , Behzad Aalipur Hafshejani , Daluyo Wang
{"title":"Retraction notice to “An Improved Multilayer Perceptron Approach for Detecting Sugarcane Yield Production in IoT based Smart Agriculture” [Microprocessors and Microsystems 82 (2021) 103822]","authors":"Pengwen Wang ,&nbsp;Behzad Aalipur Hafshejani ,&nbsp;Daluyo Wang","doi":"10.1016/j.micpro.2023.105002","DOIUrl":"10.1016/j.micpro.2023.105002","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105002"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002478/pdfft?md5=1d09b24d1f85f13f20bcd14dc9cd77a4&pid=1-s2.0-S0141933123002478-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Retraction notice to ‘Medical IoT system platform and elderly patients’ femoral shaft fracture nursing’ 医疗物联网系统平台与老年患者股骨干骨折护理》撤稿通知：[Microprocessors and Microsystems 82 (2021) 103868].
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.105004
Weiwei Liu, Kun Yao
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引用次数: 0
Retraction notice to “Design of Embedded Digital Image Processing System Based on Zynq” [Microprocessors and Microsystems 83 (2021) 104005] 基于 Zynq 的嵌入式数字图像处理系统设计》的撤稿通知 [Microprocessors and Microsystems 83 (2021) 104005]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.105000
Jin Liu , Jie Feng
{"title":"Retraction notice to “Design of Embedded Digital Image Processing System Based on Zynq” [Microprocessors and Microsystems 83 (2021) 104005]","authors":"Jin Liu ,&nbsp;Jie Feng","doi":"10.1016/j.micpro.2023.105000","DOIUrl":"https://doi.org/10.1016/j.micpro.2023.105000","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105000"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002454/pdfft?md5=fc43d609d3947e2d3675906cbcfae5c8&pid=1-s2.0-S0141933123002454-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139099687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Retraction notice to “Optimization of Storage Location Assignment in Automated Warehouse” [Microprocessors and Microsystems 80 (2021)103356] 自动化仓库中存储位置分配的优化》撤稿通知 [Microprocessors and Microsystems 80 (2021)103356]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.104995
Dong Yang, Yaohua Wu, Wenkai Ma
{"title":"Retraction notice to “Optimization of Storage Location Assignment in Automated Warehouse” [Microprocessors and Microsystems 80 (2021)103356]","authors":"Dong Yang,&nbsp;Yaohua Wu,&nbsp;Wenkai Ma","doi":"10.1016/j.micpro.2023.104995","DOIUrl":"10.1016/j.micpro.2023.104995","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 104995"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0141933123002405/pdfft?md5=f0cb971216adb835910ff83a554c37a2&pid=1-s2.0-S0141933123002405-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Retraction notice to “Design of Sino–Japanese cross border e-commerce platform based on FPGA and data mining ” [Microprocessors and Microsystems 80 (2021) 103360] 基于 FPGA 和数据挖掘的中日跨境电商平台设计》撤稿通知 [Microprocessors and Microsystems 80 (2021) 103360]
IF 2.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Microprocessors and Microsystems
Pub Date : 2023-12-28 DOI: 10.1016/j.micpro.2023.105003
Lai Junfang , Cai Shan
{"title":"Retraction notice to “Design of Sino–Japanese cross border e-commerce platform based on FPGA and data mining ” [Microprocessors and Microsystems 80 (2021) 103360]","authors":"Lai Junfang ,&nbsp;Cai Shan","doi":"10.1016/j.micpro.2023.105003","DOIUrl":"10.1016/j.micpro.2023.105003","url":null,"abstract":"","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"104 ","pages":"Article 105003"},"PeriodicalIF":2.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S014193312300248X/pdfft?md5=6c680e4b66cc6fe4d1fb38f873f03b02&pid=1-s2.0-S014193312300248X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139094373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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