Microprocessors and Microsystems最新文献

{"title":"A reconfigurable PUF and TRNG design based on multiplexers for securing IoT applications","authors":"Zhiyuan Pan ,&nbsp;Jiafeng Cheng ,&nbsp;Nengyuan Sun ,&nbsp;Jinghe Wang ,&nbsp;Kai Shi ,&nbsp;Jianghong Li ,&nbsp;Zhaoyi Niu ,&nbsp;Jiaqi Wang ,&nbsp;Jiawei Zhang ,&nbsp;Linhan Wang ,&nbsp;Weize Yu","doi":"10.1016/j.micpro.2025.105170","DOIUrl":"10.1016/j.micpro.2025.105170","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) are two important hardware security primitives in modern cryptography. A regular arbiter PUF can be broken by machine learning (ML) attacks without much effort since a high linear relationship exists between the input data and the output response of the PUF. In this paper, an ML-resistant reconfigurable PUF and TRNG (RePT) architecture is proposed for the first time. Within this RePT design, a non-linearization technique by masking the linear relationship between the input data and the output response is proposed to greatly reinforce the robustness of an arbiter PUF against ML attacks without significantly increasing its area and power overhead. So as to further reuse the existing hardware resource within the arbiter PUF to build another hardware security primitive: TRNG, a novel algorithm is proposed to efficiently determine the selection signal value of each multiplexer within the arbiter PUF. As shown in the result, the proposed RePT design is able to achieve a 38 Mbps PUF (260 Mbps TRNG) throughput with 32,621 <span><math><mi>μ</mi></math></span>m<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> area, under the synthesis of SMIC 55 nm process design kits (PDK). Additionally, when ML attacks are performed on the proposed RePT circuit, it cannot be cracked even if 100,000 training data are enabled.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"116 ","pages":"Article 105170"},"PeriodicalIF":1.9,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144189866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"STRATUM project: AI-based point of care computing for neurosurgical 3D decision support tools","authors":"Himar Fabelo ,&nbsp;Raquel Leon ,&nbsp;Emanuele Torti ,&nbsp;Santiago Marco ,&nbsp;Asaf Badouh ,&nbsp;Max Verbers ,&nbsp;Carlos Vega ,&nbsp;Javier Santana-Nunez ,&nbsp;Yann Falevoz ,&nbsp;Yolanda Ramallo-Fariña ,&nbsp;Christian Weis ,&nbsp;Ana M Wägner ,&nbsp;Eduardo Juarez ,&nbsp;Claudio Rial ,&nbsp;Alfonso Lagares ,&nbsp;Gustav Burström ,&nbsp;Francesco Leporati ,&nbsp;Luis Jimenez-Roldan ,&nbsp;Elisa Marenzi ,&nbsp;Teresa Cervero ,&nbsp;Gustavo M. Callico","doi":"10.1016/j.micpro.2025.105157","DOIUrl":"10.1016/j.micpro.2025.105157","url":null,"abstract":"<div><div>Integrated digital diagnostics are transforming complex surgical procedures, with brain tumour surgery being among the most challenging. STRATUM, a five-year Horizon Europe-funded project, aims to develop an advanced 3D decision support system leveraging real-time multimodal data processing powered by artificial intelligence. A key innovation of STRATUM is its design as an energy-efficient Point-of-Care computing system, seamlessly integrated into neurosurgical workflows. This system will provide surgeons with real-time, AI-driven insights, enhancing decision-making accuracy and efficiency. By optimizing surgical precision and reducing procedure duration, STRATUM is expected to improve patient outcomes while streamlining resource utilization within European healthcare systems.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"116 ","pages":"Article 105157"},"PeriodicalIF":1.9,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel machine learning-driven optimization methodology for faster and more efficient design space exploration in high-level synthesis","authors":"Esra Celik,&nbsp;Deniz Dal","doi":"10.1016/j.micpro.2025.105154","DOIUrl":"10.1016/j.micpro.2025.105154","url":null,"abstract":"<div><div>The optimization of digital circuits is a critical factor in determining the competitiveness of modern electronic systems, particularly in terms of area, performance, and power consumption. High-Level Synthesis (HLS) plays a pivotal role in this optimization process, enabling designers to define system requirements at a higher level of abstraction and providing opportunities to analyze and optimize digital circuits against various metrics prior to production. However, the design constraints inherent in the HLS process often lead to multi-objective optimization problems, which significantly complicate the exploration process. This complexity necessitates the development of novel synthesis methodologies enabling faster and more efficient design space exploration. In response to this need, within the scope of this study, we introduced an innovative and hybrid HLS methodology that combines metaheuristic and machine learning approaches. In this respect, two distinct synthesis tools were developed. The first tool, implemented in C++, utilizes the Simulated Annealing (SA) metaheuristic with a novel three-part solution representation. This representation, a key contribution of our study, aims to minimize the weighted sum of latency and area constraints for Data Flow Graph (DFG) designs. While effective, this approach resulted in extended execution times due to computationally intensive design variables. To address the performance bottleneck identified in the standard cost function evaluation, we developed a second tool that integrates machine learning with the traditional SA. This hybrid approach combines C++ and Python, incorporating a Support Vector Regression (SVR) model to estimate solution costs more efficiently, significantly reducing execution times. Our study also presents the detailed analyses of the experimental results conducted on seven benchmarks with varying node counts. The three-part solution representation in the traditional SA approach demonstrated up to a 53.38% improvement in performance compared to the single-part representation across all benchmarks. For benchmarks with fewer nodes (DiffEq, Lattice, Ellip, and FEWF), the model-based estimation implementation achieved results identical to the traditional approach but required longer execution times. For benchmarks characterized by higher node counts (MatMul, IntAux, and MCM), our novel approach demonstrated equivalent results to the traditional SA implementation with a time savings of up to 129 seconds. We leveraged these time savings to enhance the exploration process, achieving up to 5.4% improvement in solution quality without exceeding the execution time of the traditional approach.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"114 ","pages":"Article 105154"},"PeriodicalIF":1.9,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143881824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AAL-based smart cane system with security and privacy features for blind and visually impaired individuals","authors":"Kyriaki Tsantikidou,&nbsp;Grigorios Delimpaltadakis,&nbsp;Damianos Diasakos,&nbsp;Nicolas Sklavos","doi":"10.1016/j.micpro.2025.105155","DOIUrl":"10.1016/j.micpro.2025.105155","url":null,"abstract":"<div><div>Ambient Assisted Living (AAL) technologies aim at increasing the quality of life for people with impairments. Practicality, reliability, autonomy, ease-of-use, safety, and low cost are of the utmost importance and in some cases omitted or overlooked by the research community. In this paper, an AAL-based smart cane system with security and privacy features for blind and visually impaired individuals that aims at satisfying these requirements is proposed. Multiple services that facilitate the everyday life for both indoor and outdoor activities are implemented: obstacle detection for ground and head level via ultrasonic (US) sensors and vibrations, ascending and descending stair detection/recognition via computer vision, image processing through various sensors, an emergency button for additional safety, and a LoRa antenna with a security and privacy mechanism for safely communicating with the Health 4.0-based environment. The proposed system is implemented with an Arduino and Raspberry Pi Zero combination and provides more practical and economic services compared to other published related works, including head-level detection, an indoor-outdoor adjustment switch and security mechanisms that are in most cases dismissed. It achieves a 7.4 % accuracy increase for general obstacle detection and a 100 % consistent drop or wall detection accuracy compared to published works. The proposed system presents a 37.82 % increase of speed-adjusted recall and a 24.4 % performance increase in its stair detection feature compared to published works. It focuses on hardware efficiency, safety and real-world autonomy with cost efficient alternatives. The proposed architecture of the security mechanism achieves a small area consumption, minimum of 35.6 % decrease compared to published designs, and an efficient throughput, that is appropriate with the utilized antenna.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"114 ","pages":"Article 105155"},"PeriodicalIF":1.9,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143906800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform","authors":"Luca Zulberti ,&nbsp;Matteo Monopoli ,&nbsp;Pietro Nannipieri ,&nbsp;Silvia Moranti ,&nbsp;Geert Thys ,&nbsp;Luca Fanucci","doi":"10.1016/j.micpro.2025.105142","DOIUrl":"10.1016/j.micpro.2025.105142","url":null,"abstract":"&lt;div&gt;&lt;div&gt;With the increasing use of satellites, rovers, and other space exploration devices, Artificial Intelligence (AI) is also becoming an important tool for space exploration, allowing autonomous decision-making and operations in harsh environments. As a result, there is an increasing demand for reliable and energy-efficient processing platforms in the space industry. Among all processing architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are becoming popular, particularly in data-intensive applications like machine learning, demonstrating a substantial improvement in the energy efficiency of inference operations while preserving a good degree of versatility. In high-level class space missions, the hardware platforms incorporate radiation-hardened Field Programmable Gate Arrays (FPGAs) and microcontrollers, which do not meet the performance requirements for the aforementioned AI applications. The use of CGRA architectures in space missions is still not widely studied. The main contribution of this work is a comprehensive Design Space Exploration (DSE) activity with our highly parameterized CGRA architecture, exploring the costs associated with various design parameters when targeting AI in the space domain. We evaluated performance, power consumption, and area occupation after synthesis on the radiation-hardened DARE65T standard cell library developed by imec, based on a commercial 65 nm technology process. We characterize different CGRA configurations, comparing them with state-of-the-art solutions used for the acceleration of the AI algorithms. This work highlights Performance, Power, and Area (PPA) results that range from &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;100&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;MHz&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; (up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;600&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;MOps&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;), &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;2.43&lt;/mi&gt;&lt;mo&gt;×&lt;/mo&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;10&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;4&lt;/mi&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mstyle&gt;&lt;mstyle&gt;&lt;mi&gt;μ&lt;/mi&gt;&lt;/mstyle&gt;&lt;/mstyle&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;2&lt;/mi&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; cell area occupation and &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;0.699&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;mW&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; power consumption, to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;625&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;MHz&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; (up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;3.75&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;GOps&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;), &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;2.43&lt;/mi&gt;&lt;mo&gt;×&lt;/mo&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;10&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;5&lt;/mi&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mstyle&gt;&lt;mstyle&gt;&lt;mi&gt;μ&lt;/mi&gt;&lt;/mstyle&gt;&lt;/mstyle&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;2&lt;/mi&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mo&gt;,&lt;/mo&gt;&lt;mi&gt;46.5&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;mW&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;. During DSE activity, we highlight the optimal solutions in terms of area efficiency (up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;313.1&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;GOps/mm&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;2&lt;/mi&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;) and energy efficiency (up to &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;289&lt;/mi&gt;&lt;mspace&gt;&lt;/mspace&gt;&lt;mi&gt;GOps/W&lt;/mi&gt;&lt;/","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105142"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143180785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review on hardware accelerators for convolutional neural network-based inference engines: Strategies for performance and energy-efficiency enhancement","authors":"Deepika S․ ,&nbsp;Arunachalam V․ ,&nbsp;Alex Noel Joseph Raj","doi":"10.1016/j.micpro.2025.105146","DOIUrl":"10.1016/j.micpro.2025.105146","url":null,"abstract":"<div><div>In time-critical &amp; safety-critical image classification applications, Convolutional Neural Networks (CNNs) based Inference Engines (IEs) are preferred and required to be fast, accurate, and cost-effective to meet the market demands. The self-feature extraction capabilities use millions of parameters and neurons in the stack of layers with restricted processing time. This paper reviews strategies applied in Hardware-based image classification CNN inference engines. The acceleration strategies are (1) Arithmetic Logic Unit (ALU)-based, (2) Data flow-based, and (3) Sparsity-based are considered here. Considering benchmark accuracy, the 16-bit mixed fixed/floating point could provide 99 % and 3.75 times more performance than Half-precision floating point in an application-specific CNN model. Feeding 2-dimensional or 3-dimensional data frames to the CNN layers would reuse the data. It optimizes the volume of memory usage and improves the efficiency of the processor array. The pruning of zero/near-zero valued Input Feature Maps (IFMs) and weights leads to sparsity in the data fed to the different layers. Therefore, data compression strategies and skipping the trivial computation (zero skipping approach) would reduce the complexity of the controller. There is a benchmark performance improvement of 1.17 times and 6.2 times in power efficiency compared to dense architecture. Minimizing the complexity of indexing and load balancing controller would improve the performance further.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105146"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143510725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Open-source ROS-based simulation for verification of FPGA robotics applications","authors":"Rubén Nieto ,&nbsp;Felipe Machado ,&nbsp;Jesús Fernández-Conde ,&nbsp;David Lobato ,&nbsp;José M. Cañas","doi":"10.1016/j.micpro.2025.105143","DOIUrl":"10.1016/j.micpro.2025.105143","url":null,"abstract":"<div><div>FPGAs are increasingly incorporated in many high-end robotics applications, often involving computer vision and motor control. However, functional verification of FPGA designs is labor-intensive, time-consuming, and consequently expensive. Moreover, validation of complex systems, such as robots, poses even further challenges because neither the external interactions can be easily modeled with traditional testbenches nor the robot’s response can be adequately observed and ascertained. This work presents a new methodology that validates the robot’s behavior in a realistic simulated environment before transferring the design to the physical robot and the onboard FPGA. This methodology allows integral, fast, and flexible debugging cycles of robotics applications by integrating the functional simulation of the processing unit (FPGA) with the simulation of the robot, its environment, and their mutual interconnections. The Verilator simulation tool is used for fast Verilog/SystemVerilog verification and simulation. ROS, the standard robotics middleware, and Gazebo 3D robotics simulator are used for realistic robot simulation, including a robust physics engine. We have implemented several open-source software extensions to interconnect the Verilog circuit with the simulated ROS sensors and actuators. This methodology’s utility and correctness have been assessed by developing a complete proof-of-concept FPGA-based robotics application in which a commercial robot follows a colored object using its onboard camera and differential drive motors. This work establishes the foundations for developing and testing complex robot FPGA-based modules more efficiently and flexibly.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105143"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143428214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A cost-effective design for a mid-range microcontroller-based lock-in amplifier","authors":"Ignacio Horcas ,&nbsp;David Moreno-Salinas ,&nbsp;José Sánchez-Moreno","doi":"10.1016/j.micpro.2025.105145","DOIUrl":"10.1016/j.micpro.2025.105145","url":null,"abstract":"<div><div>Lock-in amplifiers are instruments widely used in physics and engineering laboratories, whose invention goes back to the 1940s. Due to the late electronic developments, the former analog implementations have been replaced with digital versions, mainly based on FPGAs (field-programmable gate arrays). The present work, exploiting the last advances in the microcontrollers field, consists in the development of a functional prototype of a low-cost lock-in amplifier based on a microcontroller with similar specifications to mid-range commercial amplifiers. The performance of the prototype has been tested and compared with commercial devices, showing a similar performance in common use cases at a much reduced cost.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105145"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143453911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A real-time interception system for compromised frequency-hopping signal eavesdropping","authors":"Corentin Lavaud ,&nbsp;Robin Gerzaguet ,&nbsp;Matthieu Gautier ,&nbsp;Olivier Berder ,&nbsp;Erwan Nogues ,&nbsp;Stephane Molton","doi":"10.1016/j.micpro.2025.105144","DOIUrl":"10.1016/j.micpro.2025.105144","url":null,"abstract":"<div><div>In modern computing architectures, sensitive data (<em>red data</em>) is carried out in the same processing units as encrypted data (<em>black data</em>). Due to leaks (internal mixing, coupling …), this red data can be emitted in a legitimate radio transmission through a so-called telecom side-channel. This new type of side-channel creates an important threat as it can be passively and remotely processed by a dedicated interception system. This threat becomes even more concerning within the context of the Internet of Things, as the use of low-cost components leads to increased leaks. This paper addresses telecom side-channels on frequency-hopping signals, that are harsh to eavesdrop due to their sporadic nature in both time and frequency domains. To that goal, a wideband interception system is proposed, able to intercept frequency-hopping signals in real time and to extract sensitive red data from it. The system relies on software-defined radios and leverages both hardware and software resources to process a 200MHz bandwidth in real time. The proposed architecture is capable of detecting jumps on the order of <span><math><mrow><mn>20</mn><mi>μ</mi><mi>s</mi></mrow></math></span> and can therefore track 50,000 jumps per second across 1,024 channels. Finally, the criticality of telecom side-channels in Bluetooth communications is demonstrated through real interception on several microcontroller chips.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105144"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143463740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware implementation of a high-resolution auto-tuned time-frequency signal analyzer over TMS320C6713 DSK using a compact support polynomial kernel","authors":"Ibrahim Lantri ,&nbsp;Mansour Abed ,&nbsp;Adel Belouchrani","doi":"10.1016/j.micpro.2025.105141","DOIUrl":"10.1016/j.micpro.2025.105141","url":null,"abstract":"<div><div>This paper explores the hardware implementation of an embedded time-frequency signal analyzer using the Polynomial Cheriet-Belouchrani Distribution (PCBD) with a compact kernel. We implemented this distribution on a Texas Instruments TMS320C6713 Digital Signal Processing Starter Kit (DSK). Compared to other quadratic time-frequency distributions (TFDs), the PCBD requires a low computational cost due to its compact support nature, which reduces the number of points needing calculation. The sole smoothing parameter <em>γ</em> that controls its kernel's bandwidth is an integer, simplifying the unsupervised approach. To ensure that the realized TF analyzer is automatically tuned, an accurate low-complexity performance measure must be employed to achieve optimal concentration, resolution, and cross-term suppression. Failure to do so may result in missing or degraded essential signal characteristics. The Stankovic measure has been identified as the preferred measure among many others for finding the optimal value of the integer <em>γ</em>. We have also been exploring methods to optimize the execution of various algorithms by taking advantage of specific mathematical properties inherent in the compact polynomial kernel and the PCBD. Additionally, we propose a recursive method to minimize the computation cost associated with the discrete PCB kernel. These strategies are designed to enhance efficiency and reduce the required machine cycles. To compare the performances provided, we thoroughly evaluate the numerical complexity of our implemented distribution, both with and without mathematical optimization. The findings obtained demonstrate the effectiveness of using the TMS320C6713 DSK board to design a high-resolution auto-tuned time-frequency signal analyzer. We not only achieved a perfect match with the results obtained from MATLAB, but the optimized approach also reduced runtime by approximately 19 % to 47 % compared to the direct method, depending on the input signal length and the number of loops required to optimize the Stankovic measure. A comparative analysis was also conducted to assess the effectiveness of our approach in relation to other linear and quadratic TF analyzers, including those implemented on field-programmable gate arrays (FPGAs).</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105141"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143179736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}