Pub Date : 2025-03-01DOI: 10.1016/j.micpro.2025.105146
Deepika S․ , Arunachalam V․ , Alex Noel Joseph Raj
In time-critical & safety-critical image classification applications, Convolutional Neural Networks (CNNs) based Inference Engines (IEs) are preferred and required to be fast, accurate, and cost-effective to meet the market demands. The self-feature extraction capabilities use millions of parameters and neurons in the stack of layers with restricted processing time. This paper reviews strategies applied in Hardware-based image classification CNN inference engines. The acceleration strategies are (1) Arithmetic Logic Unit (ALU)-based, (2) Data flow-based, and (3) Sparsity-based are considered here. Considering benchmark accuracy, the 16-bit mixed fixed/floating point could provide 99 % and 3.75 times more performance than Half-precision floating point in an application-specific CNN model. Feeding 2-dimensional or 3-dimensional data frames to the CNN layers would reuse the data. It optimizes the volume of memory usage and improves the efficiency of the processor array. The pruning of zero/near-zero valued Input Feature Maps (IFMs) and weights leads to sparsity in the data fed to the different layers. Therefore, data compression strategies and skipping the trivial computation (zero skipping approach) would reduce the complexity of the controller. There is a benchmark performance improvement of 1.17 times and 6.2 times in power efficiency compared to dense architecture. Minimizing the complexity of indexing and load balancing controller would improve the performance further.
{"title":"A review on hardware accelerators for convolutional neural network-based inference engines: Strategies for performance and energy-efficiency enhancement","authors":"Deepika S․ , Arunachalam V․ , Alex Noel Joseph Raj","doi":"10.1016/j.micpro.2025.105146","DOIUrl":"10.1016/j.micpro.2025.105146","url":null,"abstract":"<div><div>In time-critical & safety-critical image classification applications, Convolutional Neural Networks (CNNs) based Inference Engines (IEs) are preferred and required to be fast, accurate, and cost-effective to meet the market demands. The self-feature extraction capabilities use millions of parameters and neurons in the stack of layers with restricted processing time. This paper reviews strategies applied in Hardware-based image classification CNN inference engines. The acceleration strategies are (1) Arithmetic Logic Unit (ALU)-based, (2) Data flow-based, and (3) Sparsity-based are considered here. Considering benchmark accuracy, the 16-bit mixed fixed/floating point could provide 99 % and 3.75 times more performance than Half-precision floating point in an application-specific CNN model. Feeding 2-dimensional or 3-dimensional data frames to the CNN layers would reuse the data. It optimizes the volume of memory usage and improves the efficiency of the processor array. The pruning of zero/near-zero valued Input Feature Maps (IFMs) and weights leads to sparsity in the data fed to the different layers. Therefore, data compression strategies and skipping the trivial computation (zero skipping approach) would reduce the complexity of the controller. There is a benchmark performance improvement of 1.17 times and 6.2 times in power efficiency compared to dense architecture. Minimizing the complexity of indexing and load balancing controller would improve the performance further.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105146"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143510725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-19DOI: 10.1016/j.micpro.2025.105145
Ignacio Horcas , David Moreno-Salinas , José Sánchez-Moreno
Lock-in amplifiers are instruments widely used in physics and engineering laboratories, whose invention goes back to the 1940s. Due to the late electronic developments, the former analog implementations have been replaced with digital versions, mainly based on FPGAs (field-programmable gate arrays). The present work, exploiting the last advances in the microcontrollers field, consists in the development of a functional prototype of a low-cost lock-in amplifier based on a microcontroller with similar specifications to mid-range commercial amplifiers. The performance of the prototype has been tested and compared with commercial devices, showing a similar performance in common use cases at a much reduced cost.
{"title":"A cost-effective design for a mid-range microcontroller-based lock-in amplifier","authors":"Ignacio Horcas , David Moreno-Salinas , José Sánchez-Moreno","doi":"10.1016/j.micpro.2025.105145","DOIUrl":"10.1016/j.micpro.2025.105145","url":null,"abstract":"<div><div>Lock-in amplifiers are instruments widely used in physics and engineering laboratories, whose invention goes back to the 1940s. Due to the late electronic developments, the former analog implementations have been replaced with digital versions, mainly based on FPGAs (field-programmable gate arrays). The present work, exploiting the last advances in the microcontrollers field, consists in the development of a functional prototype of a low-cost lock-in amplifier based on a microcontroller with similar specifications to mid-range commercial amplifiers. The performance of the prototype has been tested and compared with commercial devices, showing a similar performance in common use cases at a much reduced cost.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105145"},"PeriodicalIF":1.9,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143453911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In modern computing architectures, sensitive data (red data) is carried out in the same processing units as encrypted data (black data). Due to leaks (internal mixing, coupling …), this red data can be emitted in a legitimate radio transmission through a so-called telecom side-channel. This new type of side-channel creates an important threat as it can be passively and remotely processed by a dedicated interception system. This threat becomes even more concerning within the context of the Internet of Things, as the use of low-cost components leads to increased leaks. This paper addresses telecom side-channels on frequency-hopping signals, that are harsh to eavesdrop due to their sporadic nature in both time and frequency domains. To that goal, a wideband interception system is proposed, able to intercept frequency-hopping signals in real time and to extract sensitive red data from it. The system relies on software-defined radios and leverages both hardware and software resources to process a 200MHz bandwidth in real time. The proposed architecture is capable of detecting jumps on the order of and can therefore track 50,000 jumps per second across 1,024 channels. Finally, the criticality of telecom side-channels in Bluetooth communications is demonstrated through real interception on several microcontroller chips.
{"title":"A real-time interception system for compromised frequency-hopping signal eavesdropping","authors":"Corentin Lavaud , Robin Gerzaguet , Matthieu Gautier , Olivier Berder , Erwan Nogues , Stephane Molton","doi":"10.1016/j.micpro.2025.105144","DOIUrl":"10.1016/j.micpro.2025.105144","url":null,"abstract":"<div><div>In modern computing architectures, sensitive data (<em>red data</em>) is carried out in the same processing units as encrypted data (<em>black data</em>). Due to leaks (internal mixing, coupling …), this red data can be emitted in a legitimate radio transmission through a so-called telecom side-channel. This new type of side-channel creates an important threat as it can be passively and remotely processed by a dedicated interception system. This threat becomes even more concerning within the context of the Internet of Things, as the use of low-cost components leads to increased leaks. This paper addresses telecom side-channels on frequency-hopping signals, that are harsh to eavesdrop due to their sporadic nature in both time and frequency domains. To that goal, a wideband interception system is proposed, able to intercept frequency-hopping signals in real time and to extract sensitive red data from it. The system relies on software-defined radios and leverages both hardware and software resources to process a 200MHz bandwidth in real time. The proposed architecture is capable of detecting jumps on the order of <span><math><mrow><mn>20</mn><mi>μ</mi><mi>s</mi></mrow></math></span> and can therefore track 50,000 jumps per second across 1,024 channels. Finally, the criticality of telecom side-channels in Bluetooth communications is demonstrated through real interception on several microcontroller chips.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105144"},"PeriodicalIF":1.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143463740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1016/j.micpro.2025.105143
Rubén Nieto , Felipe Machado , Jesús Fernández-Conde , David Lobato , José M. Cañas
FPGAs are increasingly incorporated in many high-end robotics applications, often involving computer vision and motor control. However, functional verification of FPGA designs is labor-intensive, time-consuming, and consequently expensive. Moreover, validation of complex systems, such as robots, poses even further challenges because neither the external interactions can be easily modeled with traditional testbenches nor the robot’s response can be adequately observed and ascertained. This work presents a new methodology that validates the robot’s behavior in a realistic simulated environment before transferring the design to the physical robot and the onboard FPGA. This methodology allows integral, fast, and flexible debugging cycles of robotics applications by integrating the functional simulation of the processing unit (FPGA) with the simulation of the robot, its environment, and their mutual interconnections. The Verilator simulation tool is used for fast Verilog/SystemVerilog verification and simulation. ROS, the standard robotics middleware, and Gazebo 3D robotics simulator are used for realistic robot simulation, including a robust physics engine. We have implemented several open-source software extensions to interconnect the Verilog circuit with the simulated ROS sensors and actuators. This methodology’s utility and correctness have been assessed by developing a complete proof-of-concept FPGA-based robotics application in which a commercial robot follows a colored object using its onboard camera and differential drive motors. This work establishes the foundations for developing and testing complex robot FPGA-based modules more efficiently and flexibly.
{"title":"Open-source ROS-based simulation for verification of FPGA robotics applications","authors":"Rubén Nieto , Felipe Machado , Jesús Fernández-Conde , David Lobato , José M. Cañas","doi":"10.1016/j.micpro.2025.105143","DOIUrl":"10.1016/j.micpro.2025.105143","url":null,"abstract":"<div><div>FPGAs are increasingly incorporated in many high-end robotics applications, often involving computer vision and motor control. However, functional verification of FPGA designs is labor-intensive, time-consuming, and consequently expensive. Moreover, validation of complex systems, such as robots, poses even further challenges because neither the external interactions can be easily modeled with traditional testbenches nor the robot’s response can be adequately observed and ascertained. This work presents a new methodology that validates the robot’s behavior in a realistic simulated environment before transferring the design to the physical robot and the onboard FPGA. This methodology allows integral, fast, and flexible debugging cycles of robotics applications by integrating the functional simulation of the processing unit (FPGA) with the simulation of the robot, its environment, and their mutual interconnections. The Verilator simulation tool is used for fast Verilog/SystemVerilog verification and simulation. ROS, the standard robotics middleware, and Gazebo 3D robotics simulator are used for realistic robot simulation, including a robust physics engine. We have implemented several open-source software extensions to interconnect the Verilog circuit with the simulated ROS sensors and actuators. This methodology’s utility and correctness have been assessed by developing a complete proof-of-concept FPGA-based robotics application in which a commercial robot follows a colored object using its onboard camera and differential drive motors. This work establishes the foundations for developing and testing complex robot FPGA-based modules more efficiently and flexibly.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105143"},"PeriodicalIF":1.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143428214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.micpro.2024.105130
Borja Losa , Pablo Parra , Antonio Da Silva , Óscar R. Polo , J. Ignacio G. Tejedor , Agustín Martínez , Sebastián Sánchez , David Guzmán
The increasing complexity of real-time embedded critical systems has driven the adoption of new methodologies to mitigate high development costs. One of the most common approaches is the implementation of mixed-criticality systems, characterized by integrating applications with different levels of criticality on the same processing unit. In these systems, applications run on a separation kernel hypervisor, a software element that controls the execution of the different operating systems, providing a virtualized environment and ensuring the necessary spatial and temporal isolation. This paper presents the design and implementation of hardware virtualization extensions for LEON processors, whose use is widespread in the field of space systems. These extensions enable the execution of virtualized applications with minimal transitions to the hypervisor, enhancing system performance. Our proposed solution defines a specific execution mode and duplicates control and status registers for the exclusive use of virtualized applications. In addition, the functionality of the hardware and software interrupt signals has been extended, allowing developers to select which ones are handled by the hypervisor and which ones by the guest operating systems directly. We have implemented the proposed extension using the LEON version 3 processor’s original VHDL code, and validated it using exhaustive tests to evaluate performance and resource consumption. The results show that the proposed modifications allow virtualized applications to execute without hypervisor intervention, matching the performance when non-virtualized while significantly outperforming existing para-virtualization solutions. Resource consumption increases by 6% to 14%, depending on the FPGA, which is low when compared to available resources. Power consumption increases by only a few milliwatts, which can be considered negligible.
{"title":"Hardware-assisted virtualization extensions for LEON processors in mixed-criticality systems","authors":"Borja Losa , Pablo Parra , Antonio Da Silva , Óscar R. Polo , J. Ignacio G. Tejedor , Agustín Martínez , Sebastián Sánchez , David Guzmán","doi":"10.1016/j.micpro.2024.105130","DOIUrl":"10.1016/j.micpro.2024.105130","url":null,"abstract":"<div><div>The increasing complexity of real-time embedded critical systems has driven the adoption of new methodologies to mitigate high development costs. One of the most common approaches is the implementation of mixed-criticality systems, characterized by integrating applications with different levels of criticality on the same processing unit. In these systems, applications run on a separation kernel hypervisor, a software element that controls the execution of the different operating systems, providing a virtualized environment and ensuring the necessary spatial and temporal isolation. This paper presents the design and implementation of hardware virtualization extensions for LEON processors, whose use is widespread in the field of space systems. These extensions enable the execution of virtualized applications with minimal transitions to the hypervisor, enhancing system performance. Our proposed solution defines a specific execution mode and duplicates control and status registers for the exclusive use of virtualized applications. In addition, the functionality of the hardware and software interrupt signals has been extended, allowing developers to select which ones are handled by the hypervisor and which ones by the guest operating systems directly. We have implemented the proposed extension using the LEON version 3 processor’s original VHDL code, and validated it using exhaustive tests to evaluate performance and resource consumption. The results show that the proposed modifications allow virtualized applications to execute without hypervisor intervention, matching the performance when non-virtualized while significantly outperforming existing para-virtualization solutions. Resource consumption increases by 6% to 14%, depending on the FPGA, which is low when compared to available resources. Power consumption increases by only a few milliwatts, which can be considered negligible.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"112 ","pages":"Article 105130"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the era of modern global design supply chain, the emergence of hardware threats is on the rise. Conventional hardware security techniques may fall short in terms of offering inferior tamper tolerance, unpersuasive digital ownership proof and weaker entropy, for sturdy intellectual property (IP) piracy detection and seamless IP ownership conflict resolution process. This paper presents a novel hardware security methodology based on IP seller's amino acid biometric and facial anthropometric features to generate an encrypted fused signature using multi-key driven non-invertible fingerprint, for providing sturdy detective countermeasure against IP piracy. The proposed approach exploits AES framework, where the generated key-translated fingerprint minutiae points of the IP seller is used as an encryption key. The proposed methodology is highly robust against hardware threats as it capable to generate large size covert security constraints for embedding, as digital evidence, in the IP design during high level synthesis (HLS). The results of the proposed approach on comparison with existing approaches, indicates enhanced tamper tolerance ability (against brute force attack) of upto 1.15E+77, lower probability of coincidence or false positive (against ghost signature search attack) of upto 6.72E-06, and stronger entropy of upto 2.06E-138, respectively.
{"title":"Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature","authors":"Anirban Sengupta, Aditya Anshul, Ayush Kumar Singh","doi":"10.1016/j.micpro.2024.105131","DOIUrl":"10.1016/j.micpro.2024.105131","url":null,"abstract":"<div><div>In the era of modern global design supply chain, the emergence of hardware threats is on the rise. Conventional hardware security techniques may fall short in terms of offering inferior tamper tolerance, unpersuasive digital ownership proof and weaker entropy, for sturdy intellectual property (IP) piracy detection and seamless IP ownership conflict resolution process. This paper presents a novel hardware security methodology based on IP seller's amino acid biometric and facial anthropometric features to generate an encrypted fused signature using multi-key driven non-invertible fingerprint, for providing sturdy detective countermeasure against IP piracy. The proposed approach exploits AES framework, where the generated key-translated fingerprint minutiae points of the IP seller is used as an encryption key. The proposed methodology is highly robust against hardware threats as it capable to generate large size covert security constraints for embedding, as digital evidence, in the IP design during high level synthesis (HLS). The results of the proposed approach on comparison with existing approaches, indicates enhanced tamper tolerance ability (against brute force attack) of upto 1.15E+77, lower probability of coincidence or false positive (against ghost signature search attack) of upto 6.72E-06, and stronger entropy of upto 2.06E-138, respectively.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"112 ","pages":"Article 105131"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.micpro.2024.105132
Miguel Jiménez Arribas, Agustín Martínez Hellín, Manuel Prieto Mateo, Iván Gamino del Río, Andrea Fernández Gallego, Óscar Rodríguez Polo, Antonio da Silva, Pablo Parra, Sebastián Sánchez
The ability to collect statistics about the execution of a program within a CPU is of the utmost importance across all fields of computing since it allows characterizing the timing performance of a program. This capability is even more relevant in safety-critical software systems, where it is mandatory to analyze the software timing requirements to ensure the correct operation of the programs. Moreover, in order to properly evaluate and verify the extra-functional properties of these systems, besides timing performance, there are many other statistics available on a CPU, such as those associated with its resource utilization. In this paper, we showcase a Performance Measurement Unit (PMU), also known as a Hardware Performance Monitor (HPM), integrated into a RISC-V On-Board Computer (OBC) designed for space applications by our research group. The monitoring technique features a novel approach whereby the events triggered are not counted immediately but instead are propagated through the pipeline so that their annotation is synchronized with the executed instruction. Additionally, we also demonstrate the use of this PMU in a process to characterize the execution model of the processor. Finally, as an example of the statistics provided by the PMU, the results obtained running the CoreMark and Dhrystone benchmarks on the RISC-V OBC are shown.
{"title":"Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor","authors":"Miguel Jiménez Arribas, Agustín Martínez Hellín, Manuel Prieto Mateo, Iván Gamino del Río, Andrea Fernández Gallego, Óscar Rodríguez Polo, Antonio da Silva, Pablo Parra, Sebastián Sánchez","doi":"10.1016/j.micpro.2024.105132","DOIUrl":"10.1016/j.micpro.2024.105132","url":null,"abstract":"<div><div>The ability to collect statistics about the execution of a program within a CPU is of the utmost importance across all fields of computing since it allows characterizing the timing performance of a program. This capability is even more relevant in safety-critical software systems, where it is mandatory to analyze the software timing requirements to ensure the correct operation of the programs. Moreover, in order to properly evaluate and verify the extra-functional properties of these systems, besides timing performance, there are many other statistics available on a CPU, such as those associated with its resource utilization. In this paper, we showcase a Performance Measurement Unit (PMU), also known as a Hardware Performance Monitor (HPM), integrated into a RISC-V On-Board Computer (OBC) designed for space applications by our research group. The monitoring technique features a novel approach whereby the events triggered are not counted immediately but instead are propagated through the pipeline so that their annotation is synchronized with the executed instruction. Additionally, we also demonstrate the use of this PMU in a process to characterize the execution model of the processor. Finally, as an example of the statistics provided by the PMU, the results obtained running the CoreMark and Dhrystone benchmarks on the RISC-V OBC are shown.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"112 ","pages":"Article 105132"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
<div><div>With the increasing use of satellites, rovers, and other space exploration devices, Artificial Intelligence (AI) is also becoming an important tool for space exploration, allowing autonomous decision-making and operations in harsh environments. As a result, there is an increasing demand for reliable and energy-efficient processing platforms in the space industry. Among all processing architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are becoming popular, particularly in data-intensive applications like machine learning, demonstrating a substantial improvement in the energy efficiency of inference operations while preserving a good degree of versatility. In high-level class space missions, the hardware platforms incorporate radiation-hardened Field Programmable Gate Arrays (FPGAs) and microcontrollers, which do not meet the performance requirements for the aforementioned AI applications. The use of CGRA architectures in space missions is still not widely studied. The main contribution of this work is a comprehensive Design Space Exploration (DSE) activity with our highly parameterized CGRA architecture, exploring the costs associated with various design parameters when targeting AI in the space domain. We evaluated performance, power consumption, and area occupation after synthesis on the radiation-hardened DARE65T standard cell library developed by imec, based on a commercial 65 nm technology process. We characterize different CGRA configurations, comparing them with state-of-the-art solutions used for the acceleration of the AI algorithms. This work highlights Performance, Power, and Area (PPA) results that range from <span><math><mrow><mi>100</mi><mspace></mspace><mi>MHz</mi></mrow></math></span> (up to <span><math><mrow><mi>600</mi><mspace></mspace><mi>MOps</mi></mrow></math></span>), <span><math><mrow><mi>2.43</mi><mo>×</mo><msup><mrow><mi>10</mi></mrow><mrow><mi>4</mi></mrow></msup><mspace></mspace><mstyle><mstyle><mi>μ</mi></mstyle></mstyle><msup><mrow><mi>m</mi></mrow><mrow><mi>2</mi></mrow></msup></mrow></math></span> cell area occupation and <span><math><mrow><mi>0.699</mi><mspace></mspace><mi>mW</mi></mrow></math></span> power consumption, to <span><math><mrow><mi>625</mi><mspace></mspace><mi>MHz</mi></mrow></math></span> (up to <span><math><mrow><mi>3.75</mi><mspace></mspace><mi>GOps</mi></mrow></math></span>), <span><math><mrow><mi>2.43</mi><mo>×</mo><msup><mrow><mi>10</mi></mrow><mrow><mi>5</mi></mrow></msup><mspace></mspace><mstyle><mstyle><mi>μ</mi></mstyle></mstyle><msup><mrow><mi>m</mi></mrow><mrow><mi>2</mi></mrow></msup><mo>,</mo><mi>46.5</mi><mspace></mspace><mi>mW</mi></mrow></math></span>. During DSE activity, we highlight the optimal solutions in terms of area efficiency (up to <span><math><mrow><mi>313.1</mi><mspace></mspace><msup><mrow><mi>GOps/mm</mi></mrow><mrow><mi>2</mi></mrow></msup></mrow></math></span>) and energy efficiency (up to <span><math><mrow><mi>289</mi><mspace></mspace><mi>GOps/W</mi></
{"title":"Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform","authors":"Luca Zulberti , Matteo Monopoli , Pietro Nannipieri , Silvia Moranti , Geert Thys , Luca Fanucci","doi":"10.1016/j.micpro.2025.105142","DOIUrl":"10.1016/j.micpro.2025.105142","url":null,"abstract":"<div><div>With the increasing use of satellites, rovers, and other space exploration devices, Artificial Intelligence (AI) is also becoming an important tool for space exploration, allowing autonomous decision-making and operations in harsh environments. As a result, there is an increasing demand for reliable and energy-efficient processing platforms in the space industry. Among all processing architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) are becoming popular, particularly in data-intensive applications like machine learning, demonstrating a substantial improvement in the energy efficiency of inference operations while preserving a good degree of versatility. In high-level class space missions, the hardware platforms incorporate radiation-hardened Field Programmable Gate Arrays (FPGAs) and microcontrollers, which do not meet the performance requirements for the aforementioned AI applications. The use of CGRA architectures in space missions is still not widely studied. The main contribution of this work is a comprehensive Design Space Exploration (DSE) activity with our highly parameterized CGRA architecture, exploring the costs associated with various design parameters when targeting AI in the space domain. We evaluated performance, power consumption, and area occupation after synthesis on the radiation-hardened DARE65T standard cell library developed by imec, based on a commercial 65 nm technology process. We characterize different CGRA configurations, comparing them with state-of-the-art solutions used for the acceleration of the AI algorithms. This work highlights Performance, Power, and Area (PPA) results that range from <span><math><mrow><mi>100</mi><mspace></mspace><mi>MHz</mi></mrow></math></span> (up to <span><math><mrow><mi>600</mi><mspace></mspace><mi>MOps</mi></mrow></math></span>), <span><math><mrow><mi>2.43</mi><mo>×</mo><msup><mrow><mi>10</mi></mrow><mrow><mi>4</mi></mrow></msup><mspace></mspace><mstyle><mstyle><mi>μ</mi></mstyle></mstyle><msup><mrow><mi>m</mi></mrow><mrow><mi>2</mi></mrow></msup></mrow></math></span> cell area occupation and <span><math><mrow><mi>0.699</mi><mspace></mspace><mi>mW</mi></mrow></math></span> power consumption, to <span><math><mrow><mi>625</mi><mspace></mspace><mi>MHz</mi></mrow></math></span> (up to <span><math><mrow><mi>3.75</mi><mspace></mspace><mi>GOps</mi></mrow></math></span>), <span><math><mrow><mi>2.43</mi><mo>×</mo><msup><mrow><mi>10</mi></mrow><mrow><mi>5</mi></mrow></msup><mspace></mspace><mstyle><mstyle><mi>μ</mi></mstyle></mstyle><msup><mrow><mi>m</mi></mrow><mrow><mi>2</mi></mrow></msup><mo>,</mo><mi>46.5</mi><mspace></mspace><mi>mW</mi></mrow></math></span>. During DSE activity, we highlight the optimal solutions in terms of area efficiency (up to <span><math><mrow><mi>313.1</mi><mspace></mspace><msup><mrow><mi>GOps/mm</mi></mrow><mrow><mi>2</mi></mrow></msup></mrow></math></span>) and energy efficiency (up to <span><math><mrow><mi>289</mi><mspace></mspace><mi>GOps/W</mi></","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105142"},"PeriodicalIF":1.9,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143180785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1016/j.micpro.2025.105141
Ibrahim Lantri , Mansour Abed , Adel Belouchrani
This paper explores the hardware implementation of an embedded time-frequency signal analyzer using the Polynomial Cheriet-Belouchrani Distribution (PCBD) with a compact kernel. We implemented this distribution on a Texas Instruments TMS320C6713 Digital Signal Processing Starter Kit (DSK). Compared to other quadratic time-frequency distributions (TFDs), the PCBD requires a low computational cost due to its compact support nature, which reduces the number of points needing calculation. The sole smoothing parameter γ that controls its kernel's bandwidth is an integer, simplifying the unsupervised approach. To ensure that the realized TF analyzer is automatically tuned, an accurate low-complexity performance measure must be employed to achieve optimal concentration, resolution, and cross-term suppression. Failure to do so may result in missing or degraded essential signal characteristics. The Stankovic measure has been identified as the preferred measure among many others for finding the optimal value of the integer γ. We have also been exploring methods to optimize the execution of various algorithms by taking advantage of specific mathematical properties inherent in the compact polynomial kernel and the PCBD. Additionally, we propose a recursive method to minimize the computation cost associated with the discrete PCB kernel. These strategies are designed to enhance efficiency and reduce the required machine cycles. To compare the performances provided, we thoroughly evaluate the numerical complexity of our implemented distribution, both with and without mathematical optimization. The findings obtained demonstrate the effectiveness of using the TMS320C6713 DSK board to design a high-resolution auto-tuned time-frequency signal analyzer. We not only achieved a perfect match with the results obtained from MATLAB, but the optimized approach also reduced runtime by approximately 19 % to 47 % compared to the direct method, depending on the input signal length and the number of loops required to optimize the Stankovic measure. A comparative analysis was also conducted to assess the effectiveness of our approach in relation to other linear and quadratic TF analyzers, including those implemented on field-programmable gate arrays (FPGAs).
{"title":"Hardware implementation of a high-resolution auto-tuned time-frequency signal analyzer over TMS320C6713 DSK using a compact support polynomial kernel","authors":"Ibrahim Lantri , Mansour Abed , Adel Belouchrani","doi":"10.1016/j.micpro.2025.105141","DOIUrl":"10.1016/j.micpro.2025.105141","url":null,"abstract":"<div><div>This paper explores the hardware implementation of an embedded time-frequency signal analyzer using the Polynomial Cheriet-Belouchrani Distribution (PCBD) with a compact kernel. We implemented this distribution on a Texas Instruments TMS320C6713 Digital Signal Processing Starter Kit (DSK). Compared to other quadratic time-frequency distributions (TFDs), the PCBD requires a low computational cost due to its compact support nature, which reduces the number of points needing calculation. The sole smoothing parameter <em>γ</em> that controls its kernel's bandwidth is an integer, simplifying the unsupervised approach. To ensure that the realized TF analyzer is automatically tuned, an accurate low-complexity performance measure must be employed to achieve optimal concentration, resolution, and cross-term suppression. Failure to do so may result in missing or degraded essential signal characteristics. The Stankovic measure has been identified as the preferred measure among many others for finding the optimal value of the integer <em>γ</em>. We have also been exploring methods to optimize the execution of various algorithms by taking advantage of specific mathematical properties inherent in the compact polynomial kernel and the PCBD. Additionally, we propose a recursive method to minimize the computation cost associated with the discrete PCB kernel. These strategies are designed to enhance efficiency and reduce the required machine cycles. To compare the performances provided, we thoroughly evaluate the numerical complexity of our implemented distribution, both with and without mathematical optimization. The findings obtained demonstrate the effectiveness of using the TMS320C6713 DSK board to design a high-resolution auto-tuned time-frequency signal analyzer. We not only achieved a perfect match with the results obtained from MATLAB, but the optimized approach also reduced runtime by approximately 19 % to 47 % compared to the direct method, depending on the input signal length and the number of loops required to optimize the Stankovic measure. A comparative analysis was also conducted to assess the effectiveness of our approach in relation to other linear and quadratic TF analyzers, including those implemented on field-programmable gate arrays (FPGAs).</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"113 ","pages":"Article 105141"},"PeriodicalIF":1.9,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143179736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-01DOI: 10.1016/j.micpro.2024.105120
V. Hurbungs , T.P. Fowdur , V. Bassoo
Edge machine learning brings intelligence to low-power devices at the periphery of a network. By running machine learning algorithms on the Edge, classification can be performed faster without the need to transmit large data volumes across a network. However, on-device training is often not feasible since Edge devices have limited computing and storage resources. Improved, Scalable, Efficient, and Fast classifieR (iSEFR) is a classifier that performs both training and testing on low-power devices using linearly separable balanced datasets. The novelty of this work is the improvement of the iSEFR accuracy by fine-tuning the algorithm with datasets having an uneven class distribution. Three adaptive linear function transformation techniques were proposed to improve the decision threshold which is in the form of a linear function. Experiments using stratified sampling with 5-fold cross-validation demonstrate that one of the proposed techniques significantly improved F1-score, Recall and Matthews Correlation Coefficient (MCC) by an average of 23 %, 35 % and 21 % compared to iSEFR. Further evaluation of this technique in a Fog environment using highly imbalanced datasets such as credit card fraud, network intrusion and diabetic retinopathy also showed a significant increase of 38 %, 44 % and 30 % in F1-score, Recall and MCC with a Precision of 97 %. The adaptive binary classifier maintained the time complexity of iSEFR without altering the class imbalance.
{"title":"An adaptive binary classifier for highly imbalanced datasets on the Edge","authors":"V. Hurbungs , T.P. Fowdur , V. Bassoo","doi":"10.1016/j.micpro.2024.105120","DOIUrl":"10.1016/j.micpro.2024.105120","url":null,"abstract":"<div><div>Edge machine learning brings intelligence to low-power devices at the periphery of a network. By running machine learning algorithms on the Edge, classification can be performed faster without the need to transmit large data volumes across a network. However, on-device training is often not feasible since Edge devices have limited computing and storage resources. Improved, Scalable, Efficient, and Fast classifieR (iSEFR) is a classifier that performs both training and testing on low-power devices using linearly separable balanced datasets. The novelty of this work is the improvement of the iSEFR accuracy by fine-tuning the algorithm with datasets having an uneven class distribution. Three adaptive linear function transformation techniques were proposed to improve the decision threshold which is in the form of a linear function. Experiments using stratified sampling with 5-fold cross-validation demonstrate that one of the proposed techniques significantly improved F1-score, Recall and Matthews Correlation Coefficient (MCC) by an average of 23 %, 35 % and 21 % compared to iSEFR. Further evaluation of this technique in a Fog environment using highly imbalanced datasets such as credit card fraud, network intrusion and diabetic retinopathy also showed a significant increase of 38 %, 44 % and 30 % in F1-score, Recall and MCC with a Precision of 97 %. The adaptive binary classifier maintained the time complexity of iSEFR without altering the class imbalance.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"111 ","pages":"Article 105120"},"PeriodicalIF":1.9,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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