Microprocessors and Microsystems最新文献_第2页

Hardware and software design of APEnetX: A custom high-speed interconnect for scientific computing 科学计算专用高速互连APEnetX的软硬件设计

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2026-02-01 Epub Date: 2025-11-21 DOI: 10.1016/j.micpro.2025.105224

Roberto Ammendola , Andrea Biagioni , Carlotta Chiarini , Paolo Cretaro , Ottorino Frezza , Francesca Lo Cicero , Alessandro Lonardo , Michele Martinelli , Pier Stanislao Paolucci , Elena Pastorelli , Pierpaolo Perticaroli , Luca Pontisso , Cristian Rossi , Francesco Simula , Piero Vicini

High speed interconnects are critical to provide robust and highly efficient services to every user in a cluster. Several commercial offerings – many of which now firmly established in the market – have arisen throughout the years, spanning the very many possible tradeoffs between cost, reconfigurability, performance, resiliency and support for a variety of processing architectures. On the other hand, custom interconnects may represent an appealing solution for applications requiring cost-effectiveness, customizability and flexibility.

In this regard, the APEnet project was started in 2003, focusing on the design of PCIe FPGA-based custom Network Interface Cards (NIC) for cluster interconnects with a 3D torus topology. In this work, we highlight the main features of APEnetX, the latest version of the APEnet NIC. Designed on the Xilinx Alveo U200 card, it implements Remote Direct Memory Access (RDMA) transactions using both Xilinx Ultrascale+ IPs and custom hardware and software components to ensure efficient data transfer without the involvement of the host operating system. The software stack lets the user interface with the NIC directly via a low level driver or through a plug-in for the OpenMPI stack, aligning our NIC to the application layer standards in the HPC community. The APEnetX architecture integrates a Quality-of-Service (QoS) scheme implementation, in order to enforce some level of performance during network congestion events. Finally, APEnetX is accompanied by an Omnet++ based simulator which enables probing the performance of the network when its size is pushed to numbers of nodes otherwise unattainable for cost and/or practicality reasons.

高速互连对于为集群中的每个用户提供健壮和高效的服务至关重要。多年来，已经出现了一些商业产品，其中许多已经在市场上站稳了脚跟，跨越了成本、可重构性、性能、弹性和对各种处理架构的支持之间的许多可能的权衡。另一方面，对于需要成本效益、可定制性和灵活性的应用程序来说，自定义互连可能是一个有吸引力的解决方案。在这方面，APEnet项目于2003年启动，重点是设计基于PCIe fpga的自定义网络接口卡（NIC），用于具有3D环面拓扑的集群互连。在这项工作中，我们重点介绍了APEnetX的主要功能，APEnetX是APEnet网卡的最新版本。在Xilinx Alveo U200卡上设计，它使用Xilinx Ultrascale+ ip和定制硬件和软件组件实现远程直接内存访问（RDMA）事务，以确保高效的数据传输，而无需主机操作系统的参与。软件栈允许用户直接通过底层驱动程序或OpenMPI栈的插件与网卡进行交互，使我们的网卡与高性能计算社区的应用层标准保持一致。APEnetX体系结构集成了服务质量（QoS）方案实现，以便在网络拥塞事件期间强制执行某种级别的性能。最后，APEnetX还附带了一个基于omnet++的模拟器，当网络的大小被推到节点数量时，它可以探测网络的性能，否则由于成本和/或实用性原因无法实现。

{"title":"Hardware and software design of APEnetX: A custom high-speed interconnect for scientific computing","authors":"Roberto Ammendola , Andrea Biagioni , Carlotta Chiarini , Paolo Cretaro , Ottorino Frezza , Francesca Lo Cicero , Alessandro Lonardo , Michele Martinelli , Pier Stanislao Paolucci , Elena Pastorelli , Pierpaolo Perticaroli , Luca Pontisso , Cristian Rossi , Francesco Simula , Piero Vicini","doi":"10.1016/j.micpro.2025.105224","DOIUrl":"10.1016/j.micpro.2025.105224","url":null,"abstract":"<div><div>High speed interconnects are critical to provide robust and highly efficient services to every user in a cluster. Several commercial offerings – many of which now firmly established in the market – have arisen throughout the years, spanning the very many possible tradeoffs between cost, reconfigurability, performance, resiliency and support for a variety of processing architectures. On the other hand, custom interconnects may represent an appealing solution for applications requiring cost-effectiveness, customizability and flexibility.</div><div>In this regard, the APEnet project was started in 2003, focusing on the design of PCIe FPGA-based custom Network Interface Cards (NIC) for cluster interconnects with a 3D torus topology. In this work, we highlight the main features of APEnetX, the latest version of the APEnet NIC. Designed on the Xilinx Alveo U200 card, it implements Remote Direct Memory Access (RDMA) transactions using both Xilinx Ultrascale+ IPs and custom hardware and software components to ensure efficient data transfer without the involvement of the host operating system. The software stack lets the user interface with the NIC directly via a low level driver or through a plug-in for the OpenMPI stack, aligning our NIC to the application layer standards in the HPC community. The APEnetX architecture integrates a Quality-of-Service (QoS) scheme implementation, in order to enforce some level of performance during network congestion events. Finally, APEnetX is accompanied by an Omnet++ based simulator which enables probing the performance of the network when its size is pushed to numbers of nodes otherwise unattainable for cost and/or practicality reasons.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"120 ","pages":"Article 105224"},"PeriodicalIF":2.6,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automatic linux malware detection using binary inspection and runtime opcode tracing 自动linux恶意软件检测使用二进制检查和运行时操作码跟踪

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2026-02-01 Epub Date: 2025-12-12 DOI: 10.1016/j.micpro.2025.105237

Martí Alonso , Andreu Gironés , Juan-José Costa , Enric Morancho , Stefano Di Carlo , Ramon Canal

The fast-paced evolution of cyberattacks to digital infrastructures requires new protection mechanisms to counterattack them. Malware attacks, a type of cyberattacks ranging from viruses and worms to ransomware and spyware, have been traditionally detected using signature-based methods. But with new versions of malware, this approach is not good enough, and new machine learning tools look promising. In this paper we present two methods to detect Linux malware using machine learning models: (1) a dynamic approach, that tracks the application executed instructions (opcodes) while they are being executed; and (2) a static approach, that inspects the binary application files before execution. We evaluate (1) five machine learning models (Support Vector Machine, k-Nearest Neighbor, Naive Bayes, Decision Tree and Random Forest) and (2) a deep neural network using a Long Short-Term Memory architecture with word embedding. We show the methodology, the initial dataset preparation, the infrastructure used to obtain the traces of executed instructions, and the evaluation of the results for the different models used. The obtained results show that the dynamic approach with a Random Forest classifier gets a 90% accuracy or higher, while the static approach obtains a 98% accuracy.

网络攻击对数字基础设施的快速演变需要新的保护机制来反击。恶意软件攻击是一种网络攻击，从病毒和蠕虫到勒索软件和间谍软件，传统上使用基于签名的方法来检测。但是对于新版本的恶意软件，这种方法还不够好，新的机器学习工具看起来很有希望。在本文中，我们提出了两种使用机器学习模型检测Linux恶意软件的方法：(1)动态方法，在应用程序执行指令（操作码）时跟踪它们；(2)静态方法，在执行前检查二进制应用程序文件。我们评估了(1)五种机器学习模型（支持向量机，k近邻，朴素贝叶斯，决策树和随机森林）和(2)使用长短期记忆架构和词嵌入的深度神经网络。我们展示了方法、初始数据集准备、用于获取执行指令的跟踪的基础设施，以及对所使用的不同模型的结果的评估。得到的结果表明，使用随机森林分类器的动态方法获得90%以上的准确率，而静态方法获得98%的准确率。

{"title":"Automatic linux malware detection using binary inspection and runtime opcode tracing","authors":"Martí Alonso , Andreu Gironés , Juan-José Costa , Enric Morancho , Stefano Di Carlo , Ramon Canal","doi":"10.1016/j.micpro.2025.105237","DOIUrl":"10.1016/j.micpro.2025.105237","url":null,"abstract":"<div><div>The fast-paced evolution of cyberattacks to digital infrastructures requires new protection mechanisms to counterattack them. Malware attacks, a type of cyberattacks ranging from viruses and worms to ransomware and spyware, have been traditionally detected using signature-based methods. But with new versions of malware, this approach is not good enough, and new machine learning tools look promising. In this paper we present two methods to detect Linux malware using machine learning models: (1) a dynamic approach, that tracks the application executed instructions (opcodes) while they are being executed; and (2) a static approach, that inspects the binary application files before execution. We evaluate (1) five machine learning models (Support Vector Machine, k-Nearest Neighbor, Naive Bayes, Decision Tree and Random Forest) and (2) a deep neural network using a Long Short-Term Memory architecture with word embedding. We show the methodology, the initial dataset preparation, the infrastructure used to obtain the traces of executed instructions, and the evaluation of the results for the different models used. The obtained results show that the dynamic approach with a Random Forest classifier gets a 90% accuracy or higher, while the static approach obtains a 98% accuracy.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"120 ","pages":"Article 105237"},"PeriodicalIF":2.6,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145790397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SHAX: Evaluation of SVM hardware accelerator for detecting and preventing ROP on Xtensa Xtensa上用于检测和预防ROP的SVM硬件加速器的评估

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2026-02-01 Epub Date: 2025-12-04 DOI: 10.1016/j.micpro.2025.105236

Adebayo Omotosho , Sirine Ilahi , Ernesto Cristopher Villegas Castillo , Christian Hammer , Hans-Martin Bluethgen

Return-oriented programming (ROP) chains together sequences of instructions residing in executable pages of the memory to compromise a program’s control flow. On embedded systems, ROP detection is intricate as such devices lack the resources to directly run sophisticated software-based detection techniques, as these are memory and CPU-intensive.

However, a Field Programmable Gate Array (FPGA) can enhance the capabilities of an embedded device to handle resource-intensive tasks. Hence, this paper presents the first performance evaluation of a Support Vector Machine (SVM) hardware accelerator for automatic ROP classification on Xtensa-embedded devices using hardware performance counters (HPCs).

In addition to meeting security requirements, modern cyber–physical systems must exhibit high reliability against hardware failures to ensure correct functionality. To assess the reliability level of our proposed SVM architecture, we perform simulation-based fault injection at the RT-level. To improve the efficiency of this evaluation, we utilize a hybrid virtual prototype that integrates the RT-level model of the SVM accelerator with the Tensilica LX7 Instruction Set Simulator. This setup enables early-stage reliability assessment, helping to identify vulnerabilities and reduce the need for extensive fault injection campaigns during later stages of the design process.

Our evaluation results show that an SVM accelerator targeting an FPGA device can detect and prevent ROP attacks on an embedded processor with high accuracy in real time. In addition, we explore the most vulnerable locations of our SVM design to permanent faults, enabling the exploration of safety mechanisms that increase fault coverage in future works.

面向返回的编程（ROP）将驻留在内存可执行页中的指令序列链接在一起，以破坏程序的控制流。在嵌入式系统上，ROP检测是复杂的，因为这些设备缺乏直接运行复杂的基于软件的检测技术的资源，因为这些是内存和cpu密集型的。然而，现场可编程门阵列（FPGA）可以增强嵌入式设备处理资源密集型任务的能力。因此，本文提出了支持向量机（SVM）硬件加速器在xtensa嵌入式设备上使用硬件性能计数器（hpc）进行自动ROP分类的首次性能评估。除了满足安全要求外，现代网络物理系统必须在硬件故障时表现出高可靠性，以确保正确的功能。为了评估我们提出的SVM架构的可靠性水平，我们在rt级执行基于仿真的故障注入。为了提高评估效率，我们使用了一个混合虚拟样机，该样机将支持向量机加速器的rt级模型与Tensilica LX7指令集模拟器集成在一起。这种设置支持早期可靠性评估，有助于识别漏洞，并减少在设计过程的后期阶段进行大量故障注入活动的需要。我们的评估结果表明，针对FPGA器件的SVM加速器可以实时高精度地检测和防止嵌入式处理器的ROP攻击。此外，我们还探索了SVM设计中最容易受到永久故障影响的位置，从而可以在未来的工作中探索增加故障覆盖的安全机制。

{"title":"SHAX: Evaluation of SVM hardware accelerator for detecting and preventing ROP on Xtensa","authors":"Adebayo Omotosho , Sirine Ilahi , Ernesto Cristopher Villegas Castillo , Christian Hammer , Hans-Martin Bluethgen","doi":"10.1016/j.micpro.2025.105236","DOIUrl":"10.1016/j.micpro.2025.105236","url":null,"abstract":"<div><div><em>Return-oriented programming</em> (ROP) chains together sequences of instructions residing in executable pages of the memory to compromise a program’s control flow. On <em>embedded systems</em>, ROP detection is intricate as such devices lack the resources to directly run sophisticated software-based detection techniques, as these are memory and CPU-intensive.</div><div>However, a <em>Field Programmable Gate Array</em> (FPGA) can enhance the capabilities of an embedded device to handle resource-intensive tasks. Hence, this paper presents the first performance evaluation of a Support Vector Machine (SVM) hardware accelerator for automatic ROP classification on Xtensa-embedded devices using hardware performance counters (HPCs).</div><div>In addition to meeting security requirements, modern cyber–physical systems must exhibit high reliability against hardware failures to ensure correct functionality. To assess the reliability level of our proposed SVM architecture, we perform simulation-based fault injection at the RT-level. To improve the efficiency of this evaluation, we utilize a hybrid virtual prototype that integrates the RT-level model of the SVM accelerator with the Tensilica LX7 Instruction Set Simulator. This setup enables early-stage reliability assessment, helping to identify vulnerabilities and reduce the need for extensive fault injection campaigns during later stages of the design process.</div><div>Our evaluation results show that an SVM accelerator targeting an FPGA device can detect and prevent ROP attacks on an embedded processor with high accuracy in real time. In addition, we explore the most vulnerable locations of our SVM design to permanent faults, enabling the exploration of safety mechanisms that increase fault coverage in future works.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"120 ","pages":"Article 105236"},"PeriodicalIF":2.6,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145685400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cardiac arrhythmia classification system: An optimized HLS-based hardware implementation on PYNQ platform 心律失常分类系统：PYNQ平台上基于hls的优化硬件实现

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2026-02-01 Epub Date: 2025-11-17 DOI: 10.1016/j.micpro.2025.105225

Soumyashree Mangaraj, Kamalakanta Mahapatra, Samit Ari

Electrocardiogram (ECG) study to diagnose cardiac abnormalities is a popular non-invasive technique. Architecture relying on deep learning (DL), and its hardware deployment on edge is crucial for effective diagnosis in smart health care applications. This inference on resource limited FPGA platform poses a significant challenge with intense mathematical computations of DL architectures. Existing FPGA implemented convolutional neural network (CNN) architectures typically adopt sequential deep convolutional stacking, which demands recurrent use of memory to retrieve data, and ultimately degrading throughput and adding latency. A hardware efficient tri-branch CNN architecture is introduced for arrhythmia classification, which leverages FPGA’s intrinsic parallel architecture and minimizes overhead of data management. The proposed CNN’s hardware architecture is implemented in a high-level synthesis (HLS) framework through three key optimizations: (i) pool-conv-graded-quantized (PCGQ) module, (ii) in-pool merged function module, and (iii) skip-zero connection. These enhancements improve layer level precision, reduce quantization error, lower latency, and optimize FPGA resource utilization. Implemented on a PYNQ-Z2 FPGA, the design utilizes 27.79% LUTs, 12.24% FFs, 50.45% DSPs, 34.29% BRAM, and delivers 347 GOPS throughput at 45 ms latency, validated in Vivado 2022.2. The proposed system is assessed using the MIT-BIH Arrhythmia Dataset in accordance with AAMI EC57 standards, and attained a classification accuracy of 97.98% across five types of ECG beats, highlighting its suitability for portable healthcare applications.

心电图检查诊断心脏异常是一种常用的无创技术。基于深度学习（DL）的架构及其边缘硬件部署对于智能医疗保健应用中的有效诊断至关重要。这种在资源有限的FPGA平台上的推断对深度学习架构的大量数学计算提出了重大挑战。现有FPGA实现的卷积神经网络（CNN）架构通常采用顺序深度卷积堆叠，这需要反复使用内存来检索数据，最终会降低吞吐量并增加延迟。利用FPGA固有的并行结构和最小化数据管理开销，提出了一种硬件高效的三分支CNN结构用于心律失常分类。本文提出的CNN硬件架构在一个高级综合（high-level synthesis， HLS）框架中通过三个关键优化实现：(i)池-卷积-分级-量化（PCGQ）模块，（ii）池内合并功能模块，（iii）跳零连接。这些增强提高了层级精度，减少了量化误差，降低了延迟，并优化了FPGA资源利用率。该设计在PYNQ-Z2 FPGA上实现，利用27.79%的lut， 12.24%的ff， 50.45%的dsp， 34.29%的BRAM，在45 ms延迟下提供347 GOPS吞吐量，在Vivado 2022.2中验证。根据AAMI EC57标准，使用MIT-BIH心律失常数据集对该系统进行了评估，并在五种类型的ECG心跳中获得了97.98%的分类准确率，突出了其适用于便携式医疗保健应用。

{"title":"Cardiac arrhythmia classification system: An optimized HLS-based hardware implementation on PYNQ platform","authors":"Soumyashree Mangaraj, Kamalakanta Mahapatra, Samit Ari","doi":"10.1016/j.micpro.2025.105225","DOIUrl":"10.1016/j.micpro.2025.105225","url":null,"abstract":"<div><div>Electrocardiogram (ECG) study to diagnose cardiac abnormalities is a popular non-invasive technique. Architecture relying on deep learning (DL), and its hardware deployment on edge is crucial for effective diagnosis in smart health care applications. This inference on resource limited FPGA platform poses a significant challenge with intense mathematical computations of DL architectures. Existing FPGA implemented convolutional neural network (CNN) architectures typically adopt sequential deep convolutional stacking, which demands recurrent use of memory to retrieve data, and ultimately degrading throughput and adding latency. A hardware efficient tri-branch CNN architecture is introduced for arrhythmia classification, which leverages FPGA’s intrinsic parallel architecture and minimizes overhead of data management. The proposed CNN’s hardware architecture is implemented in a high-level synthesis (HLS) framework through three key optimizations: (i) pool-conv-graded-quantized (PCGQ) module, (ii) in-pool merged function module, and (iii) skip-zero connection. These enhancements improve layer level precision, reduce quantization error, lower latency, and optimize FPGA resource utilization. Implemented on a PYNQ-Z2 FPGA, the design utilizes 27.79% LUTs, 12.24% FFs, 50.45% DSPs, 34.29% BRAM, and delivers 347 GOPS throughput at 45 ms latency, validated in Vivado 2022.2. The proposed system is assessed using the MIT-BIH Arrhythmia Dataset in accordance with AAMI EC57 standards, and attained a classification accuracy of 97.98% across five types of ECG beats, highlighting its suitability for portable healthcare applications.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"120 ","pages":"Article 105225"},"PeriodicalIF":2.6,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145555216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ALFA: Design of an accuracy-configurable and low-latency fault-tolerant adder ALFA：一种精度可配置、低延迟容错加法器的设计

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2026-02-01 Epub Date: 2025-11-19 DOI: 10.1016/j.micpro.2025.105226

Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis

Low-Latency Approximate Adders (LLAAs) are high-performance adder models that perform either approximate addition with configurable accuracy-loss or accurate addition by integrating proper circuitry to detect and correct the expected approximation error. Due to their block-based structure, these adder models offer lower latency at the expense of configurable accuracy loss and area overhead. However, hardware accelerators employing such adders are susceptible to hardware (HW) faults, which can cause extra errors (i.e., HW errors) in addition to the expected approximation errors during their operation. In this work, we propose a novel Accuracy Configurable Low-latency and Fault-tolerant Adder, namely ALFA, that offers 100% fault coverage taking into consideration the required accuracy level. Our approach takes advantage of the resemblance between the HW errors and the approximation errors to build a scheme based on selective Triple Modular Redundancy (TMR), which can detect and correct all errors that violate the accuracy threshold. The proposed ALFA model for approximate operation achieves significant performance gains with minimum area overhead compared to the state-of-the-art Reduced Precision Redundancy (RPR) Ripple Carry Adders (RCA) with the same level of fault-tolerance. Furthermore, the accurate ALFA model outperforms the RCA with classical TMR in terms of performance.

低延迟近似加法器（LLAAs）是高性能加法器模型，通过集成适当的电路来检测和纠正预期的近似误差，执行具有可配置精度损失的近似加法或精确加法。由于其基于块的结构，这些加法器模型以牺牲可配置精度损失和面积开销为代价提供了较低的延迟。然而，使用这种加法器的硬件加速器容易受到硬件（HW）故障的影响，这除了在其操作期间预期的近似误差外，还可能导致额外的错误（即HW错误）。在这项工作中，我们提出了一种新颖的精度可配置低延迟和容错加法器，即ALFA，它在考虑所需精度水平的情况下提供100%的故障覆盖率。我们的方法利用了HW误差和近似误差之间的相似性，建立了一种基于选择性三模冗余（TMR）的方案，该方案可以检测和纠正所有违反精度阈值的误差。与具有相同容错级别的最先进的降低精度冗余（RPR）纹波进位加法器（RCA）相比，所提出的用于近似操作的ALFA模型以最小的面积开销实现了显着的性能提升。此外，精确的ALFA模型在性能方面优于具有经典TMR的RCA模型。

{"title":"ALFA: Design of an accuracy-configurable and low-latency fault-tolerant adder","authors":"Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis","doi":"10.1016/j.micpro.2025.105226","DOIUrl":"10.1016/j.micpro.2025.105226","url":null,"abstract":"<div><div>Low-Latency Approximate Adders (LLAAs) are high-performance adder models that perform either approximate addition with configurable accuracy-loss or accurate addition by integrating proper circuitry to detect and correct the expected approximation error. Due to their block-based structure, these adder models offer lower latency at the expense of configurable accuracy loss and area overhead. However, hardware accelerators employing such adders are susceptible to hardware (HW) faults, which can cause extra errors (i.e., HW errors) in addition to the expected approximation errors during their operation. In this work, we propose a novel Accuracy Configurable Low-latency and Fault-tolerant Adder, namely ALFA, that offers 100% fault coverage taking into consideration the required accuracy level. Our approach takes advantage of the resemblance between the HW errors and the approximation errors to build a scheme based on selective Triple Modular Redundancy (TMR), which can detect and correct all errors that violate the accuracy threshold. The proposed ALFA model for approximate operation achieves significant performance gains with minimum area overhead compared to the state-of-the-art Reduced Precision Redundancy (RPR) Ripple Carry Adders (RCA) with the same level of fault-tolerance. Furthermore, the accurate ALFA model outperforms the RCA with classical TMR in terms of performance.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"120 ","pages":"Article 105226"},"PeriodicalIF":2.6,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A CGRA frontend for bandwidth utilization in HiPReP 用于HiPReP中带宽利用的CGRA前端

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-12-01 Epub Date: 2025-11-08 DOI: 10.1016/j.micpro.2025.105220

Philipp Käsgen , Markus Weinhardt , Christian Hochberger

When dealing with multiple data consumers and producers in a highly parallel accelerator architecture the challenge arises how to coordinate the requests to memory. An example of such an accelerator is a coarse-grained reconfigurable array (CGRA). CGRAs consist of multiple processing elements (PEs) which can consume and produce data. On the one hand, the resulting load and store requests to the memory need to be orchestrated such that the CGRA does not deadlock when connected to a cache hierarchy responding to memory requests out-of-request-order. On the other hand, multiple consumers and producers open up the possibility to make better use of the available memory bandwidth such that the cache is busy constantly. We call the unit to address these challenges and opportunities frontend (FE).

We propose a synthesizable FE for the HiPReP CGRA which enables the integration with a RISC-V based host system. Based on an example application, we showcase a methodology to match the number of consumers and producers (i.e. PEs) with the memory hierarchy such that the CGRA can efficiently harness the available L1 data cache bandwidth, reaching 99.6% of the theoretical peak bandwidth in a synthetic benchmark, and enabling a speedup of up to 21.9x over an out-of-order processor for dense matrix-matrix-multiplications. Moreover, we explore the FE design, the impact of the different numbers of PEs, memory access patterns, synthesis results, and compare the accelerator runtime with the runtime on the host itself as baseline.

在高度并行的加速器体系结构中处理多个数据消费者和生产者时，如何协调对内存的请求是一个挑战。这种加速器的一个例子是粗粒度可重构数组（CGRA）。CGRAs由多个可以消费和产生数据的处理元素（pe）组成。一方面，对内存产生的加载和存储请求需要进行编排，以便在连接到响应非请求顺序内存请求的缓存层次结构时，CGRA不会死锁。另一方面，多个消费者和生产者开启了更好地利用可用内存带宽的可能性，这样缓存就会一直很忙。我们称该部门为应对这些挑战和机遇的前端（FE）。我们提出了一种可合成的HiPReP CGRA FE，使其能够与基于RISC-V的主机系统集成。基于一个示例应用程序，我们展示了一种将消费者和生产者（即pe）的数量与内存层次结构相匹配的方法，这样CGRA可以有效地利用可用的L1数据缓存带宽，在合成基准测试中达到理论峰值带宽的99.6%，并在无序处理器上实现高达21.9倍的加速，用于密集矩阵-矩阵-乘法。此外，我们还探讨了FE设计、不同数量pe的影响、内存访问模式、合成结果，并将加速器运行时与主机本身的运行时作为基线进行了比较。

{"title":"A CGRA frontend for bandwidth utilization in HiPReP","authors":"Philipp Käsgen , Markus Weinhardt , Christian Hochberger","doi":"10.1016/j.micpro.2025.105220","DOIUrl":"10.1016/j.micpro.2025.105220","url":null,"abstract":"<div><div>When dealing with multiple data consumers and producers in a highly parallel accelerator architecture the challenge arises how to coordinate the requests to memory. An example of such an accelerator is a coarse-grained reconfigurable array (CGRA). CGRAs consist of multiple processing elements (PEs) which can consume and produce data. On the one hand, the resulting load and store requests to the memory need to be orchestrated such that the CGRA does not deadlock when connected to a cache hierarchy responding to memory requests out-of-request-order. On the other hand, multiple consumers and producers open up the possibility to make better use of the available memory bandwidth such that the cache is busy constantly. We call the unit to address these challenges and opportunities <em>frontend</em> (FE).</div><div>We propose a synthesizable FE for the HiPReP CGRA which enables the integration with a RISC-V based host system. Based on an example application, we showcase a methodology to match the number of consumers and producers (i.e. PEs) with the memory hierarchy such that the CGRA can efficiently harness the available L1 data cache bandwidth, reaching 99.6% of the theoretical peak bandwidth in a synthetic benchmark, and enabling a speedup of up to 21.9x over an out-of-order processor for dense matrix-matrix-multiplications. Moreover, we explore the FE design, the impact of the different numbers of PEs, memory access patterns, synthesis results, and compare the accelerator runtime with the runtime on the host itself as baseline.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"119 ","pages":"Article 105220"},"PeriodicalIF":2.6,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145520481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Machine learning for predicting digital block layout feasibility in Analog-On-Top designs 基于机器学习的模拟顶层设计中数字块布局可行性预测

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-12-01 Epub Date: 2025-11-04 DOI: 10.1016/j.micpro.2025.105221

Francesco Daghero , Gabriele Faraone , Eugenio Serianni , Nicola Di Carolo , Giovanna Antonella Franchino , Michelangelo Grosso , Daniele Jahier Pagliari

The Analog-On-Top (AoT) Mixed-Signal (AMS) design flow is a time-consuming process, heavily reliant on expert knowledge and manual iteration. A critical step involves reserving top-level layout regions for digital blocks, which typically requires several back-and-forth exchanges between analog and digital teams due to the complex interplay of design constraints that affect the digital area requirements. Existing automated approaches often fail to generalize, as they are benchmarked on overly simplistic designs that lack real-world complexity. In this work, we frame the area adequacy check as a binary classification task and propose a Machine Learning (ML) solution to predict whether the reserved area for a digital block is sufficient. We conduct an extensive evaluation across multiple ML models on a dataset of production-level designs, achieving up to 94.38% F1 score with a Random Forest. Finally, we apply ensemble techniques to improve performance further, reaching 95.35% F1 with a majority-vote ensemble.

模拟上顶（AoT）混合信号（AMS）设计流程是一个耗时的过程，严重依赖于专家知识和人工迭代。一个关键步骤是为数字块保留顶层布局区域，由于影响数字区域要求的设计约束的复杂相互作用，这通常需要模拟和数字团队之间进行多次来回交换。现有的自动化方法往往不能泛化，因为它们是在缺乏现实世界复杂性的过于简单的设计上进行基准测试的。在这项工作中，我们将区域充分性检查框架为二元分类任务，并提出了一种机器学习（ML）解决方案来预测数字块的保留区域是否足够。我们在生产级设计的数据集上对多个ML模型进行了广泛的评估，随机森林的F1得分高达94.38%。最后，我们应用集成技术进一步提高性能，多数投票集成达到95.35%的F1。

{"title":"Machine learning for predicting digital block layout feasibility in Analog-On-Top designs","authors":"Francesco Daghero , Gabriele Faraone , Eugenio Serianni , Nicola Di Carolo , Giovanna Antonella Franchino , Michelangelo Grosso , Daniele Jahier Pagliari","doi":"10.1016/j.micpro.2025.105221","DOIUrl":"10.1016/j.micpro.2025.105221","url":null,"abstract":"<div><div>The Analog-On-Top (AoT) Mixed-Signal (AMS) design flow is a time-consuming process, heavily reliant on expert knowledge and manual iteration. A critical step involves reserving top-level layout regions for digital blocks, which typically requires several back-and-forth exchanges between analog and digital teams due to the complex interplay of design constraints that affect the digital area requirements. Existing automated approaches often fail to generalize, as they are benchmarked on overly simplistic designs that lack real-world complexity. In this work, we frame the area adequacy check as a binary classification task and propose a Machine Learning (ML) solution to predict whether the reserved area for a digital block is sufficient. We conduct an extensive evaluation across multiple ML models on a dataset of production-level designs, achieving up to 94.38% F1 score with a Random Forest. Finally, we apply ensemble techniques to improve performance further, reaching 95.35% F1 with a majority-vote ensemble.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"119 ","pages":"Article 105221"},"PeriodicalIF":2.6,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Key components for unified 3D wireless communication networks 统一三维无线通信网络的关键部件

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-12-01 Epub Date: 2025-09-15 DOI: 10.1016/j.micpro.2025.105204

Marko Andjelkovic , Nebojsa Maletic , Nicola Miglioranza , Milos Krstic , Enrico Koeck , Jan Buchholz , Maike Taddiken , Markus Fehrenz , Shaden Baradie , Dirk Wübben , Markus Breitbach

The integration of conventional terrestrial wireless communication networks and non-terrestrial networks (NTNs) is the main prerequisite for achieving global connectivity in the next generation (6G) wireless communications. Such integrated communication networks are usually referred to as the unified 3D networks. These networks need to meet the requirements for 6G communications in terms of higher data rates, as well as enhanced reliability, security and network reconfigurability. To achieve these goals, new technologies and components have to be developed. This work introduces the German project 6G-TakeOff, aimed at the development of innovative solutions for unified 3D networks. The project consortium brings together leading academic and industrial partners, covering the entire value chain from design of electronics to applications. In this work, the focus is on the development of key hardware components to support the wireless communication in 3D unified networks. The design concept for each component and the planned demonstrators are presented.

传统地面无线通信网络与非地面无线通信网络（ntn）的融合是实现下一代（6G）无线通信全球互联互通的主要前提。这种集成通信网络通常被称为统一三维网络。这些网络需要在更高的数据速率方面满足6G通信的要求，以及增强的可靠性、安全性和网络可重构性。为了实现这些目标，必须开发新的技术和组件。这项工作介绍了德国6g -起飞项目，旨在为统一3D网络开发创新解决方案。该项目联盟汇集了领先的学术和工业合作伙伴，涵盖了从电子设计到应用的整个价值链。在本工作中，重点研究了支持三维统一网络无线通信的关键硬件组件的开发。介绍了每个组件的设计概念和计划的演示。

{"title":"Key components for unified 3D wireless communication networks","authors":"Marko Andjelkovic , Nebojsa Maletic , Nicola Miglioranza , Milos Krstic , Enrico Koeck , Jan Buchholz , Maike Taddiken , Markus Fehrenz , Shaden Baradie , Dirk Wübben , Markus Breitbach","doi":"10.1016/j.micpro.2025.105204","DOIUrl":"10.1016/j.micpro.2025.105204","url":null,"abstract":"<div><div>The integration of conventional terrestrial wireless communication networks and non-terrestrial networks (NTNs) is the main prerequisite for achieving global connectivity in the next generation (6G) wireless communications. Such integrated communication networks are usually referred to as the unified 3D networks. These networks need to meet the requirements for 6G communications in terms of higher data rates, as well as enhanced reliability, security and network reconfigurability. To achieve these goals, new technologies and components have to be developed. This work introduces the German project 6G-TakeOff, aimed at the development of innovative solutions for unified 3D networks. The project consortium brings together leading academic and industrial partners, covering the entire value chain from design of electronics to applications. In this work, the focus is on the development of key hardware components to support the wireless communication in 3D unified networks. The design concept for each component and the planned demonstrators are presented.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"119 ","pages":"Article 105204"},"PeriodicalIF":2.6,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ecoNIC: SmartNIC-assisted power management for networking workloads in Linux servers ecoNIC：用于Linux服务器中网络工作负载的smartnic辅助电源管理

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-12-01 Epub Date: 2025-10-14 DOI: 10.1016/j.micpro.2025.105209

Marco Liess, Franz Biersack, Lars Nolte, Thomas Wild, Andreas Herkersdorf

Improving the sustainability and energy efficiency of compute resources in next-generation networks is crucial to cope with the ever-growing computing demand while maintaining manageable energy consumption in the processing nodes of the network infrastructure. Simultaneously, critical connected applications, such as autonomous driving, require a high level of service quality in terms of available throughput and achievable latencies. This demands considerable responsiveness from the compute resources and renders power management a challenging task. Existing solutions are not sufficiently adapted to the requirements and characteristics of such applications, making them either responsive but not very efficient, or efficient but unsuitable to provide the required service quality for critical tasks.

We propose ecoNIC, a concept for energy-efficient network processing that combines an RSS-based hardware load balancer for SmartNICs with an adaptive Dynamic Voltage and Frequency Scaling (DVFS) governor. ecoNIC efficiently pins flow priorities to CPU core clusters, reducing the workload of selected cores in the process, and dynamically adjusts their clock speed to exploit freed-up capacities and save energy. We implement ecoNIC as an FPGA-prototype and integrate the DVFS governor into the Linux kernel. The experimental evaluation shows that significant energy savings can be achieved, while the employed priority-pinning ensures low tail latencies for critical traffic. Without sacrificing an increase in high-priority tail latencies, energy savings of 62% are possible. Further relaxation of the latency constraints allows for energy savings of up to 88%.

提高下一代网络中计算资源的可持续性和能源效率对于应对日益增长的计算需求，同时保持网络基础设施处理节点的可管理能耗至关重要。同时，关键的连接应用，如自动驾驶，在可用吞吐量和可实现延迟方面需要高水平的服务质量。这需要计算资源的相当大的响应能力，并使电源管理成为一项具有挑战性的任务。现有的解决方案不能充分适应此类应用程序的需求和特征，使得它们要么响应迅速，但效率不高，要么效率高，但不适合为关键任务提供所需的服务质量。我们提出了ecoNIC，这是一个节能网络处理的概念，它将基于rss的智能网卡硬件负载平衡器与自适应动态电压和频率缩放（DVFS）调节器相结合。ecoNIC有效地将流优先级固定在CPU核心集群上，减少进程中选定核心的工作量，并动态调整其时钟速度以利用空闲容量并节省能源。我们将ecoNIC作为fpga原型实现，并将DVFS调控器集成到Linux内核中。实验结果表明，采用优先级固定的方法可以实现显著的节能，同时保证了关键业务的低尾延迟。在不牺牲高优先级尾部延迟增加的情况下，可以节省62%的能源。进一步放宽延迟限制可以节省高达88%的能源。

{"title":"ecoNIC: SmartNIC-assisted power management for networking workloads in Linux servers","authors":"Marco Liess, Franz Biersack, Lars Nolte, Thomas Wild, Andreas Herkersdorf","doi":"10.1016/j.micpro.2025.105209","DOIUrl":"10.1016/j.micpro.2025.105209","url":null,"abstract":"<div><div>Improving the sustainability and energy efficiency of compute resources in next-generation networks is crucial to cope with the ever-growing computing demand while maintaining manageable energy consumption in the processing nodes of the network infrastructure. Simultaneously, critical connected applications, such as autonomous driving, require a high level of service quality in terms of available throughput and achievable latencies. This demands considerable responsiveness from the compute resources and renders power management a challenging task. Existing solutions are not sufficiently adapted to the requirements and characteristics of such applications, making them either responsive but not very efficient, or efficient but unsuitable to provide the required service quality for critical tasks.</div><div>We propose ecoNIC, a concept for energy-efficient network processing that combines an RSS-based hardware load balancer for SmartNICs with an adaptive Dynamic Voltage and Frequency Scaling (DVFS) governor. ecoNIC efficiently pins flow priorities to CPU core clusters, reducing the workload of selected cores in the process, and dynamically adjusts their clock speed to exploit freed-up capacities and save energy. We implement ecoNIC as an FPGA-prototype and integrate the DVFS governor into the Linux kernel. The experimental evaluation shows that significant energy savings can be achieved, while the employed priority-pinning ensures low tail latencies for critical traffic. Without sacrificing an increase in high-priority tail latencies, energy savings of 62% are possible. Further relaxation of the latency constraints allows for energy savings of up to 88%.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"119 ","pages":"Article 105209"},"PeriodicalIF":2.6,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145365058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FORTALESA: Fault-tolerant reconfigurable systolic array for DNN inference FORTALESA: DNN推理的容错可重构收缩阵列

IF 2.6 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems

Pub Date : 2025-12-01 Epub Date: 2025-10-29 DOI: 10.1016/j.micpro.2025.105222

Natalia Cherezova , Artur Jutman , Maksim Jenihhin

The emergence of Deep Neural Networks (DNNs) in mission- and safety-critical applications brings their reliability to the front. High performance demands of DNNs require the use of specialized hardware accelerators. Systolic array architecture is widely used in DNN accelerators due to its parallelism and regular structure. This work presents a run-time reconfigurable systolic array architecture with three execution modes and four implementation options. All four implementations are evaluated in terms of resource utilization, throughput, and fault tolerance improvement. The proposed architecture is used for reliability enhancement of DNN inference on systolic array through heterogeneous mapping of different network layers to different execution modes. The approach is supported by a novel reliability assessment method based on fault propagation analysis. It is used for the exploration of the appropriate execution mode-layer mapping for DNN inference. The proposed architecture efficiently protects registers and MAC units of systolic array PEs from transient and permanent faults. The reconfigurability feature enables a speedup of up to

3 \times

, depending on layer vulnerability. Furthermore, it requires

6 \times

fewer resources compared to static redundancy and

2.5 \times

fewer resources compared to the previously proposed solution for transient faults.

深度神经网络（dnn）在任务和安全关键应用中的出现使其可靠性成为人们关注的焦点。dnn的高性能要求需要使用专门的硬件加速器。收缩阵列结构由于其并行性和规则性被广泛应用于深度神经网络加速器中。本文提出了一种具有三种执行模式和四种实现选项的运行时可重构收缩阵列架构。根据资源利用率、吞吐量和容错性改进对所有四种实现进行评估。该架构通过不同网络层对不同执行模式的异构映射，增强了收缩阵列上DNN推理的可靠性。该方法得到了一种基于故障传播分析的可靠性评估方法的支持。它用于探索DNN推理的适当执行模式层映射。该结构有效地保护了收缩阵列pe的寄存器和MAC单元免受瞬时和永久故障的影响。可重构特性可根据层的漏洞实现高达3倍的加速。此外，与静态冗余相比，它需要的资源减少了6倍，与之前提出的瞬态故障解决方案相比，它需要的资源减少了2.5倍。

{"title":"FORTALESA: Fault-tolerant reconfigurable systolic array for DNN inference","authors":"Natalia Cherezova , Artur Jutman , Maksim Jenihhin","doi":"10.1016/j.micpro.2025.105222","DOIUrl":"10.1016/j.micpro.2025.105222","url":null,"abstract":"<div><div>The emergence of Deep Neural Networks (DNNs) in mission- and safety-critical applications brings their reliability to the front. High performance demands of DNNs require the use of specialized hardware accelerators. Systolic array architecture is widely used in DNN accelerators due to its parallelism and regular structure. This work presents a run-time reconfigurable systolic array architecture with three execution modes and four implementation options. All four implementations are evaluated in terms of resource utilization, throughput, and fault tolerance improvement. The proposed architecture is used for reliability enhancement of DNN inference on systolic array through heterogeneous mapping of different network layers to different execution modes. The approach is supported by a novel reliability assessment method based on fault propagation analysis. It is used for the exploration of the appropriate execution mode-layer mapping for DNN inference. The proposed architecture efficiently protects registers and MAC units of systolic array PEs from transient and permanent faults. The reconfigurability feature enables a speedup of up to <span><math><mrow><mn>3</mn><mo>×</mo></mrow></math></span>, depending on layer vulnerability. Furthermore, it requires <span><math><mrow><mn>6</mn><mo>×</mo></mrow></math></span> fewer resources compared to static redundancy and <span><math><mrow><mn>2</mn><mo>.</mo><mn>5</mn><mo>×</mo></mrow></math></span> fewer resources compared to the previously proposed solution for transient faults.</div></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"119 ","pages":"Article 105222"},"PeriodicalIF":2.6,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0