The dual-active-bridge converter (DAB) is widely used in solid-state transformers. However, its efficiency improvement is always subject to phase shift modulation (PSM) since obtaining optimal results under PSM is difficult. Hybrid modulation provides a solution to this problem. However, present hybrid modulation has not been fully deduced. This paper proposes an improved hybrid modulation strategy. When compared to the traditional method, the proposed strategy has the characteristics of lower solution complexity and greater performance in terms of efficiency improvement. In this paper, the complete derivation process for the proposed hybrid modulation is given and the boundary conditions for different modes of the hybrid modulation are fully discussed. In addition, based on the published losses model, the numerical results of the current stress and total losses under the proposed hybrid modulation, the traditional single-phase-shift modulation, and a previously published triple-phase-shift modulation are compared. Finally, the correctness of the derivation process and efficiency improvement under the proposed hybrid modulation are verified on an experimental prototype.
{"title":"Improved hybrid modulation strategy with low solution complexity for dual-active-bridge converters","authors":"Jinhao Shen, Jianwei Wu, Jian Zhang, Lin Qiu, Youtong Fang, Xiaoyan Huang","doi":"10.1007/s43236-024-00866-6","DOIUrl":"https://doi.org/10.1007/s43236-024-00866-6","url":null,"abstract":"<p>The dual-active-bridge converter (DAB) is widely used in solid-state transformers. However, its efficiency improvement is always subject to phase shift modulation (PSM) since obtaining optimal results under PSM is difficult. Hybrid modulation provides a solution to this problem. However, present hybrid modulation has not been fully deduced. This paper proposes an improved hybrid modulation strategy. When compared to the traditional method, the proposed strategy has the characteristics of lower solution complexity and greater performance in terms of efficiency improvement. In this paper, the complete derivation process for the proposed hybrid modulation is given and the boundary conditions for different modes of the hybrid modulation are fully discussed. In addition, based on the published losses model, the numerical results of the current stress and total losses under the proposed hybrid modulation, the traditional single-phase-shift modulation, and a previously published triple-phase-shift modulation are compared. Finally, the correctness of the derivation process and efficiency improvement under the proposed hybrid modulation are verified on an experimental prototype.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"12 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141510347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-04DOI: 10.1007/s43236-024-00855-9
Da Li, Pan Sun, Kai Ji, Yan Liang, Yilin Liu, Xusheng Wu
How to improve the efficiency of IPT systems in the case of transceiver coil misalignment is a core problem that needs to be solved urgently. Compared with single-transmitter IPT systems, multi-transmitter ones exhibit greater power supply flexibility, which ensures stable operation despite misalignment. A topology of a multi-transmitter IPT system is proposed in this study. A grouping and switching control strategy of 3 × 3 multi-transmitter coils is designed on the basis of reconfigurable inverter. A method for charging area division is also put forward to improve the efficiency of the IPT system under the condition of power priority. Compared with the traditional multi-transmitter IPT system, the new multi-transmitter topology proposed in this study can realize the independent operation of each transmitter coil with the minimum number of passive devices.
{"title":"Multi-mode switching and charging area division of multi-transmitter IPT system","authors":"Da Li, Pan Sun, Kai Ji, Yan Liang, Yilin Liu, Xusheng Wu","doi":"10.1007/s43236-024-00855-9","DOIUrl":"https://doi.org/10.1007/s43236-024-00855-9","url":null,"abstract":"<p>How to improve the efficiency of IPT systems in the case of transceiver coil misalignment is a core problem that needs to be solved urgently. Compared with single-transmitter IPT systems, multi-transmitter ones exhibit greater power supply flexibility, which ensures stable operation despite misalignment. A topology of a multi-transmitter IPT system is proposed in this study. A grouping and switching control strategy of 3 × 3 multi-transmitter coils is designed on the basis of reconfigurable inverter. A method for charging area division is also put forward to improve the efficiency of the IPT system under the condition of power priority. Compared with the traditional multi-transmitter IPT system, the new multi-transmitter topology proposed in this study can realize the independent operation of each transmitter coil with the minimum number of passive devices.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"101 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141251965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-04DOI: 10.1007/s43236-024-00856-8
Abdur Rehman, Tawfique Uzzaman, Woojin Choi
The growing focus on clean energy is driving the extensive usage of grid-connected inverters (GCIs) and nonlinear loads. The adoption of these nonlinear components causes disturbances, such as harmonic injection, frequency variation, and DC offset, which reduce the power quality of the grid. This reduced power quality induces unstable operation and deterioration of sensitive equipment. The organizations of electrical engineers have defined some standards such as IEEE 519 and P1547 to maintain the power quality of GCIs by setting the limits for harmonics, phases, and frequency variations. Harmonic elimination with grid synchronization methods is used for GCIs to meet the standards. However, the performance of these methods degrades for distorted grid conditions such as DC offset and harmonics. To rectify the mentioned issues, this study proposes a harmonic compensation method using a frequency-adaptive digital lock-in amplifier-based phase-locked loop (DLIA–PLL). The aim is to provide accurate harmonic detection and elimination by performing frequency and phase tracking for grid synchronization. Simulation and experimental results for a 5 kW inverter in an environment with high-total harmonic distortion (THD) conditions are presented to validate the performance of the proposed harmonic compensation with DLIA–PLL. Yokogawa WT1600, a power analyzer, is used to provide reference THD.
{"title":"Frequency-adaptive DLIA–PLL-based current harmonic compensation for single-phase grid-interfaced inverters","authors":"Abdur Rehman, Tawfique Uzzaman, Woojin Choi","doi":"10.1007/s43236-024-00856-8","DOIUrl":"https://doi.org/10.1007/s43236-024-00856-8","url":null,"abstract":"<p>The growing focus on clean energy is driving the extensive usage of grid-connected inverters (GCIs) and nonlinear loads. The adoption of these nonlinear components causes disturbances, such as harmonic injection, frequency variation, and DC offset, which reduce the power quality of the grid. This reduced power quality induces unstable operation and deterioration of sensitive equipment. The organizations of electrical engineers have defined some standards such as IEEE 519 and P1547 to maintain the power quality of GCIs by setting the limits for harmonics, phases, and frequency variations. Harmonic elimination with grid synchronization methods is used for GCIs to meet the standards. However, the performance of these methods degrades for distorted grid conditions such as DC offset and harmonics. To rectify the mentioned issues, this study proposes a harmonic compensation method using a frequency-adaptive digital lock-in amplifier-based phase-locked loop (DLIA–PLL). The aim is to provide accurate harmonic detection and elimination by performing frequency and phase tracking for grid synchronization. Simulation and experimental results for a 5 kW inverter in an environment with high-total harmonic distortion (THD) conditions are presented to validate the performance of the proposed harmonic compensation with DLIA–PLL. Yokogawa WT1600, a power analyzer, is used to provide reference THD.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"33 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141251961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-03DOI: 10.1007/s43236-024-00858-6
Xinghe Ma, Yue Pan
The modular multilevel matrix converter can provide frequency control support for remote AC power grids and has good application prospects in high-voltage low-frequency AC transmission systems. However, the dynamic performance of the traditional outer-loop PI controller is susceptible to changes in its own parameters and external conditions, which in turn influences the control effect. Therefore, a variable universe fuzzy proportional-integral (PI) adaptive outer-loop control strategy is proposed in this paper. Using the automatic sensing and self-adaptive capability of variable universe fuzzy control, the self-adaptation and self-adjustment of the size of the input error of the outer loop is achieved. Meanwhile, a function-based scaling factor approach is utilized to develop scaling factors for the input and output domains to enhance the control accuracy. Simulation and experimental findings demonstrate that this control strategy advances system stability and reinforces the self-adaptive adjustment capability of outer-loop control when compared to preexisting approaches.
模块化多电平矩阵变流器可为远程交流电网提供频率控制支持,在高压低频交流输电系统中具有良好的应用前景。然而,传统外环 PI 控制器的动态性能易受自身参数和外部条件变化的影响,进而影响控制效果。因此,本文提出了一种变宇宙模糊比例积分(PI)自适应外环控制策略。利用可变宇宙模糊控制的自动感应和自适应能力,实现了外环输入误差大小的自适应和自调整。同时,利用基于函数的缩放因子方法为输入域和输出域制定缩放因子,以提高控制精度。仿真和实验结果表明,与现有方法相比,该控制策略提高了系统稳定性,并增强了外环控制的自适应调节能力。
{"title":"M3C outer loop control strategy based on variable universe fuzzy PI control","authors":"Xinghe Ma, Yue Pan","doi":"10.1007/s43236-024-00858-6","DOIUrl":"https://doi.org/10.1007/s43236-024-00858-6","url":null,"abstract":"<p>The modular multilevel matrix converter can provide frequency control support for remote AC power grids and has good application prospects in high-voltage low-frequency AC transmission systems. However, the dynamic performance of the traditional outer-loop PI controller is susceptible to changes in its own parameters and external conditions, which in turn influences the control effect. Therefore, a variable universe fuzzy proportional-integral (PI) adaptive outer-loop control strategy is proposed in this paper. Using the automatic sensing and self-adaptive capability of variable universe fuzzy control, the self-adaptation and self-adjustment of the size of the input error of the outer loop is achieved. Meanwhile, a function-based scaling factor approach is utilized to develop scaling factors for the input and output domains to enhance the control accuracy. Simulation and experimental findings demonstrate that this control strategy advances system stability and reinforces the self-adaptive adjustment capability of outer-loop control when compared to preexisting approaches.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"21 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141252153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-31DOI: 10.1007/s43236-024-00840-2
Penghe Zhang, Yang Xue, Runan Song, Xiaochen Ma, Dejie Sheng
Distributed photovoltaic systems have encountered unprecedented opportunities for development given their environmentally friendly nature and flexible power generation characteristics. However, numerous connecting lines and taps within the distributed photovoltaic system can be subject to insulation issues, which will consequently cause direct current (DC) arc faults and severe electrical fire hazards. Moreover, the power semiconductor devices in the photovoltaic inverter can introduce common-mode noises to the DC current, resulting in unwanted tripping of the DC arc fault detector. The study proposes an arc fault detection method utilizing a deep residual shrinkage network (DRSN) to address this issue, thereby precisely detecting DC arc faults. A test platform for series arc faults in photovoltaic systems is built. The arc current data are collected for characteristic analysis in time and frequency domains to determine which bandwidth is preferred for the algorithm. The model’s depth is increased by introducing residual connections, enhancing its feature extraction, and improving noise reduction capabilities. The residual shrinkage network has been enhanced to prevent a computation increase from increased network depth. Introducing a convolutional auto-encoder for data dimension reduction has decreased neural network parameters, thereby improving training speed. A prototype for detecting photovoltaic DC arc faults was constructed using Raspberry Pi 4B, validating the practical application value of the proposed method. Experimental results demonstrate that the prototype for detecting photovoltaic DC arc faults successfully fulfills the real-time detection standard of the conduction test.
分布式光伏系统因其环保和灵活的发电特性,迎来了前所未有的发展机遇。然而,分布式光伏系统中的众多连接线和分路器可能存在绝缘问题,从而导致直流(DC)电弧故障和严重的电气火灾隐患。此外,光伏逆变器中的功率半导体器件会给直流电流带来共模噪声,导致直流电弧故障检测器意外跳闸。针对这一问题,研究提出了一种利用深度残余收缩网络(DRSN)的故障电弧检测方法,从而精确检测直流故障电弧。建立了光伏系统串联电弧故障测试平台。收集电弧电流数据进行时域和频域特性分析,以确定算法首选的带宽。通过引入残差连接、加强特征提取和提高降噪能力,增加了模型的深度。残差收缩网络已得到增强,以防止网络深度增加导致计算量增加。通过引入卷积自动编码器来降低数据维度,减少了神经网络参数,从而提高了训练速度。利用 Raspberry Pi 4B 构建了一个用于检测光伏直流电弧故障的原型,验证了所提方法的实际应用价值。实验结果表明,光伏直流电弧故障检测原型成功达到了传导测试的实时检测标准。
{"title":"Photovoltaic DC arc fault detection method based on deep residual shrinkage network","authors":"Penghe Zhang, Yang Xue, Runan Song, Xiaochen Ma, Dejie Sheng","doi":"10.1007/s43236-024-00840-2","DOIUrl":"https://doi.org/10.1007/s43236-024-00840-2","url":null,"abstract":"<p>Distributed photovoltaic systems have encountered unprecedented opportunities for development given their environmentally friendly nature and flexible power generation characteristics. However, numerous connecting lines and taps within the distributed photovoltaic system can be subject to insulation issues, which will consequently cause direct current (DC) arc faults and severe electrical fire hazards. Moreover, the power semiconductor devices in the photovoltaic inverter can introduce common-mode noises to the DC current, resulting in unwanted tripping of the DC arc fault detector. The study proposes an arc fault detection method utilizing a deep residual shrinkage network (DRSN) to address this issue, thereby precisely detecting DC arc faults. A test platform for series arc faults in photovoltaic systems is built. The arc current data are collected for characteristic analysis in time and frequency domains to determine which bandwidth is preferred for the algorithm. The model’s depth is increased by introducing residual connections, enhancing its feature extraction, and improving noise reduction capabilities. The residual shrinkage network has been enhanced to prevent a computation increase from increased network depth. Introducing a convolutional auto-encoder for data dimension reduction has decreased neural network parameters, thereby improving training speed. A prototype for detecting photovoltaic DC arc faults was constructed using Raspberry Pi 4B, validating the practical application value of the proposed method. Experimental results demonstrate that the prototype for detecting photovoltaic DC arc faults successfully fulfills the real-time detection standard of the conduction test.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"24 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141197331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-31DOI: 10.1007/s43236-024-00847-9
Zilong Wang, Jiawei Chen, Yue Su, Xu Zhang, Lixia Zhao
It is necessary to achieve current matching for GaN-based CMOS-like inverters. However, due to the low hole mobility of GaN p-FET devices, the weak output capacity of GaN p-FET devices makes it difficult to obtain current matching with n-FET devices in the off-state, which hinders the development of GaN-based CMOS-like inverters. In this study, a GaN-based CMOS-like device with an AlGaN back barrier layer is designed and its off-state leakage current is compared with that without an AlGaN back-barrier layer. The results show that the 2DEG confinement in the GaN-based n-FET device with an AlGaN back barrier layer can be enhanced and the leakage current is reduced from 10–3 A to 10–6 A in the off-state. This is accomplished without influencing the current of the GaN-based p-FET device in the off-state, resulting in a good current consistency between the n-FET device and the p-FET device in the off-state. The static power consumption is 4.5 µW for GaN-based CMOS-like inverters with an AlGaN back barrier structure when it is operated at Vdd = 5 V. The rise time (tr) and fall time (tf) of the GaN-based CMOS-like inverters are 4 μs and 0.12 μs, respectively. The low noise margin (NML) is 1.90 V and the high noise margin (NMH) is 2.55 V. This work lays a foundation for the development of the future of GaN-based integrated ICs.
{"title":"Low static power consumption GaN-based CMOS-like inverter design","authors":"Zilong Wang, Jiawei Chen, Yue Su, Xu Zhang, Lixia Zhao","doi":"10.1007/s43236-024-00847-9","DOIUrl":"https://doi.org/10.1007/s43236-024-00847-9","url":null,"abstract":"<p>It is necessary to achieve current matching for GaN-based CMOS-like inverters. However, due to the low hole mobility of GaN p-FET devices, the weak output capacity of GaN p-FET devices makes it difficult to obtain current matching with n-FET devices in the off-state, which hinders the development of GaN-based CMOS-like inverters. In this study, a GaN-based CMOS-like device with an AlGaN back barrier layer is designed and its off-state leakage current is compared with that without an AlGaN back-barrier layer. The results show that the 2DEG confinement in the GaN-based n-FET device with an AlGaN back barrier layer can be enhanced and the leakage current is reduced from 10<sup>–3</sup> A to 10<sup>–6</sup> A in the off-state. This is accomplished without influencing the current of the GaN-based p-FET device in the off-state, resulting in a good current consistency between the n-FET device and the p-FET device in the off-state. The static power consumption is 4.5 µW for GaN-based CMOS-like inverters with an AlGaN back barrier structure when it is operated at <i>V</i><sub>dd</sub> = 5 V. The rise time (t<sub>r</sub>) and fall time (t<sub>f</sub>) of the GaN-based CMOS-like inverters are 4 μs and 0.12 μs, respectively. The low noise margin (NM<sub>L</sub>) is 1.90 V and the high noise margin (NM<sub>H</sub>) is 2.55 V. This work lays a foundation for the development of the future of GaN-based integrated ICs.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"8 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141197365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-27DOI: 10.1007/s43236-024-00854-w
Hyung-Woo Lee, Kyo-Beum Lee
This paper proposes a diagnostic and fault-tolerant method for an open-fault condition in dual inverters with open-end winding interior permanent magnet synchronous motors (OEW-IPMSMs). Certain switch pairs show similar behavior in the output current in an open-fault condition due to the structural characteristics of the two-level dual inverter. This work presents a method for detecting open-fault conditions and ensuring a fault-tolerant operation. The proposed method is applied in dual inverters with isolated voltage sources for driving OEW-IPMSM. In the event of an open-fault condition, a pair of switches containing the faulty switch is identified based on the stator current. Subsequently, the switch with the open-fault condition is determined, and fault-tolerant control for a faulty switch is immediately performed through a single-mode operation using zero-voltage vectors. The effectiveness of the proposed detection and tolerant control method is confirmed through simulation and experimental results.
{"title":"Open-fault diagnosis and tolerant control of a dual inverter fed open-end winding interior permanent magnet synchronous motor","authors":"Hyung-Woo Lee, Kyo-Beum Lee","doi":"10.1007/s43236-024-00854-w","DOIUrl":"https://doi.org/10.1007/s43236-024-00854-w","url":null,"abstract":"<p>This paper proposes a diagnostic and fault-tolerant method for an open-fault condition in dual inverters with open-end winding interior permanent magnet synchronous motors (OEW-IPMSMs). Certain switch pairs show similar behavior in the output current in an open-fault condition due to the structural characteristics of the two-level dual inverter. This work presents a method for detecting open-fault conditions and ensuring a fault-tolerant operation. The proposed method is applied in dual inverters with isolated voltage sources for driving OEW-IPMSM. In the event of an open-fault condition, a pair of switches containing the faulty switch is identified based on the stator current. Subsequently, the switch with the open-fault condition is determined, and fault-tolerant control for a faulty switch is immediately performed through a single-mode operation using zero-voltage vectors. The effectiveness of the proposed detection and tolerant control method is confirmed through simulation and experimental results.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"64 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141168352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-25DOI: 10.1007/s43236-024-00782-9
Yaoyu Wu, Jing Liu, Suhuan Li, Mingyue Jin
Solar energy is clean and pollution free. However, the evident intermittency and volatility of illumination make power systems uncertain. Therefore, establishing a photovoltaic prediction model to enhance prediction precision is conducive to lessening the uncertainty of photovoltaic (PV) power generation and to ensuring the safe and stable operation of power grid scheduling. The radiation from the sun to the Earth has a certain regularity, which can be estimated under ideal weather conditions. However, the radiation is affected by climate, cloud cover, and other reasons. Therefore, this paper puts forward a PV prediction model combining a physical model and a neural network that can modify solar radiation in complex weather through the neural network to enhance the accuracy of PV power prediction. First, a solar radiation model (SRM) is established by using the solar radiation mechanism to estimate the sum radiation value on the horizontal plane. Then the slope radiation value received by the PV panel is calculated by the slope irradiance conversion method. Second, the main factors that greatly influence PV power are screened out by the Pearson method. The calculated slope radiation and the main influencing factors are taken as inputs. The long short-term memory network (LSTM) is selected to set up the SRM-LSTM PV power prediction method. The significance of the suggested method is verified by the true data from Alice Springs, Australia. The results show that when compared with the backpropagation (BP) prediction method, the MAE and RMSE were reduced by 22.18% and 33.89% under complex weather conditions, respectively. When compared with the LSTM prediction method, the MAE and RMSE were reduced by 15.99% and 21.73%, respectively. These results demonstrate high accuracy.
{"title":"Physical model and long short-term memory-based combined prediction of photovoltaic power generation","authors":"Yaoyu Wu, Jing Liu, Suhuan Li, Mingyue Jin","doi":"10.1007/s43236-024-00782-9","DOIUrl":"https://doi.org/10.1007/s43236-024-00782-9","url":null,"abstract":"<p>Solar energy is clean and pollution free. However, the evident intermittency and volatility of illumination make power systems uncertain. Therefore, establishing a photovoltaic prediction model to enhance prediction precision is conducive to lessening the uncertainty of photovoltaic (PV) power generation and to ensuring the safe and stable operation of power grid scheduling. The radiation from the sun to the Earth has a certain regularity, which can be estimated under ideal weather conditions. However, the radiation is affected by climate, cloud cover, and other reasons. Therefore, this paper puts forward a PV prediction model combining a physical model and a neural network that can modify solar radiation in complex weather through the neural network to enhance the accuracy of PV power prediction. First, a solar radiation model (SRM) is established by using the solar radiation mechanism to estimate the sum radiation value on the horizontal plane. Then the slope radiation value received by the PV panel is calculated by the slope irradiance conversion method. Second, the main factors that greatly influence PV power are screened out by the Pearson method. The calculated slope radiation and the main influencing factors are taken as inputs. The long short-term memory network (LSTM) is selected to set up the SRM-LSTM PV power prediction method. The significance of the suggested method is verified by the true data from Alice Springs, Australia. The results show that when compared with the backpropagation (BP) prediction method, the MAE and RMSE were reduced by 22.18% and 33.89% under complex weather conditions, respectively. When compared with the LSTM prediction method, the MAE and RMSE were reduced by 15.99% and 21.73%, respectively. These results demonstrate high accuracy.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"36 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141153317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-24DOI: 10.1007/s43236-024-00849-7
Amira Tandirovic Gursel, Ali Zülfikaroğlu
In inverter technology for hybrid and electric vehicles, some properties, such as low weight, compactness, small size, high power density, and high efficiency, are highly required because they affect vehicle production costs and fuel economy. Bringing reliable and cheap devices with high response rates into being, which is in close relation with circuit design, miniaturization, and appropriate selection of components, have become one of the main topics of scientific research in electronics. One of the main obstacles to achieving these goals is the bulkiness of inductors and capacitors. These essential building blocks of the converter topology are used to reduce input current and output voltage ripples, which are closely related to thermal stress in batteries, affecting their lifespan. This study proposes a GaN-based multidevice interleaved boost converter (MDIBC) topology for hybrid vehicles. The topology is investigated in terms of power loss, efficiency, current and voltage ripples, and size of passive components under two salient case studies at various switching frequencies. In both cases, current and voltage are reduced by smaller values of passive components without sacrificing efficiency. Efficiencies ranging between 97.34 and 97.83%, are achieved with passive components remaining in the benchmark converter.
{"title":"Modified all-GaN multidevice interleaved boost converter topology for hybrid electrical vehicles and its miniaturization","authors":"Amira Tandirovic Gursel, Ali Zülfikaroğlu","doi":"10.1007/s43236-024-00849-7","DOIUrl":"https://doi.org/10.1007/s43236-024-00849-7","url":null,"abstract":"<p>In inverter technology for hybrid and electric vehicles, some properties, such as low weight, compactness, small size, high power density, and high efficiency, are highly required because they affect vehicle production costs and fuel economy. Bringing reliable and cheap devices with high response rates into being, which is in close relation with circuit design, miniaturization, and appropriate selection of components, have become one of the main topics of scientific research in electronics. One of the main obstacles to achieving these goals is the bulkiness of inductors and capacitors. These essential building blocks of the converter topology are used to reduce input current and output voltage ripples, which are closely related to thermal stress in batteries, affecting their lifespan. This study proposes a GaN-based multidevice interleaved boost converter (MDIBC) topology for hybrid vehicles. The topology is investigated in terms of power loss, efficiency, current and voltage ripples, and size of passive components under two salient case studies at various switching frequencies. In both cases, current and voltage are reduced by smaller values of passive components without sacrificing efficiency. Efficiencies ranging between 97.34 and 97.83%, are achieved with passive components remaining in the benchmark converter.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"57 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141153360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-24DOI: 10.1007/s43236-024-00837-x
Bihua Hu, Han Yan, Zhi Zhang, Jinqing Linghu, Yuqing Liao, Xiafei Long
Conventional multi-level inverters such as neutral point clamped and flying capacitor inverters do not have boosting capability and self-balanced capacitor voltage. Thus, in this paper, we propose a novel three-level inverter based on switched capacitors to solve the above problems. The proposed inverter has lower voltage stress than the general switched-capacitor multi-level inverter. Meanwhile, an improved modulation strategy is adopted in the proposed inverter. The three-level space vector diagram is converted into a two-level one, and the space vector modulation is simplified. Then, we analyze the power loss and design guidelines for the device in the inverter. Finally, a corresponding simulation and an experimental platform will be established to verify the feasibility of the proposed inverter. The results prove that the proposed three-level inverter has good performance and dynamic response that meets the requirements.
{"title":"Three-phase three-level boost inverter with self-balanced capacitor voltage","authors":"Bihua Hu, Han Yan, Zhi Zhang, Jinqing Linghu, Yuqing Liao, Xiafei Long","doi":"10.1007/s43236-024-00837-x","DOIUrl":"https://doi.org/10.1007/s43236-024-00837-x","url":null,"abstract":"<p>Conventional multi-level inverters such as neutral point clamped and flying capacitor inverters do not have boosting capability and self-balanced capacitor voltage. Thus, in this paper, we propose a novel three-level inverter based on switched capacitors to solve the above problems. The proposed inverter has lower voltage stress than the general switched-capacitor multi-level inverter. Meanwhile, an improved modulation strategy is adopted in the proposed inverter. The three-level space vector diagram is converted into a two-level one, and the space vector modulation is simplified. Then, we analyze the power loss and design guidelines for the device in the inverter. Finally, a corresponding simulation and an experimental platform will be established to verify the feasibility of the proposed inverter. The results prove that the proposed three-level inverter has good performance and dynamic response that meets the requirements.</p>","PeriodicalId":50081,"journal":{"name":"Journal of Power Electronics","volume":"132 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141153324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}