IET Computers and Digital Techniques最新文献

Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROM-based S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.

Recently, the finite state machine (FSM)-based digital controllers are susceptible to fault-injection and side-channel attacks, which makes FSM security a more prominent factor. FSM optimality is another crucial element when designed. A state encoding approach is applied for FSM security and optimization. This article proposes the security-dominated FSM state assignment technique (SD-SHO), which obtains a satisfactory level of FSM optimization as well. It is a deterministic algorithm and consists of two key techniques, such as state assignment using an improved quadratic sum code, and state assignment using a gradient-based interior point method. A fuzzy bi-level programming logic is introduced in the proposed approach for regulating the constituting algorithms optimally. Experiments are conducted to evaluate the FSM security and optimality using the MCNC FSM benchmarks. Results indicate a substantial reduction in the error masking probability using SD-SHO. It also demonstrates that SD-SHO achieves a satisfactory level of area and power reduction compared with other existing works.

Fault detection and diagnosis of a Field-Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck-at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair-wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS’89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is $��{�\log �}_2��\left(�\frac{�n��\left(��n�-�1��\right)��}{2}�\right)��+�3�$ where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by $��{�\log �}_2��(�n�+�2�)��$ when compared with previously published methods available in the literature.

In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non-standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co-processor that can be used for video surveillance cameras in homeland security. The proposed ME co-processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co-processor is suited for high-efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block-based motion estimation (FSBB-ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB-ME algorithm. Modelism-version10.4a has been used for simulation and time verification testing proposes. The proposed ME co-processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.

The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short-period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider-based pseudorandom bit generator is compared with other LCG-based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 2²ⁿ pseudorandom bits for n-bit operands size which leads to lowering the hardware cost. Secondly, it generates high-speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex-5, Virtex-7, and Artix-7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look-up-tables and flip-flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test.

Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its functionality is retrieved when the right key is loaded onto it. We propose ‘noise-based’ logic locking, consisting of two separate compliment blocks, which function in three states. By flipping a signal once in the circuit, these modules add corruption to the circuit, whereas either flipping the same signal twice or not flipping leads to the correct functionality. Thus, a low probability skew with a low corruption in the output is obtained by utilisation of these flipping states. We have improved SAT attack resiliency based on time by 17% for a locking block with 14 primary inputs in comparison with the well-known anti-SAT. The area overhead is less in comparison with other schemes, in which extra dummy parts or obfuscation elements are added to their circuit. Also, more crucially, our locking blocks are immune to SPS attack solely. After executing various attacks, retrieved circuits indicate improved overall resiliency against automatic test pattern generation based and approximate guided removal attacks as well.

As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear-out attacks from malicious applications. However, it is also found that the non-volatile nature and the programming behaviour of PCM bring other security challenges to the memory system. The authors examine the potential risk of information leakage and theft in memory management for PCM-based cloud server or multitenant systems. By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in-memory data obfuscation mechanism to defend against memory attacks or information leakage during page reallocation mandated by OS. With the capabilities of in-memory data randomisation, the proposed SecuRAM avoids the long write latency of PCM cells to erase the content, and achieves higher data initialisation efficiency than conventional software solutions. Second, the proposed SecuRAM also provides a novel solution of fast in-memory hardware fingerprinting and random number generation, which are common and essential security functions in encryption or access authentication to protect confidential memory data from attackers. Two novel techniques are proposed to generate signatures and random numbers: the first is based on partial programming, which works in the same way as bulk data randomisation; the second is loop-counting, which is an overhead-free method by reusing the cell programming mechanism in iterate-write PCM devices. Through evaluation, SecuRAM shows a much better performance and energy-efficiency than conventional measures for PCM memory.

In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.

The merit of higher order functions for hardware description and transformation is widely acknowledged by hardware designers. However, the use of higher order types makes their correctness proof very difficult. Herein, a new proof approach based on the principle of partial application is proposed which transforms higher order functions into partially applied first-order ones. Therefore, parameterised architectures modelled by higher order functions could be easily redefined only over first-order types. The proof could be performed by induction within the same specification framework that avoids translating the higher order properties between different semantics, which remains extremely difficult. Using the notion of parameterisation where verified components are used as parameters to build more complex ones, the approach fits elegantly in the incremental bottom-up design where both the design and its proof could be developed in a systematic way. The potential features of the proposed methodological proof approach are demonstrated over a detailed example of a circuit design and verification within a functional framework.

The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2^d. Additionally, a scaling scheme is proposed that scales up the input N < 2^d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one ‘1’ in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8× more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.