IET Computers and Digital Techniques最新文献

Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross-Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.

The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2^d. Additionally, a scaling scheme is proposed that scales up the input N < 2^d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one ‘1’ in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8× more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.

The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip-flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic-0 and logic-1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

Multiprocessor task scheduling problem is a pressing problem that affects systems' performance and is still being investigated by the researchers. Finding the optimal schedules is considered to be a computationally hard problem. Recently, researchers have used fuzzy logic in the field of task scheduling to achieve optimal performance, but this area of research is still not well investigated. In addition, there are various scheduling algorithms that used fuzzy logic but most of them are often performed on uniprocessor systems. This article presents a new proposed algorithm in which the priorities of the tasks are derived from the fuzzy logic and bottom level parameter. This approach is designed to find task schedules with optimal or sub-optimal lengths in order to achieve high performance for a multiprocessor environment. With respect to the proposed algorithm, the precedence constraints between the non-preemptive tasks and their execution times are known and described by a directed acyclic graph. The number of processors is fixed, the communication costs are negligible and the processors are homogeneous. The suggested technique is tested and compared with the Prototype Standard Task Graph Set.

Fast Fourier transform (FFT) is the most common low-complexity implementation of the discrete Fourier transform, intensively employed to process real-world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low-power FFT hardware architecture combining split-radix decimation-in-time butterfly and 5-2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65-nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split-radix butterfly is 13.28% more power efficient than the radix-4 one. The results further show that, by combining 5-2 AC within the split-radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state-of-the-art radix-4 butterfly employing the adder automatically selected by the logic synthesis tool.

This study proposes an FPGA-based hardware in the loop (HIL) emulator for speed-sensorless of induction motor (IM) constant switching frequency controller-based direct torque control (CSFC-DTC) with a novel bi input-reduced order extended Kalman filter (BI-ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed-loop speed-sensorless drive system of IM on the Xilinx Virtex XC5VLX-110T ML506 FPGA board. In this HIL emulator of speed-sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI-ROEKF which is proposed for the first time in the literature. The proposed BI-ROEKF is created by applying two different non-linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed-sensorless drive system of IM is implemented on FPGA using the advantage of hand-written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model-based estimator like the novel BI-ROEKF and hence the control performance of drive system. The estimation performance of the novel BI-ROEKF is tested with speed-sensorless CSFC-DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed-sensorless BI-ROEKF-based CSFC-DTC of the IM are presented.

This article offers a new bit-serial systolic array architecture to implement the interleaved multiplication algorithm in the binary-extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit-serial multiplier structure and the existing competitive bit-serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area-time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.

The rise in complementary metal-oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond-CMOS technologies to stay in race with Moore’s law. Quantum-dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond-CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND-NOR logic. In QCA, the NAND-NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost-efficient NAND-NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND-NOR logic and the proposed blocks, a 16*16 SRAM is implemented. QCADesigner is used for the simulation and validation of the proposed designs.

In [1], the following corrections should be noted.

The work in this article is funded by National Science Technology, Innovative Plan (NSTIP), Saudi Arabia (14-ELE1049-10). The authors acknowledge the support of King Abdul-Aziz City for Science and Technology (KACST) and Science and Technology Unit (STU), Makkah.