Pub Date : 2023-01-01DOI: 10.1587/transele.2023mmp0005
Y. Kumazaki, S. Ozaki, N. Okamoto, N. Hara, Y. Nakasha, Masaru Sato, T. Ohki
{"title":"High-Efficiency 250-320 GHz Power Amplifiers Using InP-Based Metal-Oxide-Semiconductor High-Electron-Mobility Transistors","authors":"Y. Kumazaki, S. Ozaki, N. Okamoto, N. Hara, Y. Nakasha, Masaru Sato, T. Ohki","doi":"10.1587/transele.2023mmp0005","DOIUrl":"https://doi.org/10.1587/transele.2023mmp0005","url":null,"abstract":"","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":"661-668"},"PeriodicalIF":0.5,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67307131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A T-junction orthomode transducer (OMT) is a waveguide component that separates two orthogonal linear polarizations in the same frequency band. It has a common circular waveguide short-circuited at one end and two branch rectangular waveguides arranged in opposite directions near the short circuit. One of the advantages of a T-junction OMT is its short axial length. However, the two rectangular ports, which need to be orthogonal, have different levels of performance because of asymmetry. We therefore propose a uniaxially symmetrical T-junction OMT, which is configured such that the two branch waveguides are tilted 45° to the short circuit. The uniaxially symmetrical configuration enables same levels of performance for the two ports, and its impedance matching is easier compared to that for the conventional configuration. The polarization separation principle can be explained using the principles of orthomode junction (OMJ) and turnstile OMT. Based on calculations, the proposed configuration demonstrated a return loss of 25 dB, XPD of 30 dB, isolation of 21 dB between the two branch ports, and loss of 0.25 dB, with a bandwidth of 15% in the K band. The OMT was then fabricated as a single piece via 3D printing and evaluated against the calculated performance indices.
{"title":"Uniaxially Symmetrical T-Junction OMT with 45°-Tilted Branch Waveguide Ports","authors":"Hidenori YUKAWA, Yu USHIJIMA, Toru TAKAHASHI, Toru FUKASAWA, Yoshio INASAWA, Naofumi YONEDA, Moriyasu MIYAZAKI","doi":"10.1587/transele.2023ecp5013","DOIUrl":"https://doi.org/10.1587/transele.2023ecp5013","url":null,"abstract":"A T-junction orthomode transducer (OMT) is a waveguide component that separates two orthogonal linear polarizations in the same frequency band. It has a common circular waveguide short-circuited at one end and two branch rectangular waveguides arranged in opposite directions near the short circuit. One of the advantages of a T-junction OMT is its short axial length. However, the two rectangular ports, which need to be orthogonal, have different levels of performance because of asymmetry. We therefore propose a uniaxially symmetrical T-junction OMT, which is configured such that the two branch waveguides are tilted 45° to the short circuit. The uniaxially symmetrical configuration enables same levels of performance for the two ports, and its impedance matching is easier compared to that for the conventional configuration. The polarization separation principle can be explained using the principles of orthomode junction (OMJ) and turnstile OMT. Based on calculations, the proposed configuration demonstrated a return loss of 25 dB, XPD of 30 dB, isolation of 21 dB between the two branch ports, and loss of 0.25 dB, with a bandwidth of 15% in the K band. The OMT was then fabricated as a single piece via 3D printing and evaluated against the calculated performance indices.","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136256871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1587/TRANSELE.2020CDP0004
Xi Fu, Yun Wang, Zheng Li, A. Shirane, K. Okada
{"title":"A CMOS SPDT RF Switch with 68 dB Isolation and 1.0 dB Loss Feathering Switched Resonance Network for MIMO Applications","authors":"Xi Fu, Yun Wang, Zheng Li, A. Shirane, K. Okada","doi":"10.1587/TRANSELE.2020CDP0004","DOIUrl":"https://doi.org/10.1587/TRANSELE.2020CDP0004","url":null,"abstract":"","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":""},"PeriodicalIF":0.5,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67305537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1587/TRANSELE.2020CDP0001
T. Shimamura, H. Morimura
{"title":"Novel Threshold Circuit Technique and Its Performance Analysis on Nanowatt Vibration Sensing Circuits for Millimeter-Sized Wireless Sensor Nodes","authors":"T. Shimamura, H. Morimura","doi":"10.1587/TRANSELE.2020CDP0001","DOIUrl":"https://doi.org/10.1587/TRANSELE.2020CDP0001","url":null,"abstract":"","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":""},"PeriodicalIF":0.5,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67305838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1587/TRANSELE.2020CDP0006
Ruilin Zhang, Xingyu Wang, H. Shinohara
In this paper, we describe a post-processing technique having high extraction efficiency (ExE) for de-biasing and de-correlating a random bitstream generated by true random number generators (TRNGs). This research is based on the N-bit von Neumann (VN N) post-processing method. It improves the ExE of the original von Neumann method close to the Shannon entropy bound by a large N value. However, as the N value increases, the mapping table complexity increases exponentially (2N ), which makes VN N unsuitable for low-power TRNGs. To overcome this problem, at the algorithm level, we propose a waiting strategy to achieve high ExE with a small N value. At the architectural level, a Hamming weight mapping-based hierarchical structure is used to reconstruct the large mapping table using smaller tables. The hierarchical structure also decreases the correlation factor in the raw bitstream. To develop a technique with high ExE and low cost, we designed and fabricated an 8-bit von Neumann with waiting strategy (VN 8W) in a 130-nm CMOS. The maximum ExE of VN 8W is 62.21%, which is 2.49 times larger than the ExE of the original von Neumann. NIST SP 800-22 randomness test results proved the debiasing and de-correlation abilities of VN 8W. As compared with the stateof-the-art optimized 7-element iterated von Neumann, VN 8W achieved more than 20% energy reduction with higher ExE. At 0.45 V and 1 MHz, VN 8W achieved the minimum energy of 0.18 pJ/bit, which was suitable for sub-pJ low energy TRNGs. key words: post-processing techniques, von Neumann entropy extractor, true random number generator, low-power
{"title":"Energy-Efficient Post-Processing Technique Having High Extraction Efficiency for True Random Number Generators","authors":"Ruilin Zhang, Xingyu Wang, H. Shinohara","doi":"10.1587/TRANSELE.2020CDP0006","DOIUrl":"https://doi.org/10.1587/TRANSELE.2020CDP0006","url":null,"abstract":"In this paper, we describe a post-processing technique having high extraction efficiency (ExE) for de-biasing and de-correlating a random bitstream generated by true random number generators (TRNGs). This research is based on the N-bit von Neumann (VN N) post-processing method. It improves the ExE of the original von Neumann method close to the Shannon entropy bound by a large N value. However, as the N value increases, the mapping table complexity increases exponentially (2N ), which makes VN N unsuitable for low-power TRNGs. To overcome this problem, at the algorithm level, we propose a waiting strategy to achieve high ExE with a small N value. At the architectural level, a Hamming weight mapping-based hierarchical structure is used to reconstruct the large mapping table using smaller tables. The hierarchical structure also decreases the correlation factor in the raw bitstream. To develop a technique with high ExE and low cost, we designed and fabricated an 8-bit von Neumann with waiting strategy (VN 8W) in a 130-nm CMOS. The maximum ExE of VN 8W is 62.21%, which is 2.49 times larger than the ExE of the original von Neumann. NIST SP 800-22 randomness test results proved the debiasing and de-correlation abilities of VN 8W. As compared with the stateof-the-art optimized 7-element iterated von Neumann, VN 8W achieved more than 20% energy reduction with higher ExE. At 0.45 V and 1 MHz, VN 8W achieved the minimum energy of 0.18 pJ/bit, which was suitable for sub-pJ low energy TRNGs. key words: post-processing techniques, von Neumann entropy extractor, true random number generator, low-power","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":""},"PeriodicalIF":0.5,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67305628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1587/TRANSELE.2020CDP0005
Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane, K. Okada
SUMMARY This paper presents a high jitter performance injection- locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100 (cid:181) W power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to min- imize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO’s flicker noise can be suppressed, and a good PN can be achieved in flicker region (1 / f 3 ) with sub-100 (cid:181) W power consumption. Thus, a high figure-of- merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5 / -115.3dBc / Hz at 100kHz / 1MHz frequency o ff set with a 97 (cid:181) W power consumption, which corresponds to a -193 / -194dBc / Hz VCO FoM at 2.62GHz oscil- lation frequency. The measurement results show that the 1 / f 3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78fs RMS jitter while using a high reference clock. A 960fs RMS jitter can be achieved with a 40MHz common reference and 107 (cid:181) W corresponding power.
{"title":"A Low-Jitter Injection-Locked Clock Multiplier Using 97-μW Transformer-Based VCO with 18-kHz Flicker Noise Corner","authors":"Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane, K. Okada","doi":"10.1587/TRANSELE.2020CDP0005","DOIUrl":"https://doi.org/10.1587/TRANSELE.2020CDP0005","url":null,"abstract":"SUMMARY This paper presents a high jitter performance injection- locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100 (cid:181) W power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to min- imize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO’s flicker noise can be suppressed, and a good PN can be achieved in flicker region (1 / f 3 ) with sub-100 (cid:181) W power consumption. Thus, a high figure-of- merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5 / -115.3dBc / Hz at 100kHz / 1MHz frequency o ff set with a 97 (cid:181) W power consumption, which corresponds to a -193 / -194dBc / Hz VCO FoM at 2.62GHz oscil- lation frequency. The measurement results show that the 1 / f 3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78fs RMS jitter while using a high reference clock. A 960fs RMS jitter can be achieved with a 40MHz common reference and 107 (cid:181) W corresponding power.","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"75 1","pages":""},"PeriodicalIF":0.5,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67305581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1587/TRANSELE.2020CDI0001
Tsutomu Matsumoto, M. Ikeda, M. Nagata, Yasuyoshi Uemura
The Internet of Things (IoT) implicates an infrastructure that creates new value by connecting everything with communication networks, and its construction is rapidly progressing in anticipation of its great potential. Enhancing the security of IoT is an essential requirement for supporting IoT. For ensuring IoT security, it is desirable to create a situation that even a terminal component device with many restrictions in computing power and energy capacity can easily verify other devices and data and communicate securely by the use of public key cryptography. To concretely achieve the big goal of penetrating public key cryptographic technology to most IoT end devices, we elaborated the secure cryptographic unit (SCU) built in a low-end microcontroller chip. The SCU comprises a hardware cryptographic engine and a built-in access controlling functionality consisting of a software gate and hardware gate. This paper describes the outline of our SCU construction technology’s research and development and prospects. key words: IoT, security IP, public-key cryptography, root of trust
{"title":"Secure Cryptographic Unit as Root-of-Trust for IoT Era","authors":"Tsutomu Matsumoto, M. Ikeda, M. Nagata, Yasuyoshi Uemura","doi":"10.1587/TRANSELE.2020CDI0001","DOIUrl":"https://doi.org/10.1587/TRANSELE.2020CDI0001","url":null,"abstract":"The Internet of Things (IoT) implicates an infrastructure that creates new value by connecting everything with communication networks, and its construction is rapidly progressing in anticipation of its great potential. Enhancing the security of IoT is an essential requirement for supporting IoT. For ensuring IoT security, it is desirable to create a situation that even a terminal component device with many restrictions in computing power and energy capacity can easily verify other devices and data and communicate securely by the use of public key cryptography. To concretely achieve the big goal of penetrating public key cryptographic technology to most IoT end devices, we elaborated the secure cryptographic unit (SCU) built in a low-end microcontroller chip. The SCU comprises a hardware cryptographic engine and a built-in access controlling functionality consisting of a software gate and hardware gate. This paper describes the outline of our SCU construction technology’s research and development and prospects. key words: IoT, security IP, public-key cryptography, root of trust","PeriodicalId":50384,"journal":{"name":"IEICE Transactions on Electronics","volume":"1 1","pages":""},"PeriodicalIF":0.5,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67305781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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