Pub Date : 2013-06-05DOI: 10.1109/MDAT.2012.2237138
R. Topaloglu, B. Baas
The articles in this special section focus on parallel computing platforms in electronic design automation.
本专题的文章主要关注电子设计自动化中的并行计算平台。
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Pub Date : 2013-06-05DOI: 10.1109/MDAT.2013.2258093
S. Bhunia, D. Agrawal, L. Nazhandali
The articles in this special section focus on design of trusted systems-on-chip components and applications for their use.
这个特殊部分中的文章主要关注可信的片上系统组件的设计及其使用的应用程序。
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Pub Date : 2013-06-05DOI: 10.1109/MDAT.2013.2259096
Christopher W. Fletcher, Marten van Dijk, S. Devadas
The paper states that people are trusting the cloud more and more to perform sensitive operations. Demanding more trust in software systems is a recipe for disaster. Suppose the people only trust hardware manufacturers and cryptographers, and not system software developers, application programmers, or other software vendors. It will be the hardware manufacturer's job to produce a piece of hardware that provides some security properties. These properties will correspond to cryptographic operations being implemented correctly in the hardware and adding a modicum of physical security. The beauty of hardware is that its functionality is fixed. If we design our systems to only depend on hardware properties, then we need not worry about software changes or patches introducing new security holes-inevitable in current systems. How can it ensure privacy of data despite the practically infinite number of malicious programs out there? The Ascend processor attempts to achieve these goals; the only entity that the client has to trust is the processor itself.
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Pub Date : 2013-06-01DOI: 10.1109/MDAT.2013.2269775
A. Ivanov
h OUR INDUSTRY FACES a complex myriad of potential problems and challenges across all mediums involving design and test, and the resulting solutions and research methods used to counter experience problems are even more varied and comprehensive. Thus, it makes sense for us at some point to introduce a variety of some of the most current and striking areas of contemporary research and experimentation to our readers. While a narrower focus on selected themes is certainly a top priority for us, the reality is that our industry is varied in the truest sense of the word, and the occasional wide-issue can serve immense benefits in representing this point. This is what we have compiled in this issue; a compendium of recent, highly relevant selections that runs the gamut of problems and solutions in design and test, not only from an interindustry standpoint ranging from Trojans to 3D integration, but also from an international perspective that accounts for studies carried out across the globe. We have provided articles that should give our readers a highly interesting, yet widely informative, background on some of the most prevalent issues facing our global industry today. Indeed, our current market is filled with an ever-increasing need to go faster while maintaining fluid and efficient design; and this is a pursuit that must be highlighted on a cross-industry, global scope, if we are to fully take part in the increasing depth of international communication and collaboration. To start things off, we follow up from our last issue’s focus by providing an examination of Trojan threats due to design vulnerability with ‘‘Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.’’ A reliance on third-party hardware IP is also highlighted as a cause for concern. A protection solution is proposed to combine predeployment design with postdeployment monitoringVa comprehensive method with high hopes for future defense. Our second entry, ‘‘Exploiting Multiple Mahalanobis Distance Metric to Screen Outliers From Analogue Product Manufacturing Test Responses,’’ provides an in-depth explanation from the University of Twente, The Netherlands, of two problemswith the Mahalanobis Distance classification method, before suggesting a new, more effective method of Multiple Mahalanobis. The conclusions are exemplified by the study of a real-world automobile product. A collaboration from New York University researchers is our third entry called ‘‘ExpeditedCompact Architecture for Average Scan Power Reduction,’’ and proposes an architectural solution to strengthen the reliability of chip under test. This selection poses to minimize scan power hot spots and high heat, while upholding design flow and delivering savings in test power. From here, we travel to researchers from the University of Ferhat Abbes in Algeria for our fourth entry, who present ‘‘An Optical BILBO for On-Line Testing of Embedded Systems,’’ an online optical testing approach to detect immedia
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Pub Date : 2013-02-01DOI: 10.1109/MDT.2012.2228294
G. Smith
Gary Smith gives an outlook that looks forward all the way to 2025 and gives insight as to how parallel EDA plays a role in reducing cost.
Gary Smith对2025年进行了展望，并就并行EDA如何在降低成本方面发挥作用提出了见解。
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Pub Date : 2013-02-01DOI: 10.1109/MDAT.2013.2251831
A. Ivanov
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Pub Date : 2013-01-21DOI: 10.1109/MDAT.2014.2308364
T. Theocharides
The TTTC website has been updated to include several more features and information for its visitors! To find out more, please visit the website at http://www.ieee-tttc.org/ .
{"title":"Test Technology TC Newsletter","authors":"T. Theocharides","doi":"10.1109/MDAT.2014.2308364","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2308364","url":null,"abstract":"The TTTC website has been updated to include several more features and information for its visitors! To find out more, please visit the website at http://www.ieee-tttc.org/ .","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"3 1","pages":"602-603"},"PeriodicalIF":0.0,"publicationDate":"2013-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74015863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Mavroidis, Ioannis Mavroidis, I. Papaefstathiou
Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).
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We study the problem of hardware Trojans in wireless cryptographic integrated circuits, wherein the objective is to leak secret information (i.e. the encryption key) through the wireless channel. Using a mixed-signal system-on-chip, consisting of a DES encryption core and a UWB transmitter, we demonstrate the following three key findings of this study: i) Simple malicious modifications to the digital part of a wireless cryptographic chip suffice to leak information without changing the more sensitive analog part. We demonstrate two hardware Trojan examples, which leak the encryption key by manipulating the transmission amplitude or frequency. ii) Such hardware Trojans do not change the functionality of the digital part or the performances of the analog part and their impact on the wireless transmission parameters can be hidden within the fabrication process variations. Hence, neither traditional manufacturing testing nor recently proposed hardware Trojan detection methods will expose them. iii) For the attacker to be able to discern the leaked information from the legitimate signal, effective hardware Trojans must impose some structure to the transmission parameters. While this structure is not known to the defender, advanced statistical analysis of these parameters (i.e. transmission power), may reveal its existence and, thereby, expose the hardware Trojan.
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