The Embedded Object Concept (EOC) is a concept that utilizes common object-oriented methods used in software by applying them to combined Lego-like software-hardware entities. These modular entities represent objects in object-oriented design methods, and they function as building blocks of embedded systems. This concept enables you to build new embedded systems from electronic Lego-like building blocks. The goal of the EOC is to make designing of embedded systems faster and easier while preserving the commercial applicability of the resulting device. The EOC enables people without comprehensive knowledge in electronics design to create new embedded systems. For experts it shortens the design time of new embedded systems. This article presents the concept and two realized embedded systems: a telerobot and Painmeter.
{"title":"The Embedded Object Concept: a Lego-like Approach to Making Embedded Systems","authors":"Tero Vallius, J. Röning","doi":"10.1109/MDT.2009.103","DOIUrl":"https://doi.org/10.1109/MDT.2009.103","url":null,"abstract":"The Embedded Object Concept (EOC) is a concept that utilizes common object-oriented methods used in software by applying them to combined Lego-like software-hardware entities. These modular entities represent objects in object-oriented design methods, and they function as building blocks of embedded systems. This concept enables you to build new embedded systems from electronic Lego-like building blocks. The goal of the EOC is to make designing of embedded systems faster and easier while preserving the commercial applicability of the resulting device. The EOC enables people without comprehensive knowledge in electronics design to create new embedded systems. For experts it shortens the design time of new embedded systems. This article presents the concept and two realized embedded systems: a telerobot and Painmeter.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.103","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
System-level Functions (SLF) of microprocessors such as Memory Management and Interrupt Handling that provide hardware support to the software are hard to be verified on an FPGA prototype where the behavioral testbench building the complex software contexts can not be mapped. Traditionally, the FPGA verification task is performed by running a General Purpose Operating System (GPOS) like Linux, which is debugging inefficient and hard to be controlled. In this paper, the authors have proposed a Verification Purpose Operating System (VPOS) on FPGA to initialize machine resources and to build software contexts for directed or random tests. This framework greatly reduces the debugging complexity by seamlessly interacting with SW-simulation, and considerably increases coverage as opposed to the Linux-based method by providing high flexibility. We assess the feasibility of our approach by applying it to a microprocessor designed by our institute.
{"title":"VPOS: A Specific Operating System for the FPGA Verification of Microprocessor System-level Functions","authors":"Lingkan Gong, Jin-Qin Lu","doi":"10.1109/MDT.2009.104","DOIUrl":"https://doi.org/10.1109/MDT.2009.104","url":null,"abstract":"System-level Functions (SLF) of microprocessors such as Memory Management and Interrupt Handling that provide hardware support to the software are hard to be verified on an FPGA prototype where the behavioral testbench building the complex software contexts can not be mapped. Traditionally, the FPGA verification task is performed by running a General Purpose Operating System (GPOS) like Linux, which is debugging inefficient and hard to be controlled. In this paper, the authors have proposed a Verification Purpose Operating System (VPOS) on FPGA to initialize machine resources and to build software contexts for directed or random tests. This framework greatly reduces the debugging complexity by seamlessly interacting with SW-simulation, and considerably increases coverage as opposed to the Linux-based method by providing high flexibility. We assess the feasibility of our approach by applying it to a microprocessor designed by our institute.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.104","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45nm technology test chip to relate geometry to failure rate statistics for low-k dielectric breakdown. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to determine if low-k materials satisfy lifetime requirements in the presence of die-to-die linewidth variation.
{"title":"Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation","authors":"L. Milor","doi":"10.1109/MDT.2009.131","DOIUrl":"https://doi.org/10.1109/MDT.2009.131","url":null,"abstract":"Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45nm technology test chip to relate geometry to failure rate statistics for low-k dielectric breakdown. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to determine if low-k materials satisfy lifetime requirements in the presence of die-to-die linewidth variation.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.131","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a tutorial on the techniques and procedures used in a production test environment is presented. This overview is structured in such a way that the less experienced test engineer can learn about the common and various methods used in mixed-signal test. Various aspects related to test and their role in the manufacturing process of ICs are discussed. In fact, the paper starts off by motivating the need for testing and then describes the different methods: DC, AC, and dynamic testing as well as clocks, SerDes and RF testing. Design for Test (DFT) techniques are also described.
{"title":"An Overview of Mixed-Signal Production Test from a Measurement Principle Perspective","authors":"G. Roberts, S. Aouini","doi":"10.1109/MDT.2009.92","DOIUrl":"https://doi.org/10.1109/MDT.2009.92","url":null,"abstract":"In this article, a tutorial on the techniques and procedures used in a production test environment is presented. This overview is structured in such a way that the less experienced test engineer can learn about the common and various methods used in mixed-signal test. Various aspects related to test and their role in the manufacturing process of ICs are discussed. In fact, the paper starts off by motivating the need for testing and then describes the different methods: DC, AC, and dynamic testing as well as clocks, SerDes and RF testing. Design for Test (DFT) techniques are also described.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.92","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62466381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Balancing new reliability challenges and system performance at the architecture level","authors":"P. Kudva, J. Rivers","doi":"10.1109/MDT.2009.129","DOIUrl":"https://doi.org/10.1109/MDT.2009.129","url":null,"abstract":"","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.129","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yanjing Li, S. Mitra, Donald S. Gardner, Young Moon Kim, E. Mintarno
The biggest challenge in designing robust systems is to minimize the costs of error detection. Most existing error detection techniques suffer from high power and performance costs, and / or additional design complexity. Circuit failure prediction, together with CASP on-line diagnostics, enable design of robust systems that can effectively overcome reliability challenges associated with early-life failures and aging. The key attractive feature of such an approach is its significantly reduced power cost compared to traditional error detection. It also opens up new research opportunities across multiple abstraction layers (circuit, architecture, virtualization/OS, and applications) for designing optimized robust systems with respect to reliability requirements while balancing power, performance, area, and design complexity constraints. Such global optimization is essential for robust systems of the future.
{"title":"Overcoming Early-Life Failure and Aging Challenges for Robust System Design","authors":"Yanjing Li, S. Mitra, Donald S. Gardner, Young Moon Kim, E. Mintarno","doi":"10.1109/MDT.2009.132","DOIUrl":"https://doi.org/10.1109/MDT.2009.132","url":null,"abstract":"The biggest challenge in designing robust systems is to minimize the costs of error detection. Most existing error detection techniques suffer from high power and performance costs, and / or additional design complexity. Circuit failure prediction, together with CASP on-line diagnostics, enable design of robust systems that can effectively overcome reliability challenges associated with early-life failures and aging. The key attractive feature of such an approach is its significantly reduced power cost compared to traditional error detection. It also opens up new research opportunities across multiple abstraction layers (circuit, architecture, virtualization/OS, and applications) for designing optimized robust systems with respect to reliability requirements while balancing power, performance, area, and design complexity constraints. Such global optimization is essential for robust systems of the future.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.132","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hongbin Sun, Jibang Liu, Rakesh S. Anigundi, Nanning Zheng, James J.-Q. Lu, Rose Ken, Tong Zhang
This paper concerns appropriate 3D DRAM architecture design and the potential of using 3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM integrated computing systems. We first present a coarse-grained 3D partitioning strategy for 3D DRAM design that can well exploit the benefits provided by 3D integration without incurring stringent constraints on through-silicon via (TSV) fabrications. Targeting multi-core processors, we further present design techniques that can effectively reduce the access latency of 3D DRAM L2 cache, hence improve the overall 3D integrated computing system performance. The effectiveness of these developed design techniques have been successfully evaluated based on CACTI-based memory modeling and full system simulations over a wide spectrum of multi-programmed workloads. Simulation results show that the proposed heterogeneous 3D DRAM design can improve the harmonic mean IPC by 23.9% on average compared with a baseline scenario using 3D DRAM only as the main memory.
本文讨论了3D DRAM的结构设计，以及在3D多核处理器-DRAM集成计算系统中使用3D DRAM实现二级缓存和主存的潜力。我们首先提出了一种用于3D DRAM设计的粗粒度3D分区策略，该策略可以很好地利用3D集成提供的好处，而不会对硅通孔(TSV)制造产生严格的限制。针对多核处理器，我们进一步提出了可以有效降低3D DRAM L2缓存访问延迟的设计技术，从而提高整体3D集成计算系统的性能。这些开发的设计技术的有效性已经基于基于caci的内存建模和在广泛的多编程工作负载上的全系统仿真成功地进行了评估。仿真结果表明，与仅使用3D DRAM作为主存的基准方案相比，提出的异构3D DRAM设计可将谐波平均IPC平均提高23.9%。
{"title":"Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems","authors":"Hongbin Sun, Jibang Liu, Rakesh S. Anigundi, Nanning Zheng, James J.-Q. Lu, Rose Ken, Tong Zhang","doi":"10.1109/MDT.2009.93","DOIUrl":"https://doi.org/10.1109/MDT.2009.93","url":null,"abstract":"This paper concerns appropriate 3D DRAM architecture design and the potential of using 3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM integrated computing systems. We first present a coarse-grained 3D partitioning strategy for 3D DRAM design that can well exploit the benefits provided by 3D integration without incurring stringent constraints on through-silicon via (TSV) fabrications. Targeting multi-core processors, we further present design techniques that can effectively reduce the access latency of 3D DRAM L2 cache, hence improve the overall 3D integrated computing system performance. The effectiveness of these developed design techniques have been successfully evaluated based on CACTI-based memory modeling and full system simulations over a wide spectrum of multi-programmed workloads. Simulation results show that the proposed heterogeneous 3D DRAM design can improve the harmonic mean IPC by 23.9% on average compared with a baseline scenario using 3D DRAM only as the main memory.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.93","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62466389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract—In this paper, we propose a novel simulation fault injection method for the dependability analysis of complex SoCs using 32 nm technology. In previous simulation fault injections, the original simulation model is modified to implement a saboteur module or many mutants. This creates a problem since the architectural complexity of current SoCs is expected to increase rapidly in the 32 nm era. Furthermore, the modification process may incur additional tasks, such as verification and validation of the modified simulation model. Our simulation fault injection environment uses the modified SystemC simulation kernel augmented for fault injection experiments. The proposed methodology offers the following advantages over previous simulation fault injection methods. First, it does not require changes in the target simulation design model. Second, it minimizes the simulation hardware resource requirements and simulation time. Third, it allows mixed simulation of the ESL model and the register transfer level model using wrappers. To demonstrate the effectiveness of the proposed methodology, we designed the SystemC models of MIPS and TMR MIPS processors and ran the benchmark SW from MiBench to compare the failure rates of the two processors.
{"title":"A Novel Simulation Fault Injection using Electronic Systems Level Simulation Models","authors":"Jongwhoa Na","doi":"10.1109/MDT.2009.128","DOIUrl":"https://doi.org/10.1109/MDT.2009.128","url":null,"abstract":"Abstract—In this paper, we propose a novel simulation fault injection method for the dependability analysis of complex SoCs using 32 nm technology. In previous simulation fault injections, the original simulation model is modified to implement a saboteur module or many mutants. This creates a problem since the architectural complexity of current SoCs is expected to increase rapidly in the 32 nm era. Furthermore, the modification process may incur additional tasks, such as verification and validation of the modified simulation model. Our simulation fault injection environment uses the modified SystemC simulation kernel augmented for fault injection experiments. The proposed methodology offers the following advantages over previous simulation fault injection methods. First, it does not require changes in the target simulation design model. Second, it minimizes the simulation hardware resource requirements and simulation time. Third, it allows mixed simulation of the ESL model and the register transfer level model using wrappers. To demonstrate the effectiveness of the proposed methodology, we designed the SystemC models of MIPS and TMR MIPS processors and ran the benchmark SW from MiBench to compare the failure rates of the two processors.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.128","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An interconnect strategy for a heterogeneous processor","authors":"M. Kuehnle, A. Deledda","doi":"10.1109/MDT.2009.160","DOIUrl":"https://doi.org/10.1109/MDT.2009.160","url":null,"abstract":"","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.160","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bias temperature instability (BTI) in MOSFETs in one of the major reliability challenges in nano-scale technology. This paper evaluates the severity of Negative BTI (NBTI) degradation in two major circuit applications: random logic and memory array. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. Simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memories results in severe READ stability degradation, especially when combined with random process variation. Moreover, in scaled technology nodes, finite number of Si-H bonds in the channel can induce a statistical random variation in the degradation process. Simulations using 32nm/22nm Predictive Technology Model (PTM) shows that statistical random variation of NBTI, on top of random dopant fluctuation (RDF) results in significant random Vt variation in PMOS transistors, resulting in considerable degradation in static noise margin (SNM) of memory cells.
{"title":"Reliability Implications of NBTI in Digital Integrated Circuits","authors":"S. P. Park, Kunhyuk Kang, K. Roy","doi":"10.1109/MDT.2009.133","DOIUrl":"https://doi.org/10.1109/MDT.2009.133","url":null,"abstract":"Bias temperature instability (BTI) in MOSFETs in one of the major reliability challenges in nano-scale technology. This paper evaluates the severity of Negative BTI (NBTI) degradation in two major circuit applications: random logic and memory array. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. Simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memories results in severe READ stability degradation, especially when combined with random process variation. Moreover, in scaled technology nodes, finite number of Si-H bonds in the channel can induce a statistical random variation in the degradation process. Simulations using 32nm/22nm Predictive Technology Model (PTM) shows that statistical random variation of NBTI, on top of random dopant fluctuation (RDF) results in significant random Vt variation in PMOS transistors, resulting in considerable degradation in static noise margin (SNM) of memory cells.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.133","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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