1 RuleML 2016 also hosted the RuleML Doctoral Consortium and the 10th International Rule Challenge. Moreover, it was co-located with DecisionCAMP, a popular event for Decision Management practitioners. As it is clear from Paul's report, this co-location promoted interaction opportunities for the rule-based community and the industrial decision-modeling community. 2 Organized in cooperation with ACM SIGLOG and ACM SIGPLAN, FSCD 2016 gathered together, for the first time, two well-established conferences: RTA (Rewriting Techniques and Applications) and TLCA (Typed Lambda Calculi and Applications). As Sandra describes in her report, this first installment of the new FSCD conference was a resounding success. Considering the main conference and the 11 co-located events, there were 135 talks — an impressive number by any standard. I am most grateful to Paul and Sandra for their reports. As usual, I look forward to receiving your personal impressions and/or reports on conferences and meetings broadly related to SIGLOG. Your ideas and suggestions for future installments of the column are also most welcome.
{"title":"Conference reports","authors":"Jorge A. Pérez","doi":"10.1109/MDT.2004.54","DOIUrl":"https://doi.org/10.1109/MDT.2004.54","url":null,"abstract":"1 RuleML 2016 also hosted the RuleML Doctoral Consortium and the 10th International Rule Challenge. Moreover, it was co-located with DecisionCAMP, a popular event for Decision Management practitioners. As it is clear from Paul's report, this co-location promoted interaction opportunities for the rule-based community and the industrial decision-modeling community. 2 Organized in cooperation with ACM SIGLOG and ACM SIGPLAN, FSCD 2016 gathered together, for the first time, two well-established conferences: RTA (Rewriting Techniques and Applications) and TLCA (Typed Lambda Calculi and Applications). As Sandra describes in her report, this first installment of the new FSCD conference was a resounding success. Considering the main conference and the 11 co-located events, there were 135 talks — an impressive number by any standard. I am most grateful to Paul and Sandra for their reports. As usual, I look forward to receiving your personal impressions and/or reports on conferences and meetings broadly related to SIGLOG. Your ideas and suggestions for future installments of the column are also most welcome.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"54 1","pages":"350-353"},"PeriodicalIF":0.0,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73485250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/MDAT.2014.2355093
K. Bergman
With power dissipation severely limiting the frequency scaling of microprocessors, the emergence of chip multiprocessors (CMPs) had shifted computingto embrace highly parallel multicore architectures. Realizing performance in these newgenerations of chips is becoming increasingly dependent on how efficiently applications can exploit the growing number of parallel resources. Whereas computation power as measured in FLOPs was the key metric of past microprocessors, performance in today?s CMPs is dominated by data movement challenges. In this so-called ``communications bound?? era of computing, new technologies are sought that can deliver energy-efficient high-bandwidth interconnectivity. While optics is a natural communications technology with broad success in long-haul fiber optic telecommunications, integration at the chip scale, particularly with silicon, had been challenging.
{"title":"A Tale of Two Technology Disruptions","authors":"K. Bergman","doi":"10.1109/MDAT.2014.2355093","DOIUrl":"https://doi.org/10.1109/MDAT.2014.2355093","url":null,"abstract":"With power dissipation severely limiting the frequency scaling of microprocessors, the emergence of chip multiprocessors (CMPs) had shifted computingto embrace highly parallel multicore architectures. Realizing performance in these newgenerations of chips is becoming increasingly dependent on how efficiently applications can exploit the growing number of parallel resources. Whereas computation power as measured in FLOPs was the key metric of past microprocessors, performance in today?s CMPs is dominated by data movement challenges. In this so-called ``communications bound?? era of computing, new technologies are sought that can deliver energy-efficient high-bandwidth interconnectivity. While optics is a natural communications technology with broad success in long-haul fiber optic telecommunications, integration at the chip scale, particularly with silicon, had been challenging.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"31 1","pages":"87-88"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2014.2355093","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/MDAT.2014.2349277
E. Marinissen
Presents an interview with Dr. Aart De Geus, founder of Synopsys, an EDA worldwide supplier.
介绍了对新思公司(EDA全球供应商)创始人Aart De Geus博士的采访。
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Pub Date : 2014-10-01DOI: 10.1109/MDAT.2014.2355512
S. Pasricha, Yi Xu
The articles in this special section discuss the applications and services provided by silison nanophotonics for multicore network architectures. The need for high-performance and energy-efficient communication between processing cores has never been more critical. The increase in core counts in emerging chip multiprocessors (CMPs) has put more pressure on the communication fabric to support many more streams of high bandwidth data transfers than ever before. An important consequence of this trend is that chip power and performance are now beginning to be dominated not by processor cores but by the components that facilitate transport of data between processors and to memory.
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Pub Date : 2014-10-01DOI: 10.1109/mdat.2014.2355391
A. Ivanov
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Pub Date : 2014-08-07DOI: 10.1109/MDAT.2014.2337234
S. Davidson
h I ARRIVED AT my friend George’s new house as the temperature outside had begun to drop. The place was bigger than I had expected. I rang the doorbell, which played a clip of John Lennon singing ‘‘Money.’’ George opened the door and greeted me. The living room, as usual had one couch, one small table, two chairs, and about a dozen servers. Still, it was impressive. ‘‘How did you score this place?’’ I asked George. Housing in the Bay Area was hot these days. ‘‘I got lucky,’’ George said. ‘‘The guy who owned it before made his money in Alabama, heard about bitcoins, and came here to cash in.’’ George grinned. ‘‘By selling leather-tooled purses for them. It turns out that just like some people don’t want to buy a house where someone died, around here they don’t buy houses where businesses died. Except this is more serious because money is involved.’’ ‘‘So what’s your new big idea?’’ I asked. ‘‘Everyone’s doing Internet-of-Things startups, net-enabling everything from refrigerators to picture frames to thermostats. So I’m doing it too. Just about everything in this house is smart. ‘‘But that’s not enough to differentiate a startup.’’ George continued. ‘‘Then it came to me. If all your appliances talk to one another, it might be a good idea to be able to listen in.’’ I rolled my eyes. ‘‘That’s a bogus idea, even for you,’’ I told him. ‘‘The computer illiterate are sure going to want to look at packet counts.’’ ‘‘You are correct. My system translates the commands into English, and it has an AI to interpret the commands in the context of the house’s environment.’’ George looked at his smart watch. ‘‘You’re just in time to see the heating and cooling system go into action. Follow me.’’ We went into a gigantic room. One wall was lined with windows, all closed and curtained to keep out the afternoon heat. George led me to the interior wall, which had speakers, displays, a thermostat, and what turned out to be a thermometer. ‘‘The thermometer displays temperatures from inside as well as from a bunch of temperature sensors outside. That way the house can figure out the exact time to turn off the air conditioning and open the windows.’’ He pushed a button. ‘‘Let’s listen in.’’ Thermostat: Temperature outside cool enough. Air conditioner off, curtains up, windows, open. AC: Off? It’s stifling in here. Windows: Which way is open? Curtains: If I fold up I get all creased. Thermostat: Windows, open is up. Air conditioner off. AC: I’ll compromise. I’ll set myself up five degrees. Window: Which way is up? Curtains: You see, no one cares about us. We’re just window dressing. Thermostat: Air conditioner off already. Curtains, the iron can smooth you out. Window, up is toward the ceiling. Curtains: Okay. We like Iron. He’s hot. Going up now. Windows: What’s a ceiling? Thermostat: *&*$%$# Just flex. Windows. Flexing. Oh, that open. Thermostat: Air conditioner, set yourself to 99 degrees.
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Pub Date : 2014-08-01DOI: 10.1109/MDAT.2014.2343311
A. Ivanov
h THIS ISSUE OF IEEE Design & Test brings to our readers a selection of highly progressive and relevant topics, focusing intently on solutions to some of today’s most challenging areas facing the design, manufacturing, and deployment of complex ICs and systems on chip. The articles highlight advances in yield improvement, design methodologies, testing, diagnosis, and temperature and power management in 3-D ICs and mixed signal circuits. I am again very pleased to present another timely issue on the fringe of our industry’s progression. By reading the articles, as I mention below, they all very much address the bottom line! This usually matters to most if not all of us! Read on! Our first article will be of interest to a broad set of constituents, from designers, to process engineers, to quality assurance personnel, and more. It comes from an international group of authors ranging from Cadence Design Systems, to UCLA and the Missouri University of Science and Technology, to Nanyang Technological University in Singapore. It is a wellknown fact that process variations in deeply scaled technologies create major design and fabrication challenges. Accurately predicting yield for analog and mixed signal circuits is equally challenging but extremely important to the success of a product and company. The article here is focused precisely on yield estimation. The authors present two distinct approaches, one that is referred to as a performance domain method, and a second referred to as a parameter domain method. The authors present a thorough analysis of the tradeoffs of these two approaches through a number of circuit examples and quantitative comparisons of the efficiency of the two different methods. The second article, by a group of Taiwanese authors, moves us back to the emerging world of 3-D ICs and yield. The authors focused their work on the integrity of interconnects in 3-D ICs, which has major impact on yield of such chips. They address design for testability, built-in self-test, and defect diagnosis and repair in 3-D ICs that are based on through silicon vias (TSVs) and interposers. The claimed improvement results are significant and should make a difference to the bottom line! Following this, Bhagavatula et al. from Purdue University present a detailed view of the issues faced in the development and implementation of real-time power sensors that may be the key to successful and cost-effective intelligent power management in highperformance ICs and systems. The authors make the point that the need for accurate on-chip estimation of load currents is critical. They present a proposed solution approach to this challenge and discuss broader issues surrounding power management. Rounding out this general-interest issue, an article by Huang and Huang from the National Tsing Hua University in Taiwan takes us back to a test and yield/binning problem with 3-D TSV ICs. The authors present the usefulness of a cell-based phaselocked loop that can be synthesi
这一期的IEEE设计与测试为我们的读者带来了一系列高度进步和相关的主题，专注于解决当今一些最具挑战性的领域，这些领域面临着复杂的集成电路和芯片系统的设计、制造和部署。文章重点介绍了3-D集成电路和混合信号电路在产量改进、设计方法、测试、诊断、温度和电源管理方面的进展。我再次非常高兴地在我们行业发展的边缘提出另一个及时的问题。通过阅读这些文章，正如我在下面提到的，它们都非常关注底线!这对我们大多数人来说都很重要。继续读下去!我们的第一篇文章将会引起很多人的兴趣，从设计人员到过程工程师，再到质量保证人员等等。它来自一个国际作者小组，包括Cadence Design Systems、加州大学洛杉矶分校(UCLA)、密苏里科技大学(Missouri University of Science and Technology)和新加坡南洋理工大学(Nanyang Technological University)。众所周知，深度规模化技术中的工艺变化会带来重大的设计和制造挑战。准确预测模拟和混合信号电路的良率同样具有挑战性，但对产品和公司的成功极为重要。本文的重点是产量估计。作者提出了两种不同的方法，一种称为性能域方法，另一种称为参数域方法。作者通过一些电路实例和两种不同方法效率的定量比较，对这两种方法的权衡进行了彻底的分析。第二篇文章由一群台湾作者撰写，将我们带回到新兴的3d集成电路和收益率世界。作者将他们的工作重点放在3-D集成电路互连的完整性上，这对这类芯片的成品率有重大影响。它们解决了基于硅通孔(tsv)和中间体的3-D集成电路的可测试性设计、内置自检以及缺陷诊断和修复。声称的改进结果是显著的，应该对底线产生影响!在此之后，来自普渡大学的Bhagavatula等人详细介绍了实时功率传感器的开发和实施所面临的问题，这些问题可能是高性能集成电路和系统中成功且具有成本效益的智能电源管理的关键。作者指出，对负载电流进行精确的片上估计是至关重要的。他们提出了一种针对这一挑战的拟议解决方案，并讨论了围绕电源管理的更广泛问题。台湾国立清华大学的Huang和Huang撰写的一篇文章将我们带回到3d TSV集成电路的测试和yield/binning问题，以解决这个普遍感兴趣的问题。作者提出了一种基于单元的锁相环的实用性，该锁相环可以“自动”合成以产生达到1ghz的片上时钟信号。他们展示了这样一个时钟如何能够用于精确地检测TSV泄漏的3-D集成电路。同样，人们会期望这样的方法对底线产生影响。为了拓展读者的思维和兴趣，一篇教程文章将我们带到了机械工程的世界，更具体地说，是
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Pub Date : 2014-02-24DOI: 10.1109/MDAT.2013.2295761
P. Pande, A. Kalyanaraman
The articles in this special section focus on hardware acceleration in the field of computational biology.
这个特殊部分的文章主要关注计算生物学领域的硬件加速。
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Pub Date : 2014-02-01DOI: 10.1109/MDAT.2014.2299596
S. Davidson
h HARDWARE ACCELERATION IN Computational Biology is the theme of this issue of IEEE Design & Test. In graduate school, a long time I worked on the acceleration of things that used to be considered compute-intensive, such as compilers. Then I was involved in the acceleration of fault simulation through special purpose hardware. None of these efforts was successful. Advances in general purpose computing technology outpaced that of acceleration, so our speed advantage shrank by the time these accelerators were ready. Since work today is leveraging general purpose hardware like GPUs and FPGAs, this shouldn’t be a problem. But a bigger problem was that our target applications were for a limited market, so the investment in developing acceleration wasn’t worth it. Maybe we can find some other things out there with a vast number of users that we could accelerate. Perhaps in the future, we’ll see ads like the following.
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Pub Date : 2014-02-01DOI: 10.1109/MDAT.2014.2302039
A. Ivanov
Welcome to 2014! h FOLLOWING DECEMBER 2013’S special year end issue on the slowing effects of variability and aging in ICs and systems, to start this new volume of D&T we bring you to a completely different space. In this issue, we take a focused look into the growing computational challenges associated with molecular biology research. The generation of biological data is now happening at unprecedented rates, and processing rates have not really kept pace. Such processing has typically been carried out in software on standard desktop computing platforms, but this situation is changing. This issue explores such changes and highlights some of the hardware-based approaches and corresponding algorithms that have been developed to enable highly desired biological data processing acceleration. Our first article, by Majumder et al., dives into the specifics of high-speed rates of data generation in molecular biology research. The article compares the performance of emerging hardware platforms with other applications across the field of computational biology. Second, an article by Aluru and Jammula provides a wider scope investigation by presenting surveys on FPGA and GPU hardware accelerators in biological sequence analysis, as well as research on acceleration resulting from examining high-throughput sequencing and applications. Our third submission, authored by Liu and Schmidt, presents two critical computing techniques for CUDA-enabled GPUs that allow fast alignments to accelerate the CUSHAW2 algorithm, supported by the alignments of simulated and real reads to the human genome. Next, Schlachter et al. investigate the problem of resource utilization in molecular dynamics simulations. They focus on non-dedicated high-end clusters and propose additional modules to supplement existing workflow and resource managers. They report on two molecular simulations and validate the performance benefits that their proposed approaches bring. Following this, authors Savran, Gao, and Bakos discuss improvements to the memory usage and performance of their GPU kernel, which performs large-scale short sequence dataset pair wise alignments. The authors have established a possible new record in large-scale alignments. To conclude this discussion of computational biology acceleration, an article by Chrysos et al. presents a number of informative case studies that exemplify how modern hybrid systems with FPGAbased reconfigurable computing platforms can offer large speed-ups and savings in bioinformatics algorithms. Our last three feature articles touch on more general interest topics. The first is an article by Yilmaz, Nassery, and Ozev that outlines and confirms the accuracy of built-in EVM measurement techniques that use QAM modulation and avoid high DFT overheads. Following this, Jenihhin et. al present an approach to design error localization that combines statistical analysis of VHDL code items with static slicing. The authors demonstrate the efficiency of their approa
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