Pub Date : 2012-12-01DOI: 10.1109/MDT.2012.2209392
R. Staszewski
In this review article, the author revisits the digitization journey of wireless systems and the motivations that have driven this research field, gives a brief yet concise summary of state-of-the-art solutions, and offers insights for future developments.
{"title":"Digitally intensive wireless transceivers","authors":"R. Staszewski","doi":"10.1109/MDT.2012.2209392","DOIUrl":"https://doi.org/10.1109/MDT.2012.2209392","url":null,"abstract":"In this review article, the author revisits the digitization journey of wireless systems and the motivations that have driven this research field, gives a brief yet concise summary of state-of-the-art solutions, and offers insights for future developments.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"7-18"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2209392","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/MDT.2012.2210380
J. Buurma, R. Sayah, F. Valente, C. Rodgers
This paper presents the details of a standard, named OpenDFM, which describes an efficient method to ensure manufacturability of integrated circuits that are designed at advanced technology nodes of today and one that can scale to address similar issues at future nodes as well. OpenDFM uses a meta-language format to capture and improve critical patterns that must be tested to ensure correct manufacturing and thus enhance yield.
{"title":"OpenDFM Bridging the Gap Between DRC and DFM","authors":"J. Buurma, R. Sayah, F. Valente, C. Rodgers","doi":"10.1109/MDT.2012.2210380","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210380","url":null,"abstract":"This paper presents the details of a standard, named OpenDFM, which describes an efficient method to ensure manufacturability of integrated circuits that are designed at advanced technology nodes of today and one that can scale to address similar issues at future nodes as well. OpenDFM uses a meta-language format to capture and improve critical patterns that must be tested to ensure correct manufacturing and thus enhance yield.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"84-90"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/MDT.2012.2210533
Markus Seuring, M. Braun, Alan Ma, G. Eide, Kathy Yang, Huaxing Tang
This paper focuses on the V4-2007 extension of the Standard Test Data Format (STDF). STDF has been used as the standard representation for logging test data from automatic test equipment (ATE). This format however lacked a key capability, i.e., storing scan test results. The V4-2007 extension of this standard, as described in this paper, provides details on its ability in efficiently storing scan test results. Thus this standard now provides a complete and unified repository to store the results of parametric tests, functional tests and scan tests, all in a consistent format to aid in fault diagnosis and yield learning. This has in turn simplified the test flow and tracking of all necessary data to ensure more time-efficient testing and failure diagnosis.
{"title":"Employing the STDF V4-2007 Standard for Scan Test Data Logging","authors":"Markus Seuring, M. Braun, Alan Ma, G. Eide, Kathy Yang, Huaxing Tang","doi":"10.1109/MDT.2012.2210533","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210533","url":null,"abstract":"This paper focuses on the V4-2007 extension of the Standard Test Data Format (STDF). STDF has been used as the standard representation for logging test data from automatic test equipment (ATE). This format however lacked a key capability, i.e., storing scan test results. The V4-2007 extension of this standard, as described in this paper, provides details on its ability in efficiently storing scan test results. Thus this standard now provides a complete and unified repository to store the results of parametric tests, functional tests and scan tests, all in a consistent format to aid in fault diagnosis and yield learning. This has in turn simplified the test flow and tracking of all necessary data to ensure more time-efficient testing and failure diagnosis.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"91-99"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210533","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-09DOI: 10.1109/MDT.2012.2199612
K. Chakrabarty
This forward-looking special section highlights a number of bio-design challenges to that the electronic design automation (EDA) community can explore, and it illustrates the many similarities and some key differences between EDA and synthetic biology. Guest Editors Doug Denmore and Soha Hassoun have put together this special section. They had to reach out to researchers who are from outside the traditional design and test community. The editor-in-chief welcomes these contributions from experts in parallel research areas, and hopes that D&T can develop longer-term alliances and attract readers and contributors from allied disciplines. The articles in the special section include a tutorial by the guest editors on synthetic biology and design using complementary methods of bottom-up assembly of genetic circuits and a higher-level approach based on the modification of genetic pathways. The next three articles cover the landscape of research advances, ranging from digital signal processing using molecular reactions, simulation of synthetic biology systems, and mathematically modeling of the dynamics in biological systems. A perspectives article on the convergence of EDA with synthetic biology provides historical context andmakes some bold predictions. Readerswill also find our regular Last Byte column that blends fact with fiction and provides a "creative" look at synthetic biology. This issue of D&T also includes three non-theme articles on system design. These include design space exploration of parallel, embedded hardware for executing Clifford algebra operations, hardware IP protection for secure ICs, and formal modeling to enable the verification of the on-chip communication fabric. Finally, the issue includes an article that highlights organizational dynamics and its relationship to team productivity in the semiconductor industry.
{"title":"Looking ahead at the role of electronic design automation in synthetic biology [From the EIC]","authors":"K. Chakrabarty","doi":"10.1109/MDT.2012.2199612","DOIUrl":"https://doi.org/10.1109/MDT.2012.2199612","url":null,"abstract":"This forward-looking special section highlights a number of bio-design challenges to that the electronic design automation (EDA) community can explore, and it illustrates the many similarities and some key differences between EDA and synthetic biology. Guest Editors Doug Denmore and Soha Hassoun have put together this special section. They had to reach out to researchers who are from outside the traditional design and test community. The editor-in-chief welcomes these contributions from experts in parallel research areas, and hopes that D&T can develop longer-term alliances and attract readers and contributors from allied disciplines. The articles in the special section include a tutorial by the guest editors on synthetic biology and design using complementary methods of bottom-up assembly of genetic circuits and a higher-level approach based on the modification of genetic pathways. The next three articles cover the landscape of research advances, ranging from digital signal processing using molecular reactions, simulation of synthetic biology systems, and mathematically modeling of the dynamics in biological systems. A perspectives article on the convergence of EDA with synthetic biology provides historical context andmakes some bold predictions. Readerswill also find our regular Last Byte column that blends fact with fiction and provides a \"creative\" look at synthetic biology. This issue of D&T also includes three non-theme articles on system design. These include design space exploration of parallel, embedded hardware for executing Clifford algebra operations, hardware IP protection for secure ICs, and formal modeling to enable the verification of the on-chip communication fabric. Finally, the issue includes an article that highlights organizational dynamics and its relationship to team productivity in the semiconductor industry.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"115 1","pages":"4"},"PeriodicalIF":0.0,"publicationDate":"2012-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74547359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-09DOI: 10.1109/MDT.2012.2194610
A. Sangiovanni-Vincentelli
Before the 1970s, design automation was used more intensely in mechanical and civil engineering. In the 1970s, it became clear that the design of electrical and electronic circuits could be greatly aided by software tools. These tools enabled the creation of a novel electronic design automation (EDA) industry that claimed its space in the software industry. Today there is not a single IC company that does not use EDA tools. But because of this fact, EDA's overall market is saturated and enjoys modest growth. Much has been talked about extending EDA in the system space. To the rescue of a difficult path to double digit growth in EDA comes Synthetic Biology! Synthetic biology is about the synthesis of complex biological systems to obtain behaviors that do not exist in nature. A METHODOLOGY HAS come to the rescue within the past decade to reduce complexity, and to provide abstraction and design composability. The methodology is based on the availability of biological primitives: DNA-encoded 'Parts' are designed and then assembled to create modular 'Devices' that can be integrated into a host organism or assembled into a larger 'System.' This process resembles very much what we do today with integrated circuits. This methodology has enabled the development of design tools and a new discipline has emerged: Biology Design Automation (BDA). Workshops related to biodesign automation are appearing at traditional EDA venues (DAC), bioinformatics conferences (ISMB), and synthetic biology meetings (SB X.0). The way for EDA to extend to a new exciting field through the systematic construction of biological circuits maybe bumpy with detours, but eventually will enable the creation of a new industry by providing tools that make the design of living systems a true engineering discipline which is safe and effective.
{"title":"EDA meets biology! The bumpy road ahead [Perscetives]","authors":"A. Sangiovanni-Vincentelli","doi":"10.1109/MDT.2012.2194610","DOIUrl":"https://doi.org/10.1109/MDT.2012.2194610","url":null,"abstract":"Before the 1970s, design automation was used more intensely in mechanical and civil engineering. In the 1970s, it became clear that the design of electrical and electronic circuits could be greatly aided by software tools. These tools enabled the creation of a novel electronic design automation (EDA) industry that claimed its space in the software industry. Today there is not a single IC company that does not use EDA tools. But because of this fact, EDA's overall market is saturated and enjoys modest growth. Much has been talked about extending EDA in the system space. To the rescue of a difficult path to double digit growth in EDA comes Synthetic Biology! Synthetic biology is about the synthesis of complex biological systems to obtain behaviors that do not exist in nature. A METHODOLOGY HAS come to the rescue within the past decade to reduce complexity, and to provide abstraction and design composability. The methodology is based on the availability of biological primitives: DNA-encoded 'Parts' are designed and then assembled to create modular 'Devices' that can be integrated into a host organism or assembled into a larger 'System.' This process resembles very much what we do today with integrated circuits. This methodology has enabled the development of design tools and a new discipline has emerged: Biology Design Automation (BDA). Workshops related to biodesign automation are appearing at traditional EDA venues (DAC), bioinformatics conferences (ISMB), and synthetic biology meetings (SB X.0). The way for EDA to extend to a new exciting field through the systematic construction of biological circuits maybe bumpy with detours, but eventually will enable the creation of a new industry by providing tools that make the design of living systems a true engineering discipline which is safe and effective.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"49-50"},"PeriodicalIF":0.0,"publicationDate":"2012-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2194610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/MDT.2012.2209053
S. Krolikoski
The author considers the question: what if a member of an IEEE SA Working Group either has a granted or pending essential patent (or personally knows that his/her employer owns such a patent), and keeps that information secret despite the regular "calls for essential patents" made at the start of each Working Group meeting? The brief answer in the IEEEs case is that such deviant behavior is grounds for suspension or expulsion from the IEEE-SA for an individual, a representative of an entity or the entity itself depending on how widespread the deception itself. The case can also be referred by PatCom with a recommendation to the IEEE Standards Association Standards Board for appropriate action. Si2, another standards setting organization (SSO), has a different way of handling such a case, which the author describes using a flow chart of its patent policy flow. It is seen that any Si2 member that tried to subvert the system by not disclosing an necessary patent claim until after an Si2 standard was approved and published, will have necessary already agreed to issue a "Reasonable and Nondiscriminatory" (RAND) license on the necessary patents.
{"title":"Two Approaches to Handling Late Essential/Necessary Patent Claims Against Standards","authors":"S. Krolikoski","doi":"10.1109/MDT.2012.2209053","DOIUrl":"https://doi.org/10.1109/MDT.2012.2209053","url":null,"abstract":"The author considers the question: what if a member of an IEEE SA Working Group either has a granted or pending essential patent (or personally knows that his/her employer owns such a patent), and keeps that information secret despite the regular \"calls for essential patents\" made at the start of each Working Group meeting? The brief answer in the IEEEs case is that such deviant behavior is grounds for suspension or expulsion from the IEEE-SA for an individual, a representative of an entity or the entity itself depending on how widespread the deception itself. The case can also be referred by PatCom with a recommendation to the IEEE Standards Association Standards Board for appropriate action. Si2, another standards setting organization (SSO), has a different way of handling such a case, which the author describes using a flow chart of its patent policy flow. It is seen that any Si2 member that tried to subvert the system by not disclosing an necessary patent claim until after an Si2 standard was approved and published, will have necessary already agreed to issue a \"Reasonable and Nondiscriminatory\" (RAND) license on the necessary patents.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"102-104"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2209053","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/MDT.2012.2214271
S. Davidson
Disneyland (CA, USA) will once again set the stage for International Test Conference (ITC), hosting the 43rd annual TestWeek event from 4-9 November 2012. ITC is a technology conference that is dedicated to the electronic test of devices, boards and systems. Preview ITC through the Advance Program found on ITC's website at http://itctestweek.org. Check out this year's panels that will help you in distinguish fantasy from reality. Panel 2, "Are Industrial Test Problems Real Problems? I Thought Research Has Solved Them All!" looks at how those paid-to-dream academics and the paid-to-implement industrialists can cooperate to turn fantasy into reality. Learn how realistic fantasy and fantastic reality meld to form to the future of test. Entrepreneurs and venture capitalists are paid to turn fantasy into reality. The special "ATE/Test Vision 2020: Entrepreneurship in Test CEO Panel" will let you see how they do it.
{"title":"ITC - Where fantasy becomes reality","authors":"S. Davidson","doi":"10.1109/MDT.2012.2214271","DOIUrl":"https://doi.org/10.1109/MDT.2012.2214271","url":null,"abstract":"Disneyland (CA, USA) will once again set the stage for International Test Conference (ITC), hosting the 43rd annual TestWeek event from 4-9 November 2012. ITC is a technology conference that is dedicated to the electronic test of devices, boards and systems. Preview ITC through the Advance Program found on ITC's website at http://itctestweek.org. Check out this year's panels that will help you in distinguish fantasy from reality. Panel 2, \"Are Industrial Test Problems Real Problems? I Thought Research Has Solved Them All!\" looks at how those paid-to-dream academics and the paid-to-implement industrialists can cooperate to turn fantasy into reality. Learn how realistic fantasy and fantastic reality meld to form to the future of test. Entrepreneurs and venture capitalists are paid to turn fantasy into reality. The special \"ATE/Test Vision 2020: Entrepreneurship in Test CEO Panel\" will let you see how they do it.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"112-112"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2214271","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/MDT.2012.2223511
K. Chakrabarty
This issue of IEEE Design & Test of Computers (D&T) is focused on the theme of smarter silicon for achieving predictable performance and high reliability without the need for significant guard banding. Guest Editors Mohammad Tehranipoor and LeRoy Winemberg have taken the initiative and worked diligently to put together this special issue with a set of five selected articles, which include contributions by experts from both academia and industry. These articles cover a number of aspects of smarter silicon, including onchip structures for monitoring aging, voltage and frequency scaling to proactively prevent errors, a study of the relationship between performance degradation and operating conditions, optimization of SerDes, and hardware Trojan detection. This issue of D&T also includes the annual International Test Conference (ITC) special section. Candidate papers were selected from ITC 2011 and they went through the regular D&T review process. After review, three papers were selected for inclusion in the ITC special section. A fourth paper from ITC 2011 is being published as a "prize paper." The paper titled "Physically-Aware Analysis of Systematic Defects in Integrated Circuits" is based on the PhD thesis of Chiu-Wing (Jason) Tam, who won the E. J. McCluskey Best 2012 Doctoral Thesis Award in 2011.
本期IEEE计算机设计与测试(D&T)聚焦于智能硅的主题，以实现可预测的性能和高可靠性，而无需显着的保护带。特邀编辑Mohammad Tehranipoor和LeRoy Winemberg主动并勤奋地将这期特刊与五篇精选文章组合在一起，其中包括来自学术界和工业界的专家的贡献。这些文章涵盖了智能硅的许多方面，包括用于监测老化的片上结构，主动预防错误的电压和频率缩放，性能下降与操作条件之间关系的研究，SerDes的优化以及硬件木马检测。本期《D&T》还包括年度国际测试会议(ITC)专题。候选论文从ITC 2011中选出，并通过常规的D&T审查程序。经评审，三篇论文入选ITC专题。ITC 2011年的第四篇论文将作为“获奖论文”发表。这篇题为“集成电路系统缺陷的物理感知分析”的论文是基于2011年获得E. J. McCluskey 2012年最佳博士论文奖的Chiu-Wing (Jason) Tam的博士论文。
{"title":"Towards smarter silicon and data-driven design of integrated circuits [From the EIC]","authors":"K. Chakrabarty","doi":"10.1109/MDT.2012.2223511","DOIUrl":"https://doi.org/10.1109/MDT.2012.2223511","url":null,"abstract":"This issue of IEEE Design & Test of Computers (D&T) is focused on the theme of smarter silicon for achieving predictable performance and high reliability without the need for significant guard banding. Guest Editors Mohammad Tehranipoor and LeRoy Winemberg have taken the initiative and worked diligently to put together this special issue with a set of five selected articles, which include contributions by experts from both academia and industry. These articles cover a number of aspects of smarter silicon, including onchip structures for monitoring aging, voltage and frequency scaling to proactively prevent errors, a study of the relationship between performance degradation and operating conditions, optimization of SerDes, and hardware Trojan detection. This issue of D&T also includes the annual International Test Conference (ITC) special section. Candidate papers were selected from ITC 2011 and they went through the regular D&T review process. After review, three papers were selected for inclusion in the ITC special section. A fourth paper from ITC 2011 is being published as a \"prize paper.\" The paper titled \"Physically-Aware Analysis of Systematic Defects in Integrated Circuits\" is based on the PhD thesis of Chiu-Wing (Jason) Tam, who won the E. J. McCluskey Best 2012 Doctoral Thesis Award in 2011.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"7 1","pages":"4-5"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2223511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/MDT.2012.2212533
M. Tehranipoor, L. Winemberg
This special issue presents novel on-chip structures for monitoring aging and variations in the circuit, analyzing circuit operation condition's impact on aging and performance degradation, agingaware power/performance tuning, interoperability and optimization for SerDes, and finally using onchip power monitors for detection of hardware Trojans in integrated circuits. Five papers were selected for publication in this special issue.
{"title":"Guest Editors' introduction: On-chip structures for smarter silicon","authors":"M. Tehranipoor, L. Winemberg","doi":"10.1109/MDT.2012.2212533","DOIUrl":"https://doi.org/10.1109/MDT.2012.2212533","url":null,"abstract":"This special issue presents novel on-chip structures for monitoring aging and variations in the circuit, analyzing circuit operation condition's impact on aging and performance degradation, agingaware power/performance tuning, interoperability and optimization for SerDes, and finally using onchip power monitors for detection of hardware Trojans in integrated circuits. Five papers were selected for publication in this special issue.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"6-7"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2212533","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-08-13DOI: 10.1109/MDT.2012.2211561
J. Keane, C. Kim, Qunzeng Liu, S. Sapatnekar
This paper describes the use of sensing schemes that drive on-chip process and aging variation measurements in manufactured silicon.
本文描述了驱动片上工艺和老化变化测量的传感方案的使用。
{"title":"Process and Reliability Sensors for Nanoscale CMOS","authors":"J. Keane, C. Kim, Qunzeng Liu, S. Sapatnekar","doi":"10.1109/MDT.2012.2211561","DOIUrl":"https://doi.org/10.1109/MDT.2012.2211561","url":null,"abstract":"This paper describes the use of sensing schemes that drive on-chip process and aging variation measurements in manufactured silicon.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"8-17"},"PeriodicalIF":0.0,"publicationDate":"2012-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2211561","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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