Pub Date : 2019-11-05DOI: 10.1007/s10617-019-09226-1
Wilayat Khan, David Sanán, Zhé Hóu, Liu Yang
{"title":"On embedding a hardware description language in Isabelle/HOL","authors":"Wilayat Khan, David Sanán, Zhé Hóu, Liu Yang","doi":"10.1007/s10617-019-09226-1","DOIUrl":"https://doi.org/10.1007/s10617-019-09226-1","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"23 1","pages":"123 - 151"},"PeriodicalIF":1.4,"publicationDate":"2019-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-019-09226-1","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46859486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-20DOI: 10.1007/s10617-019-09223-4
Marcelo Ruaro, L. L. Caimi, Vinicius Fochi, F. Moraes
{"title":"Memphis: a framework for heterogeneous many-core SoCs generation and validation","authors":"Marcelo Ruaro, L. L. Caimi, Vinicius Fochi, F. Moraes","doi":"10.1007/s10617-019-09223-4","DOIUrl":"https://doi.org/10.1007/s10617-019-09223-4","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"23 1","pages":"103 - 122"},"PeriodicalIF":1.4,"publicationDate":"2019-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-019-09223-4","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45010085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-12DOI: 10.1007/s10617-019-09222-5
Zongkai Liu, Xiaoqiang Yang, J. Shen
{"title":"Optimization of multitask parallel mobile edge computing strategy based on deep learning architecture","authors":"Zongkai Liu, Xiaoqiang Yang, J. Shen","doi":"10.1007/s10617-019-09222-5","DOIUrl":"https://doi.org/10.1007/s10617-019-09222-5","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"24 1","pages":"129 - 143"},"PeriodicalIF":1.4,"publicationDate":"2019-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-019-09222-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44259461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-14DOI: 10.1007/s10617-019-09221-6
Jaishree Mayank, Arijit Mondal, A. Sarkar
{"title":"Control-schedule co-design for fast stabilization in real time systems facing repeated reconfigurations","authors":"Jaishree Mayank, Arijit Mondal, A. Sarkar","doi":"10.1007/s10617-019-09221-6","DOIUrl":"https://doi.org/10.1007/s10617-019-09221-6","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"23 1","pages":"79 - 101"},"PeriodicalIF":1.4,"publicationDate":"2019-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-019-09221-6","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-30DOI: 10.1007/s10617-019-09220-7
Neng Hou, Xiaohu Yan, Fazhi He
In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion.
{"title":"A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design","authors":"Neng Hou, Xiaohu Yan, Fazhi He","doi":"10.1007/s10617-019-09220-7","DOIUrl":"https://doi.org/10.1007/s10617-019-09220-7","url":null,"abstract":"In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion.","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"49 3","pages":"57-77"},"PeriodicalIF":1.4,"publicationDate":"2019-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-22DOI: 10.1007/s10617-019-09219-0
José Augusto Miranda Nacif,Marcio Seiji Oyamada
{"title":"Special issue with selected papers from 2017 Brazilian Symposium on Computer Engineering (SBESC 2017)","authors":"José Augusto Miranda Nacif,Marcio Seiji Oyamada","doi":"10.1007/s10617-019-09219-0","DOIUrl":"https://doi.org/10.1007/s10617-019-09219-0","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"1 1","pages":""},"PeriodicalIF":1.4,"publicationDate":"2019-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-05DOI: 10.1007/s10617-018-09218-7
Ivan Luiz Pedroso Pires, Marco Antonio Zanata Alves, Luiz Carlos Pessoa Albini
Simulation is one of the main tools used to analyze and test new proposals in the Network-on-Chip field. Several simulators can be found in the literature, among them the Noxim simulator stands out. It is being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the system and its features. The correct workload can lead to rapid and efficient system development, while the wrong one may compromise the entire system evaluation. To ensure a more realistic simulation, simulators usually relies on real workloads by using a trace-driven approach. Although Noxim provides a simple support for input traces, it is very limited to a general behavior of the system, accepting only a generic injection rate parameter over time. Another important part of the simulator is the ability to consider the Processing Elements processing time. We propose in this paper an extension of the Noxim simulator to address these issues. Consequently, results are more realistic and may be possible to predict the total execution time very accurately. This extension is demonstrated and evaluated using the NAS-NPB workload.
{"title":"Trace-driven and processing time extensions for Noxim simulator","authors":"Ivan Luiz Pedroso Pires, Marco Antonio Zanata Alves, Luiz Carlos Pessoa Albini","doi":"10.1007/s10617-018-09218-7","DOIUrl":"https://doi.org/10.1007/s10617-018-09218-7","url":null,"abstract":"Simulation is one of the main tools used to analyze and test new proposals in the Network-on-Chip field. Several simulators can be found in the literature, among them the Noxim simulator stands out. It is being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the system and its features. The correct workload can lead to rapid and efficient system development, while the wrong one may compromise the entire system evaluation. To ensure a more realistic simulation, simulators usually relies on real workloads by using a trace-driven approach. Although Noxim provides a simple support for input traces, it is very limited to a general behavior of the system, accepting only a generic injection rate parameter over time. Another important part of the simulator is the ability to consider the Processing Elements processing time. We propose in this paper an extension of the Noxim simulator to address these issues. Consequently, results are more realistic and may be possible to predict the total execution time very accurately. This extension is demonstrated and evaluated using the NAS-NPB workload.","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"7 4","pages":"41-55"},"PeriodicalIF":1.4,"publicationDate":"2019-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-30DOI: 10.1007/s10617-018-9217-0
A. L. Sartor, P. H. E. Becker, A. C. S. Beck
{"title":"A fast and accurate hybrid fault injection platform for transient and permanent faults","authors":"A. L. Sartor, P. H. E. Becker, A. C. S. Beck","doi":"10.1007/s10617-018-9217-0","DOIUrl":"https://doi.org/10.1007/s10617-018-9217-0","url":null,"abstract":"","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"31 1","pages":"3 - 19"},"PeriodicalIF":1.4,"publicationDate":"2018-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10617-018-9217-0","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52170409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-29DOI: 10.1007/s10617-018-9216-1
José Carlos da Silva, Flávio Assis
Industrial environments are typically characterised by high levels of interference. Therefore, standards for industrial wireless sensor networks (WirelessHART, ISA 100.11a, and IEEE 802.15.4e) have defined a time division and multichannel-based mode of operation, in which pairs of time slots and channels are assigned to links representing communication between nodes. In IEEE 802.15.4e this mode of operation is called Timed Slotted Channel Hopping. In this paper we describe a distributed algorithm to define such an assignment for a given network. The algorithm is efficient, scalable and was developed for the Signal-to-Interference-plus-Noise-Ratio model, currently considered the most appropriate to analyse algorithms for wireless networks when interference is taken into consideration. In particular, the algorithm provides deterministic communication in the network. Previous approaches to this problem are mainly centralised, based on a simple (or none) interference model, do not provide deterministic communication or do not consider multiple physical channels. In this paper we describe the algorithm and present results of simulation, where we evaluated the number of rounds needed for computing the schedules and the size of the produced schedules. The described algorithm applies also to the Internet of Things, characterised by high scale and presence of interference.
{"title":"A distributed algorithm to schedule TSCH links under the SINR model","authors":"José Carlos da Silva, Flávio Assis","doi":"10.1007/s10617-018-9216-1","DOIUrl":"https://doi.org/10.1007/s10617-018-9216-1","url":null,"abstract":"Industrial environments are typically characterised by high levels of interference. Therefore, standards for industrial wireless sensor networks (WirelessHART, ISA 100.11a, and IEEE 802.15.4e) have defined a time division and multichannel-based mode of operation, in which pairs of time slots and channels are assigned to links representing communication between nodes. In IEEE 802.15.4e this mode of operation is called <i>Timed Slotted Channel Hopping</i>. In this paper we describe a distributed algorithm to define such an assignment for a given network. The algorithm is efficient, scalable and was developed for the <i>Signal-to-Interference-plus-Noise-Ratio</i> model, currently considered the most appropriate to analyse algorithms for wireless networks when interference is taken into consideration. In particular, the algorithm provides <i>deterministic</i> communication in the network. Previous approaches to this problem are mainly centralised, based on a simple (or none) interference model, do not provide deterministic communication or do not consider multiple physical channels. In this paper we describe the algorithm and present results of simulation, where we evaluated the number of rounds needed for computing the schedules and the size of the produced schedules. The described algorithm applies also to the <i>Internet of Things</i>, characterised by high scale and presence of interference.","PeriodicalId":50594,"journal":{"name":"Design Automation for Embedded Systems","volume":"14 2","pages":"21-39"},"PeriodicalIF":1.4,"publicationDate":"2018-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138524181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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