Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457213
Kyu Hyun Choi, Taeho Hwang
Processing-in-Memory (PIM) has garnered attention as a platform for large language model inference due to its ability to perform computations within memory, leveraging the internal bandwidth of memory components. In data center environments, to execute AI models across multiple nodes, an inference server is typically deployed at the data center's frontend. This server orchestrates the assignment of AI inference tasks to the appropriate nodes. This paper presents the construction of an open source-based inference server designed for easy deployment of a PIM platform grounded in data flow architecture within a data center setting. We have conducted operational tests on large language models to validate the efficacy of our approach.
{"title":"Building an Inference Server Platform for Large Language Models Using Dataflow PIM Platform","authors":"Kyu Hyun Choi, Taeho Hwang","doi":"10.1109/ICEIC61013.2024.10457213","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457213","url":null,"abstract":"Processing-in-Memory (PIM) has garnered attention as a platform for large language model inference due to its ability to perform computations within memory, leveraging the internal bandwidth of memory components. In data center environments, to execute AI models across multiple nodes, an inference server is typically deployed at the data center's frontend. This server orchestrates the assignment of AI inference tasks to the appropriate nodes. This paper presents the construction of an open source-based inference server designed for easy deployment of a PIM platform grounded in data flow architecture within a data center setting. We have conducted operational tests on large language models to validate the efficacy of our approach.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"323 7","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457182
An Kyung-Chan, Jun-Ying Li, Chu-Feng Yang, Ng Si En Timothy, Shibi Varku, Qinjie Wu, Priyanka Kajal, N. Mathews, Arindam Basu, Tony Tae-Hyoung Kim
This work presents a hand gesture recognition system for a single photovoltaic(PV) cell and provides a comparison and insight into several gesture recognition algorithms. The photovoltaic cell based on halide perovskites is used for a single sensor for hand gesture recognition. The multi-layer perceptron(MLP) classification algorithm was selected to recognize hand gestures from a PV cell after testing and comparing different algorithms. Using the proposed MLP classification algorithm, our proposed hand-gesture recognition system can provide 100% accuracy on our collected dataset.
{"title":"A Dynamic Gesture Recognition Algorithm Using Single Halide Perovskite Photovoltaic Cell for Human-Machine Interaction","authors":"An Kyung-Chan, Jun-Ying Li, Chu-Feng Yang, Ng Si En Timothy, Shibi Varku, Qinjie Wu, Priyanka Kajal, N. Mathews, Arindam Basu, Tony Tae-Hyoung Kim","doi":"10.1109/ICEIC61013.2024.10457182","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457182","url":null,"abstract":"This work presents a hand gesture recognition system for a single photovoltaic(PV) cell and provides a comparison and insight into several gesture recognition algorithms. The photovoltaic cell based on halide perovskites is used for a single sensor for hand gesture recognition. The multi-layer perceptron(MLP) classification algorithm was selected to recognize hand gestures from a PV cell after testing and comparing different algorithms. Using the proposed MLP classification algorithm, our proposed hand-gesture recognition system can provide 100% accuracy on our collected dataset.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"141 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457160
Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo
This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy.
{"title":"Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application","authors":"Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo","doi":"10.1109/ICEIC61013.2024.10457160","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457160","url":null,"abstract":"This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"172 3","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457243
Saeyeon Kim, Sohyeon Kim, Hannah Yang, Heejin Roh, Jiyoung Lee, Ji-Hoon Kim
The importance of video compression technology is highly emphasized according to the advancement of display technology which plays a crucial role in many industries. Video compression technology is important in the aspect of reducing bandwidth usage, optimizing storage space, and enhancing the efficiency of data transmission. Video Electronics Standards Association (VESA) Display Compression-M (VDC-M) video compression standard [1], as released by the VESA, shows high compression ratio and high performance. In this paper, we propose a hardware architecture for transform entropy decoding which supports the VDC-M standard. It can extract and align quantized coefficients which are transmitted from encoder to decoder for reconstruction. The utilization of optimized entropy coding techniques enhances the overall performance, making the proposed hardware architecture contribute to advanced video compression in modern display technologies.
{"title":"Optimized Transform Entropy Decoding Architecture for VDC-M","authors":"Saeyeon Kim, Sohyeon Kim, Hannah Yang, Heejin Roh, Jiyoung Lee, Ji-Hoon Kim","doi":"10.1109/ICEIC61013.2024.10457243","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457243","url":null,"abstract":"The importance of video compression technology is highly emphasized according to the advancement of display technology which plays a crucial role in many industries. Video compression technology is important in the aspect of reducing bandwidth usage, optimizing storage space, and enhancing the efficiency of data transmission. Video Electronics Standards Association (VESA) Display Compression-M (VDC-M) video compression standard [1], as released by the VESA, shows high compression ratio and high performance. In this paper, we propose a hardware architecture for transform entropy decoding which supports the VDC-M standard. It can extract and align quantized coefficients which are transmitted from encoder to decoder for reconstruction. The utilization of optimized entropy coding techniques enhances the overall performance, making the proposed hardware architecture contribute to advanced video compression in modern display technologies.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"170 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a CMOS analog front-end (AFE) for hall sensor readout IC. A three- operational amplifier-based instrumentation amplifier (IA) is employed for low noise amplification with high common mode rejection ratio. To address the input offset of the hall magnetic sensor, an internal offset cancellation circuit using a R-2R DAC is adopted. A 2nd order incremental ADC is used to convert the amplified analog input into 16-bit digital output. The proposed AFE is implemented in an 80nm CMOS process. It achieves a 6.8nV2 of the output noise power at a voltage gain of 40V/V and consumes 16.8mW from a 2.8V power supply.
{"title":"A CMOS Analog Front-End for Hall Sensor Readout IC","authors":"Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, Gil-Cho Ahn","doi":"10.1109/ICEIC61013.2024.10457102","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457102","url":null,"abstract":"This paper presents a CMOS analog front-end (AFE) for hall sensor readout IC. A three- operational amplifier-based instrumentation amplifier (IA) is employed for low noise amplification with high common mode rejection ratio. To address the input offset of the hall magnetic sensor, an internal offset cancellation circuit using a R-2R DAC is adopted. A 2nd order incremental ADC is used to convert the amplified analog input into 16-bit digital output. The proposed AFE is implemented in an 80nm CMOS process. It achieves a 6.8nV2 of the output noise power at a voltage gain of 40V/V and consumes 16.8mW from a 2.8V power supply.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"158 2","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457186
Heuijee Yun, Daejin Park
At the moment, autonomous driving requires a lot of sensors: cameras, lidar, etc. It takes a lot of time and resources to process all the input data from these sensors. In this paper, we reduce the processing time and resources of lidar and camera data by parallelizing the input data of autonomous vehicles. Cameras mounted on autonomous vehicles are often wide-angle or have multiple angles of view. These multiple camera inputs are flattened and processed in parallel, and then YOLO is used to combine the 3D data from the lidar with the 2D inputs from the camera. By combining cameras from multiple angles and processing them in parallel, except where they overlap, you can reduce the time it would take to process each image serially. This algorithm is also highly scalable as it can be applied to a single camera rather than multiple camera sensors. Experiments were conducted using KITTY and YOLO with labelled 3D lidar data and 2D image data. The FPS is 7.98, which is fast, and the parallel processing reduces the time by about 1.4 times.
{"title":"Parallel Processing of 3D Object Recognition by Fusion of 2D Images and LiDAR for Autonomous Driving","authors":"Heuijee Yun, Daejin Park","doi":"10.1109/ICEIC61013.2024.10457186","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457186","url":null,"abstract":"At the moment, autonomous driving requires a lot of sensors: cameras, lidar, etc. It takes a lot of time and resources to process all the input data from these sensors. In this paper, we reduce the processing time and resources of lidar and camera data by parallelizing the input data of autonomous vehicles. Cameras mounted on autonomous vehicles are often wide-angle or have multiple angles of view. These multiple camera inputs are flattened and processed in parallel, and then YOLO is used to combine the 3D data from the lidar with the 2D inputs from the camera. By combining cameras from multiple angles and processing them in parallel, except where they overlap, you can reduce the time it would take to process each image serially. This algorithm is also highly scalable as it can be applied to a single camera rather than multiple camera sensors. Experiments were conducted using KITTY and YOLO with labelled 3D lidar data and 2D image data. The FPS is 7.98, which is fast, and the parallel processing reduces the time by about 1.4 times.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"369 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An emulation method for geometry-dependent cryogenic effects in bulk CMOS technology based on the PSP model is proposed. By properly selecting and adjusting geometry- and temperature-independent/dependent parameters in the PSP model, characteristic changes of transistors due to cryogenic effects can be emulated using existing commercial process design kits (PDKs). To emulate the increased threshold voltage (Vth) and mobility (μ) due to cryogenic effects, the parameter values of VFBO, STBETO, and STMUEO are modified. To model the geometry-dependent cryogenic effects, the parameter values of STVFBLW and STVFBL for Vth and STBETL for μ are modified. To validate the proposed method, a 23-stage inverter-based ring oscillator was designed and evaluated, using the proposed emulation method based on commercial PDK of 28-nm bulk CMOS technology.
{"title":"PSP Model-Based Emulation Method for Geometry-Dependent Cryogenic Effects in 28-nm Bulk CMOS Technology","authors":"Seunghoon Yi, Hee-Cheol Joo, Seung Chae Jung, Yoochang Kim, Young-Ha Hwang","doi":"10.1109/ICEIC61013.2024.10457168","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457168","url":null,"abstract":"An emulation method for geometry-dependent cryogenic effects in bulk CMOS technology based on the PSP model is proposed. By properly selecting and adjusting geometry- and temperature-independent/dependent parameters in the PSP model, characteristic changes of transistors due to cryogenic effects can be emulated using existing commercial process design kits (PDKs). To emulate the increased threshold voltage (Vth) and mobility (μ) due to cryogenic effects, the parameter values of VFBO, STBETO, and STMUEO are modified. To model the geometry-dependent cryogenic effects, the parameter values of STVFBLW and STVFBL for Vth and STBETL for μ are modified. To validate the proposed method, a 23-stage inverter-based ring oscillator was designed and evaluated, using the proposed emulation method based on commercial PDK of 28-nm bulk CMOS technology.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457199
Janghoo Lee, Youngjin Kim, Hyekang Park, Seoyun Kim, Seyong Choi, S. Moon, Wei Lei, Byoung Seong Bae
The flat panel detector (FPD) detecting X-ray has several applications like medical imaging, security checks, and industrial inspection. Nowadays, an active pixel sensor (APS) is applied for X-ray detectors composed of three transistors normally. One is for reset of the circuit and the other two are for amplification and readout. This fundamental structure offers advantages in terms of high resolution, rapid detection speed, and heightened sensitivity. However, the output signal is reliant on electrical parameters, particularly the threshold voltage and mobility of the amplifying transistor, which can vary for various reasons. To mitigate this variability, compensation methods, both internal and external, have been explored. In this research, we introduce an innovative internal compensation pixel circuit tailored for X-ray detectors and validate its performance through simulations based on amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The simulation results indicate that our proposed pixel circuit demonstrates remarkable resilience, with only a -0.16% and 0.04% error rate when threshold voltage variation falls within the range of ±0.5 V, in contrast to the 10% variation observed in conventional pixel circuits.
探测 X 射线的平板探测器（FPD）有多种应用，如医疗成像、安全检查和工业检测。如今，有源像素传感器（APS）被应用于 X 射线探测器，通常由三个晶体管组成。其中一个用于电路复位，另外两个用于放大和读出。这种基本结构具有分辨率高、检测速度快和灵敏度高等优点。然而，输出信号依赖于电气参数，特别是放大晶体管的阈值电压和迁移率，这些参数会因各种原因而变化。为了减少这种变化，人们探索了内部和外部补偿方法。在这项研究中，我们介绍了一种为 X 射线探测器量身定制的创新型内部补偿像素电路，并通过基于非晶铟镓锌氧化物（a-IGZO）薄膜晶体管（TFT）的仿真验证了其性能。仿真结果表明，我们提出的像素电路具有出色的恢复能力，当阈值电压变化在 ±0.5 V 范围内时，误差率仅为 -0.16% 和 0.04%，而传统像素电路的误差率为 10%。
{"title":"Internal Compensation X-Ray Detector Pixel Circuit with IGZO TFT and Perovskite Single Crystal","authors":"Janghoo Lee, Youngjin Kim, Hyekang Park, Seoyun Kim, Seyong Choi, S. Moon, Wei Lei, Byoung Seong Bae","doi":"10.1109/ICEIC61013.2024.10457199","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457199","url":null,"abstract":"The flat panel detector (FPD) detecting X-ray has several applications like medical imaging, security checks, and industrial inspection. Nowadays, an active pixel sensor (APS) is applied for X-ray detectors composed of three transistors normally. One is for reset of the circuit and the other two are for amplification and readout. This fundamental structure offers advantages in terms of high resolution, rapid detection speed, and heightened sensitivity. However, the output signal is reliant on electrical parameters, particularly the threshold voltage and mobility of the amplifying transistor, which can vary for various reasons. To mitigate this variability, compensation methods, both internal and external, have been explored. In this research, we introduce an innovative internal compensation pixel circuit tailored for X-ray detectors and validate its performance through simulations based on amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The simulation results indicate that our proposed pixel circuit demonstrates remarkable resilience, with only a -0.16% and 0.04% error rate when threshold voltage variation falls within the range of ±0.5 V, in contrast to the 10% variation observed in conventional pixel circuits.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"126 9","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457220
Kyudan Jung, Seungmin Bae, Nam Joon Kim, Hyun Gon Ryu, Hyuk-Jae Lee
Recently, there has been a growing interest in conversational artificial intelligence (AI). As a result, research is actively being conducted on automatic speech recognition (ASR) to facilitate interactions between humans and machines. This paper proposes a system that enhances ASR performance. The proposed method accumulates images captured from lecture videos in real-time every 30 seconds. The frequency ratios between text data from captured images and text data calculated offline from over 333K are used to improve the ASR performance. Experimental results showed that the word error rate (WER) decreased by a maximum of 0.68% compared to using only the traditional ASR. Especially, the recognition rate for specialized terms frequently used in lectures showed an improvement of 64%.
最近，人们对对话式人工智能（AI）的兴趣与日俱增。因此，人们正在积极开展自动语音识别（ASR）方面的研究，以促进人类与机器之间的互动。本文提出了一种可提高 ASR 性能的系统。所提出的方法每 30 秒实时累积从讲座视频中捕获的图像。捕获图像中的文本数据与从超过 333K 文本数据中离线计算出的文本数据之间的频率比被用来提高 ASR 性能。实验结果表明，与仅使用传统 ASR 相比，词错误率（WER）最大降低了 0.68%。特别是对讲座中常用专业术语的识别率提高了 64%。
{"title":"Improving ASR Performance with OCR Through Using Word Frequency Difference","authors":"Kyudan Jung, Seungmin Bae, Nam Joon Kim, Hyun Gon Ryu, Hyuk-Jae Lee","doi":"10.1109/ICEIC61013.2024.10457220","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457220","url":null,"abstract":"Recently, there has been a growing interest in conversational artificial intelligence (AI). As a result, research is actively being conducted on automatic speech recognition (ASR) to facilitate interactions between humans and machines. This paper proposes a system that enhances ASR performance. The proposed method accumulates images captured from lecture videos in real-time every 30 seconds. The frequency ratios between text data from captured images and text data calculated offline from over 333K are used to improve the ASR performance. Experimental results showed that the word error rate (WER) decreased by a maximum of 0.68% compared to using only the traditional ASR. Especially, the recognition rate for specialized terms frequently used in lectures showed an improvement of 64%.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-28DOI: 10.1109/ICEIC61013.2024.10457091
Jiho Park, Heehun Yang, Donghun Lee, Hoyoung Yoo
In this paper, we propose a novel Ring-Oscillator Physical Unclonable Functions (RO-PUF) architecture using Programmable Delay Lines (PDL) in Field Programmable Gate Arrays (FPGA). Our proposed PUF uses PDL to change the propagation path inside the Look Up Table (LUT), thereby changing the output of RO. Depending on the output of the changed RO, different response outputs occur for the same RO-PUF architecture and challenge input. We have examined how the challenge-response pairs of the proposed PUF structure change according to the PDL. Additionally, we have analyzed the performance changes of the proposed PUF, finding that HDinter showed a maximum difference of 7. 1248%, and HDintra showed a maximum difference of 3.9731%. We confirm that the performance of the proposed PUF structure can vary depending on the PDL, and our research results will provide an optimal PUF structure solution to enhance the performance of PUF.
{"title":"Physical Unclonable Function Using Programmable Delay Lines","authors":"Jiho Park, Heehun Yang, Donghun Lee, Hoyoung Yoo","doi":"10.1109/ICEIC61013.2024.10457091","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457091","url":null,"abstract":"In this paper, we propose a novel Ring-Oscillator Physical Unclonable Functions (RO-PUF) architecture using Programmable Delay Lines (PDL) in Field Programmable Gate Arrays (FPGA). Our proposed PUF uses PDL to change the propagation path inside the Look Up Table (LUT), thereby changing the output of RO. Depending on the output of the changed RO, different response outputs occur for the same RO-PUF architecture and challenge input. We have examined how the challenge-response pairs of the proposed PUF structure change according to the PDL. Additionally, we have analyzed the performance changes of the proposed PUF, finding that HDinter showed a maximum difference of 7. 1248%, and HDintra showed a maximum difference of 3.9731%. We confirm that the performance of the proposed PUF structure can vary depending on the PDL, and our research results will provide an optimal PUF structure solution to enhance the performance of PUF.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"376 6","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：