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2024 International Conference on Electronics, Information, and Communication (ICEIC)最新文献

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An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery 基于时钟和数据恢复的 32-Gb/s 和全速率相位插值器分析
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457116
Dong-Hoe Heo, Tae-Hyeon Kim, Kwang-Ho Lee, Min-Seong Choo
This paper presents a 32-Gb/s full-rate clock and data recovery (CDR) architecture based on a phase interpolator (PI), which incorporates high-speed channel equalization to widen the ppm tolerance or locking range. This work focuses on the receiver-side implementation. Therefore, the feed-forward equalizer (FFE) tap is not utilized, and only the voltage swing level is adjusted at the transmitter side. The channel is modeled using Verilog language with a -10 dB loss at 10 GHz. The overall architecture comprises several components: a continuous-time linear equalizer (CTLE), 1-tap decision feedback equalizer (DFE), 7-bit PI, digital loop filter, and 2x oversampling phase detector. By individually employing the DFE and CTLE, the optimal tap coefficient value for the DFE, which produces the widest eye pattern, and the pole and zero positions of the CTLE are determined. Finally, CTLE and 1-tap DFE ensure optimal vertical 322 mV and timing margin of 25.8 ps. It also relaxes phase modulation to obtain acceptable error of the phase interpolator up to ±15625 ppm.
本文介绍了一种基于相位细分器(PI)的 32 Gb/s 全速率时钟和数据恢复(CDR)架构,该架构采用了高速信道均衡技术,以扩大 ppm 容差或锁定范围。这项工作的重点是接收器侧的实现。因此,没有使用前馈均衡器(FFE)抽头,仅在发送器侧调整了电压摆幅电平。信道使用 Verilog 语言建模,在 10 GHz 时损耗为 -10 dB。整体架构由几个部分组成:连续时间线性均衡器(CTLE)、1 抽头决策反馈均衡器(DFE)、7 位 PI、数字环路滤波器和 2 倍超采样相位检测器。通过单独使用 DFE 和 CTLE,确定了 DFE 的最佳抽头系数值(可产生最宽的眼图)以及 CTLE 的极点和零点位置。最后,CTLE 和单抽头 DFE 可确保最佳垂直 322 mV 和 25.8 ps 的时序余量。它还放松了相位调制,使相位内插器的误差达到 ±15625 ppm。
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引用次数: 0
A Method of Extending the Transmission and Reception Range of Ultrasonic Sensors for Stable Following in a Narrow Indoor Space 一种扩大超声波传感器发射和接收范围的方法,以便在狭窄的室内空间稳定跟踪
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457255
Ga-Young Kim, Su-Hong Eom, Eunghyuk Lee, Jeon-Min Kang
This study proposes a following method based on ultrasonic sensors in consideration of the situation that requires collaboration while performing autonomous driving-based service robot tasks. Since it is impossible to follow the target when it is outside the transmission and reception range of ultrasonic sensors, this study proposes a method of extending the range by changing the angle of the ultrasonic sensor. It was confirmed that the proposed method can extend the transmission and reception range in comparing the transmission and reception range with the basic sensor installation method in which ultrasonic sensors are installed facing the front with each other.
本研究考虑到在执行基于自动驾驶的服务机器人任务时需要协作的情况,提出了一种基于超声波传感器的跟踪方法。由于在超声波传感器的发射和接收范围之外无法跟踪目标,本研究提出了通过改变超声波传感器的角度来扩大跟踪范围的方法。结果表明,与超声波传感器正面安装的基本传感器安装方法相比,本研究提出的方法可以扩大发射和接收范围。
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引用次数: 0
An Effective Meta-Learning Network Model for No-Reference Image Quality Assessment 用于无参考图像质量评估的有效元学习网络模型
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457155
Donghyeon Lim, Changhoon Yim
The use of meta-learning has been proven efficient to address the limitations of insufficient data for no-reference image quality assessment (NR-IQA). While meta-learning methods have been developed as training process, the works for appropriate network models were not sufficient, which posed limitations on performance improvement. The goal of this work is to design a suitable network model for meta-learning to enhance NR-IQA performance. The proposed method follows the training process of optimization-based meta-learning for each distortion type. The proposed network model learns efficiently distortion-specific features and adapts easily to unknown distortions. Experimental results show that the proposed network model provides superior performance than the previous NR-IQA methods using meta-learning.
事实证明,使用元学习可以有效解决无参考图像质量评估(NR-IQA)数据不足的局限性。虽然元学习方法已被开发为训练过程,但合适的网络模型的工作并不充分,这对性能的提高造成了限制。这项工作的目标是为元学习设计一个合适的网络模型,以提高 NR-IQA 性能。所提出的方法针对每种失真类型都采用了基于优化的元学习训练过程。所提出的网络模型能有效学习特定失真特征,并能轻松适应未知失真。实验结果表明,与之前使用元学习的 NR-IQA 方法相比,所提出的网络模型具有更优越的性能。
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引用次数: 0
Real-time Semantic Segmentation with Bilateral Patch Attention 利用双侧补丁注意进行实时语义分割
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457099
Minseok Kang, Minhyeok Lee, Sangyoun Lee
Semantic segmentation, a fundamental task in computer vision, has evolved significantly with the introduction of deep learning techniques, particularly fully convolutional networks (FCNs). In the context of real-time semantic segmentation, the demand for efficient yet accurate models has grown, particularly for resource-constrained devices. Recent advancements have explored the fusion of global context and local details through bidirectional network structures, exemplified by BiSeNet, STDCNet, and DDRNet. However, issues of pixel inconsistency within the same object classification persist. Attention-based models like SETR and SegFormer have shown promise in mitigating this issue by capturing intricate spatial dependencies. This paper introduces the concept of ‘Mask Disarrange’ and proposes a lightweight attention mechanism suitable for real-time semantic segmentation. The Cross Patch Attention (CPA) and Inter Patch Attention (IPA) methods are presented, addressing fusion and mask disarrange challenges while maintaining computational efficiency. Experimental results on the Cityscapes dataset demonstrate the effectiveness of the proposed Bilateral Patch-Net (BPNet) in achieving superior segmentation performance and increased frames per second (FPS) compared to the state-of-the-art PIDNet. BPNet's contributions lie in its simplicity, efficiency, and applicability to diverse domains, offering potential for broader adoption in computer vision applications.
语义分割是计算机视觉领域的一项基本任务,随着深度学习技术的引入,尤其是全卷积网络(FCN)的引入,语义分割技术得到了长足的发展。在实时语义分割的背景下,对高效而准确的模型的需求与日俱增,尤其是对于资源受限的设备而言。最近的进展是通过双向网络结构探索全局上下文和局部细节的融合,例如 BiSeNet、STDCNet 和 DDRNet。然而,同一物体分类中像素不一致的问题依然存在。SETR 和 SegFormer 等基于注意力的模型通过捕捉错综复杂的空间依赖关系,有望缓解这一问题。本文介绍了 "掩码错乱 "的概念,并提出了一种适用于实时语义分割的轻量级注意力机制。本文介绍了跨补丁关注(CPA)和补丁间关注(IPA)方法,在保持计算效率的同时,解决了融合和掩码错乱的难题。在城市景观数据集上的实验结果表明,与最先进的 PIDNet 相比,所提出的双边补丁网(BPNet)在实现卓越的分割性能和提高每秒帧数(FPS)方面非常有效。BPNet 的贡献在于它的简单性、高效性和对不同领域的适用性,为计算机视觉应用提供了更广泛的应用潜力。
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引用次数: 0
Spatial-Temporal Flood Hazard Mapping Using Integration of Telemetry Data and Prediction Model 利用遥测数据和预测模型的整合绘制时空洪水灾害图
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457113
Pornnapa Panyadee, P. Champrasert
The flood early warning system can help mitigate the resulting damages by predicting future events. This is achieved through the utilization of data obtained from telemetry stations to predict the values of water levels in the future. Flood hazard maps are considered a tool for representing the potential flood events that occur in an area. This paper proposed a framework to apply the spatial and temporal data to generate flood hazard mapping using the integration of interpolation telemetry station data and a temporal prediction model. The framework consists of two components: 1) the temporal prediction model is applied to water level prediction on hourly and daily scales, and 2) the interpolation of spatial data to generate a flood hazard map. The evaluation results show that the hourly and daily temporal prediction models can predict the water level with an average of MAPE using 500 iterations are 3.17% and 4.88% of training, and 3.48% and 4.72% of testing. Then, the flood hazard map is generated. The accuracy is 70.90% and F1-score is 81.50% compared to the observation flood event.
洪水预警系统可以通过预测未来事件,帮助减轻由此造成的损失。这是通过利用从遥测站获得的数据来预测未来的水位值来实现的。洪水灾害图被认为是表示一个地区可能发生的洪水事件的工具。本文提出了一个应用空间和时间数据的框架,通过整合插值遥测站数据和时间预测模型来生成洪水灾害图。该框架由两部分组成:1)将时间预测模型应用于每小时和每天尺度的水位预测;2)对空间数据进行插值,生成洪水灾害图。评估结果表明,每小时和每天的时间预测模型都能预测水位,迭代 500 次训练的平均 MAPE 为 3.17% 和 4.88%,测试的平均 MAPE 为 3.48% 和 4.72%。然后,生成洪水灾害图。与观测洪水事件相比,准确率为 70.90%,F1 分数为 81.50%。
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引用次数: 0
Efficient Dual-Mode Generalized Spatial Modulation Detection with Enhanced DNN Architecture 利用增强型 DNN 架构进行高效双模广义空间调制检测
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457089
Zihui Wang, Xueqin Jiang, Jinming Yu, Miaowen Wen, Jun Li, Han Hai
Dual-mode generalized spatial modulation (DM-GSM) enhances spectral efficiency in GSM systems using two modes across transmit antennas. However, interference between antennas poses a challenge for signal detection. For this, a deep learning detector, the dual-mode deep neural network (DM-DNN), is proposed. The DM-DNN enables simultaneous detection of the antenna mode and modulation symbol through its network structure and label generation. A loss function is proposed to train the DM-DNN, approximating optimal bit error rate (BER) performance. Simulation results demonstrate that the DM-DNN achieves BER performance close to the maximum likelihood (ML) detector while significantly reducing complexity.
双模广义空间调制(DM-GSM)通过在发射天线上使用两种模式来提高 GSM 系统的频谱效率。然而,天线之间的干扰给信号检测带来了挑战。为此,我们提出了一种深度学习检测器--双模深度神经网络(DM-DNN)。DM-DNN 可通过其网络结构和标签生成同时检测天线模式和调制符号。为训练 DM-DNN 提出了近似最佳误码率 (BER) 性能的损失函数。仿真结果表明,DM-DNN 的误码率性能接近最大似然 (ML) 检测器,同时大大降低了复杂性。
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引用次数: 0
Efficient CRC-BCH Unified Encoder for Global Positioning System 用于全球定位系统的高效 CRC-BCH 统一编码器
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457230
Yongtaek Hwang, Jiwoo Hwang, Yuseok Lee, Hoyoung Yoo
GPS uses ECCs to see if an error occurs when the data sent from the satellite reaches the user. Each message structure uses ECCs such as Hamming Code, CRC, BCH Code, and LDPC Code. If the satellite contains all of the encoders, it has a negative impact to the area and power consumption. Therefore, in this paper, we propose a CRC-BCH unified encoder for GPS, which is efficient in terms of space and power consumption. Since both the CRC and BCH encoders use shift registers, the design was made using this part. To replace the existing encoder, the CRC-BCH encoder must have the same output. To validate this, we used individual CRC and BCH encoders and confirmed that the generated output was identical to the output of the proposed encoder. The proposed CRC-BCH unified encoder was synthesized at an operating frequency of 400 MHz using the CMOS 28nm process. The synthesis results showed that it used 16.67% less area and consumed 19.68% less power than the existing encoder. Therefore, the proposed CRC-BCH unified encoder offers advantages in terms of satellite weight and energy efficiency.
当卫星发送的数据到达用户时,GPS 使用 ECC 来检测是否发生错误。每个信息结构都使用 ECC,如 Hamming 码、CRC、BCH 码和 LDPC 码。如果卫星包含所有编码器,则会对面积和功耗产生负面影响。因此,本文提出了一种用于 GPS 的 CRC-BCH 统一编码器,它在空间和功耗方面都很有效。由于 CRC 和 BCH 编码器都使用移位寄存器,因此设计时使用了这一部分。要取代现有的编码器,CRC-BCH 编码器必须具有相同的输出。为了验证这一点,我们使用了单独的 CRC 和 BCH 编码器,并确认生成的输出与拟议编码器的输出完全相同。建议的 CRC-BCH 统一编码器是在 400 MHz 的工作频率下使用 CMOS 28nm 工艺合成的。合成结果表明,与现有编码器相比,它使用的面积减少了 16.67%,消耗的功率减少了 19.68%。因此,拟议的 CRC-BCH 统一编码器在卫星重量和能效方面具有优势。
{"title":"Efficient CRC-BCH Unified Encoder for Global Positioning System","authors":"Yongtaek Hwang, Jiwoo Hwang, Yuseok Lee, Hoyoung Yoo","doi":"10.1109/ICEIC61013.2024.10457230","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457230","url":null,"abstract":"GPS uses ECCs to see if an error occurs when the data sent from the satellite reaches the user. Each message structure uses ECCs such as Hamming Code, CRC, BCH Code, and LDPC Code. If the satellite contains all of the encoders, it has a negative impact to the area and power consumption. Therefore, in this paper, we propose a CRC-BCH unified encoder for GPS, which is efficient in terms of space and power consumption. Since both the CRC and BCH encoders use shift registers, the design was made using this part. To replace the existing encoder, the CRC-BCH encoder must have the same output. To validate this, we used individual CRC and BCH encoders and confirmed that the generated output was identical to the output of the proposed encoder. The proposed CRC-BCH unified encoder was synthesized at an operating frequency of 400 MHz using the CMOS 28nm process. The synthesis results showed that it used 16.67% less area and consumed 19.68% less power than the existing encoder. Therefore, the proposed CRC-BCH unified encoder offers advantages in terms of satellite weight and energy efficiency.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"322 5","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Study on the UWB/Encoder/IMU Sensor Fusion Position Estimation System for the Development of Driving Assistance Technology in Autonomous Driving Wheelchairs 面向自主驾驶轮椅辅助驾驶技术开发的 UWB/编码器/IMU 传感器融合位置估计系统研究
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457206
Eunsu Jang, Su-Hong Eom, D. Kim, Eunghyuk Lee
As the number of people who need electric wheelchairs increases around the world, there is a lot of demand, but there are many people who cannot use them because they are difficult to operate. Accordingly, the introduction of autonomous driving technology is being studied for wheelchairs that do not require separate manipulation. Currently, such autonomous driving is based on Map, but it is difficult to have Map in all environments. Thus, it is necessary to develop driving assistance technology in a Mapless environment. This study focuses on the position estimation system by fusion of UWB/Encoder/IMU for the development of driving assistance systems in the Mapless environment of wheelchairs.
随着全世界需要电动轮椅的人越来越多,需求量也越来越大,但也有很多人因为难以操作而无法使用。因此,人们正在研究为不需要单独操控的轮椅引入自动驾驶技术。目前,这种自动驾驶技术基于地图,但很难在所有环境中都使用地图。因此,有必要开发无地图环境下的辅助驾驶技术。本研究的重点是融合 UWB/编码器/IMU 的位置估计系统,以开发轮椅无地图环境下的驾驶辅助系统。
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引用次数: 0
Searching Optimal Floating-Point Format for Sub-8-Bit Large Language Model Inference 为低于 8 位的大型语言模型推理寻找最佳浮点格式
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457111
Youngdeok Hwang, Janghwan Lee, Jiwoong Park, Jieun Lim, Jungwook Choi
Large Language Models (LLMs) have shown remarkable success in various natural language processing tasks. However, their extensive parameter count leads to significant memory and computational demands. To tackle these challenges, there is growing interest in employing post-training quantization (PTQ) with reduced-precision floating-point (FP) operations. Yet, the optimal FP configuration remains a topic of debate. Existing studies often overlook a thorough analysis of the diverse data distributions found in LLMs and the crucial design choice, denormal. In this paper, we conduct a comprehensive examination of the various data distributions within LLMs and the significance of denormal representation, presenting a mixed-format floating-point framework. Our proposed framework allows for sub-8-bit inference with minimal performance degradation in language modeling and reasoning tasks across a broad spectrum of LLMs.
大型语言模型(LLM)在各种自然语言处理任务中取得了显著的成功。然而,其庞大的参数数量导致了巨大的内存和计算需求。为了应对这些挑战,越来越多的人开始关注使用降低精度浮点运算(FP)进行训练后量化(PTQ)。然而,最佳 FP 配置仍是一个争论不休的话题。现有的研究往往忽略了对 LLM 中各种数据分布的全面分析,以及关键的设计选择--非正态分布。在本文中,我们对 LLM 中的各种数据分布和非正态表示的重要性进行了全面研究,并提出了一个混合格式浮点框架。我们提出的框架允许在语言建模和推理任务中使用低于 8 位的推理方法,并在广泛的 LLM 中将性能降低到最低程度。
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引用次数: 0
An Architecture-Level Framework for Enabling Processing-Using-Memory Simulations in Deep Neural Networks 实现深度神经网络处理-内存仿真的架构级框架
Pub Date : 2024-01-28 DOI: 10.1109/ICEIC61013.2024.10457163
Inseong Hwang, Jihoon Jang, Hyun Kim
The emulation or layout in the study of processing-in-memory (PIM) is a highly time-consuming process. Especially, the processing-using-memory (PUM), a subset of PIM, is much more complex due to the positioning of the processing unit in the high-density data array. Because of this reason, it is important to efficiently verify PIM hardware using simulation to activate the PIM study. To this end, we modify the DRAMsim3, a memory simulator, to implement a PUM system, and propose a PIM operation compiler in the Zsim, a CPU simulator. The PIM operation compiler performs the role of tracing instructions from various precision deep neural network (DNN) workloads and generating PIM operation commands. Finally, we propose an architecture-level PUM simulation framework that can simulate the PUM system with DNN workloads based on the PIM command generated by the compiler.
内存处理(PIM)研究中的仿真或布局是一个非常耗时的过程。特别是作为 PIM 子集的内存处理(PUM),由于处理单元在高密度数据阵列中的定位,其复杂程度更高。正因为如此,利用仿真来有效验证 PIM 硬件以启动 PIM 研究就显得尤为重要。为此,我们修改了内存模拟器 DRAMsim3 以实现 PUM 系统,并在 CPU 模拟器 Zsim 中提出了 PIM 操作编译器。PIM 操作编译器的作用是追踪各种精密深度神经网络(DNN)工作负载的指令,并生成 PIM 操作命令。最后,我们提出了一个架构级 PUM 仿真框架,该框架可根据编译器生成的 PIM 命令模拟带有 DNN 工作负载的 PUM 系统。
{"title":"An Architecture-Level Framework for Enabling Processing-Using-Memory Simulations in Deep Neural Networks","authors":"Inseong Hwang, Jihoon Jang, Hyun Kim","doi":"10.1109/ICEIC61013.2024.10457163","DOIUrl":"https://doi.org/10.1109/ICEIC61013.2024.10457163","url":null,"abstract":"The emulation or layout in the study of processing-in-memory (PIM) is a highly time-consuming process. Especially, the processing-using-memory (PUM), a subset of PIM, is much more complex due to the positioning of the processing unit in the high-density data array. Because of this reason, it is important to efficiently verify PIM hardware using simulation to activate the PIM study. To this end, we modify the DRAMsim3, a memory simulator, to implement a PUM system, and propose a PIM operation compiler in the Zsim, a CPU simulator. The PIM operation compiler performs the role of tracing instructions from various precision deep neural network (DNN) workloads and generating PIM operation commands. Finally, we propose an architecture-level PUM simulation framework that can simulate the PUM system with DNN workloads based on the PIM command generated by the compiler.","PeriodicalId":518726,"journal":{"name":"2024 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"364 6","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2024-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140530459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
期刊
2024 International Conference on Electronics, Information, and Communication (ICEIC)
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