Tsinghua Science and Technology最新文献

A neural network fire detection method was developed using detection information for temperature, smoke density, and CO concentration to determine the probability of three representative fire conditions. The method overcomes the shortcomings of domestic fire alarm systems using single sensor information. Test results show that the identification error rates for fires, smoldering fires, and no fire are less than 5%, which greatly reduces leak-check rates and false alarms. This neural network fire alarm system can fuse a variety of sensor data and improve the ability of systems to adapt in the environment and accurately predict fires, which has great significance for life and property safety.

As a promising approach to improve network reliability, proactive failure recovery (PFR) re-routes failure affected traffic to backup paths without waiting for the completion of IP routing convergence. However, the failure affected traffic may cause congestion if it is not carefully allocated over the backup paths according to their available capacity. A post failure traffic engineering (PostTE) scheme is proposed to balance the load in the PFR scheme. Loop-free backup paths are prepared in advance to cover all the potential single-link failures. The failure affected load is locally allocated to the backup paths through solving a linear programming (LP) problem. Most of the time, the maximum link utilization (MLU) of the network is minimized under both the failure and failure-free cases. For the tested education networks, the LP problem can be solved within milliseconds.

Directional speech enhancement of signals from microphone arrays is an effective way to improve speech recognition for cochlear implant users. The strict implant size limitation results in a short distance between microphones. The fractional delay problem due to the short distance between microphones is solved by a maximal flat (Maxflat) finite impulse response (FIR) filter, using the Maxflat error criteria at a low frequency containing most of the speech information and energy. The fractional Maxflat FIR filter approximates the ideal digital fractional filter at the magnitude response, phase response, and phase delay characteristics, and is also very low order. The results demonstrate that the Maxflat FIR filter accurately and effectively solves the fractional digital delay and is very suitable for real-time speech processing in practical cochlear implant products.

Multimodal documents combining language and graphs are wide-spread in print media as well as in electronic media. One of the most important tasks to be solved in comprehending graph-text combinations is construction of causal chains among the meaning entities provided by modalities. In this study we focus on the role of annotation position and shape of graph lines in simple line graphs on causal attributions concerning the event presented by the annotation and the processes (i.e. increases and decreases) and states (no-changes) in the domain value of the graphs presented by the process-lines and state-lines. Based on the experimental investigation of readers’ inferences under different conditions, guidelines for the design of multimodal documents including text and statistical information graphics are suggested. One suggestion is that the position and the number of verbal annotations should be selected appropriately, another is that the graph line smoothing should be done cautiously.

This paper presents a multilevel hypergraph partitioning method that balances constraints on not only the cell area but also the wire weight with a partition-based global placement algorithm that maximizes the wire density uniformity to control chemical-mechanical polishing (CMP) variations. The multilevel partitioning alternately uses two FM variants in the refinement stage to give a more uniform wire distribution. The global placement is based on a top-down recursive bisection framework. The partitioning algorithm is used in the bisectioning to impact the wire density uniformity. Tests show that, with a 10% constraint, the partitioning produces solutions with more balanced edge weights that are 837% better than from hMetis, 1039.1% better than MLPart, and 762.9% better than FM in terms of imbalance proportion and that this global placement algorithm improves ROOSTER with a more uniform wire distribution by 3.1% on average with an increased wire length of only 3.0%.

An English speech recognition system was implemented on a chip, called speech system-on-chip (SoC). The SoC included an application specific integrated circuit with a vector accelerator to improve performance. The sub-word model based on a continuous density hidden Markov model recognition algorithm ran on a very cheap speech chip. The algorithm was a two-stage fixed-width beam-search baseline system with a variable beam-width pruning strategy and a frame-synchronous word-level pruning strategy to significantly reduce the recognition time. Tests show that this method reduces the recognition time nearly 6 fold and the memory size nearly 2 fold compared to the original system, with less than 1% accuracy degradation for a 600 word recognition task and recognition accuracy rate of about 98%.

Cayley graphs have many good properties as models of communication networks. This study analyzes the reliability of the Cayley graph based on the dihedral graph. Graph theory and analyses show that almost all Cayley graphs of the dihedral graph D_2n are optimal super-λ. The number N_i(G) of cutsets of size i,λ≤i≤λ′ is given as$N_i\left(G\right)=n\left(\begin{array}{c}(G-1)\\ i-\delta \end{array}\right).$

Divide-and-conquer methods for FPGA placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA placer.

This paper describes a low-power low-cost 24-bit Σ-Δ digital-to-analog converter (DAC) for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage Σ-Δ modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter (DCT-SC LPF) is used to reconstruct the analog signal to reduce the kT/C noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process. The cell area of the digital part is 0.056 mm² and the total area of the analog part is 0.34 mm². The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications.

This paper describes a quantum switching architecture for nearest neighbor coupling. An efficient quantum shear sorting (QSS) algorithm is used to reduce the number of time steps. For the QSS algorithm, the running complexity of the quantum switching architecture is polynomial in time with the nearest neighbor coupling and the implementation is less complex. The result shows that improved switching is extremely simple to implement using existing quantum computer candidates.