Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487713
Jiashu Chen, Lu Ye, D. Titz, F. Gianesello, R. Pilard, A. Cathelin, F. Ferrero, C. Luxey, A. Niknejad
With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].
{"title":"A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining","authors":"Jiashu Chen, Lu Ye, D. Titz, F. Gianesello, R. Pilard, A. Cathelin, F. Ferrero, C. Luxey, A. Niknejad","doi":"10.1109/ISSCC.2013.6487713","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487713","url":null,"abstract":"With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"7 1","pages":"232-233"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74358284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487638
Jun-Han Choi, Sungku Yeo, Changbyung Park, Sehoon Park, J. Lee, G. Cho
Wireless power transfer up to the 5W power level has become a recent trend for mobile phones, which can be classified into two types: inductive type and resonant type. Inductive type usually has higher efficiency but requires short distance and precise alignment between the transmitter and receiver. From the viewpoint of convenience, resonant type has much better freedom from distance and alignment under a handicap of somewhat less efficiency. Among the numerous resonant wireless power transfer (RWPT) mechanisms, the one using 6.78MHz or 13.56MHz band for fRS has been a the mainstream option [1-2]. Major sources of power loss related to efficiency degradation are the transmitter circuits, receiver circuits, and resonant tanks of both sides. The efficiency of the receiver circuit is more important since it is especially related to the thermal emission of hands-on mobile devices and has to meet a strict value because the recent mobile phones already spend most of their thermal margins on the application processor. In this paper, we suggest a new receiver circuit for RWPT with simple structure and high efficiency.
{"title":"A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiency","authors":"Jun-Han Choi, Sungku Yeo, Changbyung Park, Sehoon Park, J. Lee, G. Cho","doi":"10.1109/ISSCC.2013.6487638","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487638","url":null,"abstract":"Wireless power transfer up to the 5W power level has become a recent trend for mobile phones, which can be classified into two types: inductive type and resonant type. Inductive type usually has higher efficiency but requires short distance and precise alignment between the transmitter and receiver. From the viewpoint of convenience, resonant type has much better freedom from distance and alignment under a handicap of somewhat less efficiency. Among the numerous resonant wireless power transfer (RWPT) mechanisms, the one using 6.78MHz or 13.56MHz band for fRS has been a the mainstream option [1-2]. Major sources of power loss related to efficiency degradation are the transmitter circuits, receiver circuits, and resonant tanks of both sides. The efficiency of the receiver circuit is more important since it is especially related to the thermal emission of hands-on mobile devices and has to meet a strict value because the recent mobile phones already spend most of their thermal margins on the application processor. In this paper, we suggest a new receiver circuit for RWPT with simple structure and high efficiency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"589 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76785332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487782
Hyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee
Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into the touch-screen system. HUM, display noise, and SMPS are such noise sources. The main electrical power source produces HUM, one of the most important sources of noise, which has a 50 or 60Hz component. Display noise is emitted when an LCD or OLED is driven by the internal timing controller, which generates the driving signal in the tens of kHz range. The touch performance of On-Cell or In-Cell touch displays is seriously affected by this kind of noise, because the distance between the display pixel layer and the capacitive touchscreen panel is getting smaller. SMPS is another noise source that ranges up to 300kHz. The charger for a smart-phone, the USB port in a computer, a tri-phosphor fluorescent light bulb are all examples of sources of SMPS. There have been many attempts to remove such noise. Amplitude modulation with frequency hopping is proposed in [1]. However, when the noise environment changes, this method needs recalibration, resulting in non-constant touch response time. Another method tries to filter the noise from the display [2], but it does not remove other noise sources like HUM or SMPS.
{"title":"A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique","authors":"Hyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee","doi":"10.1109/ISSCC.2013.6487782","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487782","url":null,"abstract":"Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into the touch-screen system. HUM, display noise, and SMPS are such noise sources. The main electrical power source produces HUM, one of the most important sources of noise, which has a 50 or 60Hz component. Display noise is emitted when an LCD or OLED is driven by the internal timing controller, which generates the driving signal in the tens of kHz range. The touch performance of On-Cell or In-Cell touch displays is seriously affected by this kind of noise, because the distance between the display pixel layer and the capacitive touchscreen panel is getting smaller. SMPS is another noise source that ranges up to 300kHz. The charger for a smart-phone, the USB port in a computer, a tri-phosphor fluorescent light bulb are all examples of sources of SMPS. There have been many attempts to remove such noise. Amplitude modulation with frequency hopping is proposed in [1]. However, when the noise environment changes, this method needs recalibration, resulting in non-constant touch response time. Another method tries to filter the noise from the display [2], but it does not remove other noise sources like HUM or SMPS.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"388-389"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82420547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487762
J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski
An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.
{"title":"A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS","authors":"J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski","doi":"10.1109/ISSCC.2013.6487762","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487762","url":null,"abstract":"An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"54 1","pages":"342-343"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89399324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487642
T. Tsai, Kai Chen
Energy harvesting is an attractive technique to take advantage of renewable energy and make systems, such as wireless sensor nodes, less dependent on external power sources. A photovoltaic (PV) energy-harvesting charger can convert energy from solar panels to charge batteries or super capacitors. To manage the variation in illumination, maximum power point tracking (MPPT) is essential to lock the output power of solar panels on the maximum power points [1, 2]. For any generic solar cell, its output current is determined by the output voltage in an exponential relation. Without knowing the characteristics of the solar cell in advance, it is necessary to monitor a feedback parameter to reach its maximum power point. Current measurement is needed at the output of the boost converter [1] or in the output path of the solar cell [2]. Motivated by the topology in [2], we propose a mixed-signal integration to avoid power hungry digital signal processing. In this paper, we report a charger with an integrated MPPT controller that can provide fast tracking for wide-range illumination levels while keeping high conversion efficiency. Also, a battery management unit is implemented and integrated on the same IC.
{"title":"A 3.4mW photovoltaic energy-harvesting charger with integrated maximum power point tracking and battery management","authors":"T. Tsai, Kai Chen","doi":"10.1109/ISSCC.2013.6487642","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487642","url":null,"abstract":"Energy harvesting is an attractive technique to take advantage of renewable energy and make systems, such as wireless sensor nodes, less dependent on external power sources. A photovoltaic (PV) energy-harvesting charger can convert energy from solar panels to charge batteries or super capacitors. To manage the variation in illumination, maximum power point tracking (MPPT) is essential to lock the output power of solar panels on the maximum power points [1, 2]. For any generic solar cell, its output current is determined by the output voltage in an exponential relation. Without knowing the characteristics of the solar cell in advance, it is necessary to monitor a feedback parameter to reach its maximum power point. Current measurement is needed at the output of the boost converter [1] or in the output path of the solar cell [2]. Motivated by the topology in [2], we propose a mixed-signal integration to avoid power hungry digital signal processing. In this paper, we report a charger with an integrated MPPT controller that can provide fast tracking for wide-range illumination levels while keeping high conversion efficiency. Also, a battery management unit is implemented and integrated on the same IC.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"17 1","pages":"72-73"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88753006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487829
S. Koyama, K. Onozawa, Keisuke Tanaka, Y. Kato
We present a CMOS image sensor that enables a compact 3-dimensional (3D) vision camera system comprising a single set of the sensor and a camera lens. In order to make binocular parallax, which is essential for 3D imaging, the input pupil of the camera lens is presumed to consist of the right-eye and the left-eye domains, where the pixels exclusively receiving light beams from the right-eye domain and those from the left-eye domain, are arranged alternately. In addition, the sensor features an on-chip lenticular lens to split the incident light from the two directions and a Digital Micro Lens [1,2] to focus the split light beams onto the dedicated pixels without significant crosstalk. The fabricated 3D image sensor enables not only successful stereovision imaging in color with sufficiently high sensitivity, but also accurate calculation of distance.
{"title":"A 3D vision 2.1Mpixel image sensor for single-lens camera systems","authors":"S. Koyama, K. Onozawa, Keisuke Tanaka, Y. Kato","doi":"10.1109/ISSCC.2013.6487829","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487829","url":null,"abstract":"We present a CMOS image sensor that enables a compact 3-dimensional (3D) vision camera system comprising a single set of the sensor and a camera lens. In order to make binocular parallax, which is essential for 3D imaging, the input pupil of the camera lens is presumed to consist of the right-eye and the left-eye domains, where the pixels exclusively receiving light beams from the right-eye domain and those from the left-eye domain, are arranged alternately. In addition, the sensor features an on-chip lenticular lens to split the incident light from the two directions and a Digital Micro Lens [1,2] to focus the split light beams onto the dedicated pixels without significant crosstalk. The fabricated 3D image sensor enables not only successful stereovision imaging in color with sufficiently high sensitivity, but also accurate calculation of distance.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"20 1","pages":"492-493"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90100176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487756
Lu Ye, Jiashu Chen, Lingkai Kong, P. Cathelin, E. Alon, A. Niknejad
In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.
{"title":"A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS","authors":"Lu Ye, Jiashu Chen, Lingkai Kong, P. Cathelin, E. Alon, A. Niknejad","doi":"10.1109/ISSCC.2013.6487756","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487756","url":null,"abstract":"In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"35 1","pages":"330-331"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78271526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487769
Zhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu
There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of -98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].
{"title":"A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners","authors":"Zhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu","doi":"10.1109/ISSCC.2013.6487769","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487769","url":null,"abstract":"There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of -98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"12 1","pages":"358-359"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90601705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487660
M. Shulaker, J. V. Rethy, G. Hills, Hong-Yu Chen, G. Gielen, H. Wong, S. Mitra
This paper presents a complete sensor interface implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by using the imperfection-immune paradigm [4], which successfully overcomes major obstacles for CNFET-based circuits: mis-positioned and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200 CNTs depending on transistor sizing, are used to build the circuit. In contrast, earlier demonstrations of CNFET-based circuits included only small stand-alone components such as an adder sum, latch, percolation transport-based decoder, and ring oscillator on a single CNT [4]. Because it is easier to implement digital circuits using immature technologies compared to analog circuits, highly-digital sensor interfaces such as the PLL-based design in [5] are ideal implementations when using a new technology. The implemented capacitive sensor interface is based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architecture, which processes the sensor information entirely in the frequency domain (Fig. 6.8.1). Its funcationality is described in detail in [5].
{"title":"Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs","authors":"M. Shulaker, J. V. Rethy, G. Hills, Hong-Yu Chen, G. Gielen, H. Wong, S. Mitra","doi":"10.1109/ISSCC.2013.6487660","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487660","url":null,"abstract":"This paper presents a complete sensor interface implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by using the imperfection-immune paradigm [4], which successfully overcomes major obstacles for CNFET-based circuits: mis-positioned and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200 CNTs depending on transistor sizing, are used to build the circuit. In contrast, earlier demonstrations of CNFET-based circuits included only small stand-alone components such as an adder sum, latch, percolation transport-based decoder, and ring oscillator on a single CNT [4]. Because it is easier to implement digital circuits using immature technologies compared to analog circuits, highly-digital sensor interfaces such as the PLL-based design in [5] are ideal implementations when using a new technology. The implemented capacitive sensor interface is based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architecture, which processes the sensor information entirely in the frequency domain (Fig. 6.8.1). Its funcationality is described in detail in [5].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"5 1","pages":"112-113"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90144471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487767
Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim
Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.
{"title":"A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS","authors":"Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim","doi":"10.1109/ISSCC.2013.6487767","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487767","url":null,"abstract":"Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"108 1","pages":"354-355"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79405636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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