Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487694
Dong-Woo Jee, D. Sylvester, D. Blaauw, J. Sim
Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential block, is one of the most actively researched blocks. It is required to distribute various frequency ranges for energy-optimal operation, e.g., Hz for internal timer [1], kHz for global clock [2], and MHz for fast data transmission or intensive signal processing [3]. However, free-running oscillators are seriously affected by process variations and should be readjusted by post-fabrication trimming. Though a crystal gives a stable frequency, the use of multiple crystals is generally not allowed by limited form-factor and increased cost. Instead, frequency multiplication from one clean reference is more effective way for higher frequency generation. Considering high-frequency clock is only intermittently used in sensor applications, the clock multiplier should provide a fast settling when turned on as well as low-power dissipation. This paper presents a 423nW, 3.2 MHz all-digital multiplying DLL (MDLL) with a digitally controlled leakage-based oscillator (DCLO) and a fast frequency relocking scheme adaptive to the amount of frequency drift during sleep state, which is required for intermittent operation of sensor node platforms.
{"title":"A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms","authors":"Dong-Woo Jee, D. Sylvester, D. Blaauw, J. Sim","doi":"10.1109/ISSCC.2013.6487694","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487694","url":null,"abstract":"Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential block, is one of the most actively researched blocks. It is required to distribute various frequency ranges for energy-optimal operation, e.g., Hz for internal timer [1], kHz for global clock [2], and MHz for fast data transmission or intensive signal processing [3]. However, free-running oscillators are seriously affected by process variations and should be readjusted by post-fabrication trimming. Though a crystal gives a stable frequency, the use of multiple crystals is generally not allowed by limited form-factor and increased cost. Instead, frequency multiplication from one clean reference is more effective way for higher frequency generation. Considering high-frequency clock is only intermittently used in sensor applications, the clock multiplier should provide a fast settling when turned on as well as low-power dissipation. This paper presents a 423nW, 3.2 MHz all-digital multiplying DLL (MDLL) with a digitally controlled leakage-based oscillator (DCLO) and a fast frequency relocking scheme adaptive to the amount of frequency drift during sleep state, which is required for intermittent operation of sensor node platforms.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"55 1","pages":"188-189"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86930099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487777
Junsik Kim, Jiyong Lee, S. Park
Light-emitting diodes (LEDs) are widely used in general lightings due to their several advantages including high efficiency, high reliability, long life, and environmental friendliness. Recently, various converter-free methods for non-isolated LED drivers with multiple LED strings connected in series have been introduced, enabling both a higher efficiency and power factor (PF) as well as lower total harmonic distortion (THD) [1-3]. In multiple-string LED drivers, the efficiency and PF are enhanced as the number of LED strings increases because of a low overhead voltage. However, as the operational voltage range decreases, it is difficult to find a proper commutation time using input voltage sensing approaches due to input voltage noise and LED voltage variation [4]. Other concerns are EMI and EMC noise caused by high di/dt and dv/dt in hard commutations. When the LED current is high, negative effects of hard commutation become worse and the required di/dt control circuits are more complicated [5]. To meet EMI and EMC regulations for lightings without adding on-board EMI filters, soft commutation is essential. In order to overcome these problems, we propose a soft self-commutating method using a Source-Coupled Pair (SCP) and reference voltages. The conventional control circuits required for an appropriate commutation time and soft commutation are no longer necessary. The fabricated 6-string LED driver IC is capable of achieving high efficiency (92.2%), high PF (0.996) and low THD (8.6%) under the 22W/110V AC condition.
{"title":"A soft self-commutating method using minimum control circuitry for multiple-string LED drivers","authors":"Junsik Kim, Jiyong Lee, S. Park","doi":"10.1109/ISSCC.2013.6487777","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487777","url":null,"abstract":"Light-emitting diodes (LEDs) are widely used in general lightings due to their several advantages including high efficiency, high reliability, long life, and environmental friendliness. Recently, various converter-free methods for non-isolated LED drivers with multiple LED strings connected in series have been introduced, enabling both a higher efficiency and power factor (PF) as well as lower total harmonic distortion (THD) [1-3]. In multiple-string LED drivers, the efficiency and PF are enhanced as the number of LED strings increases because of a low overhead voltage. However, as the operational voltage range decreases, it is difficult to find a proper commutation time using input voltage sensing approaches due to input voltage noise and LED voltage variation [4]. Other concerns are EMI and EMC noise caused by high di/dt and dv/dt in hard commutations. When the LED current is high, negative effects of hard commutation become worse and the required di/dt control circuits are more complicated [5]. To meet EMI and EMC regulations for lightings without adding on-board EMI filters, soft commutation is essential. In order to overcome these problems, we propose a soft self-commutating method using a Source-Coupled Pair (SCP) and reference voltages. The conventional control circuits required for an appropriate commutation time and soft commutation are no longer necessary. The fabricated 6-string LED driver IC is capable of achieving high efficiency (92.2%), high PF (0.996) and low THD (8.6%) under the 22W/110V AC condition.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"8 1","pages":"376-377"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85725384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487692
A. Paidimarri, D. Griffith, Alice Wang, A. Chandrakasan, G. Burra
Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.
{"title":"A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability","authors":"A. Paidimarri, D. Griffith, Alice Wang, A. Chandrakasan, G. Burra","doi":"10.1109/ISSCC.2013.6487692","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487692","url":null,"abstract":"Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"42 1","pages":"184-185"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85775707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487828
O. Shcherbakova, L. Pancheri, G. Betta, N. Massari, D. Stoppa
In the last few years, both the scientific and industrial communities have shown an increasing interest in range imaging, due to its potential exploitation in various application domains such as robotics, security and surveillance, vehicle safety, gaming, and mobile applications. Among the diversity of techniques available for range detection, Time-of-Flight (ToF) offers advantages in terms of compact system realization, good performance, and low required computational power. The last works on ToF sensors, presenting demodulation sensors based on photon-mixing devices [1, 2], and time-counting sensors based on single-photon avalanche diodes [3], have shown a trend towards higher resolutions, with a consequent reduction of pixel size, higher modulation frequencies, and demodulation contrast to allow better distance precision. In this paper, we introduce a range camera concept that exploits linear-mode avalanche photodiodes (APD) as in-pixel demodulating detectors [4]. Thanks to photocurrent gain modulation, APDs can combine optical sensing and light-signal demodulation in a single device. The main advantage of the APD implementation is the possibility to operate at high frequencies, due to its very wide bandwidth.
{"title":"3D camera based on linear-mode gain-modulated avalanche photodiodes","authors":"O. Shcherbakova, L. Pancheri, G. Betta, N. Massari, D. Stoppa","doi":"10.1109/ISSCC.2013.6487828","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487828","url":null,"abstract":"In the last few years, both the scientific and industrial communities have shown an increasing interest in range imaging, due to its potential exploitation in various application domains such as robotics, security and surveillance, vehicle safety, gaming, and mobile applications. Among the diversity of techniques available for range detection, Time-of-Flight (ToF) offers advantages in terms of compact system realization, good performance, and low required computational power. The last works on ToF sensors, presenting demodulation sensors based on photon-mixing devices [1, 2], and time-counting sensors based on single-photon avalanche diodes [3], have shown a trend towards higher resolutions, with a consequent reduction of pixel size, higher modulation frequencies, and demodulation contrast to allow better distance precision. In this paper, we introduce a range camera concept that exploits linear-mode avalanche photodiodes (APD) as in-pixel demodulating detectors [4]. Thanks to photocurrent gain modulation, APDs can combine optical sensing and light-signal demodulation in a single device. The main advantage of the APD implementation is the possibility to operate at high frequencies, due to its very wide bandwidth.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"490-491"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82110070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487782
Hyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee
Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into the touch-screen system. HUM, display noise, and SMPS are such noise sources. The main electrical power source produces HUM, one of the most important sources of noise, which has a 50 or 60Hz component. Display noise is emitted when an LCD or OLED is driven by the internal timing controller, which generates the driving signal in the tens of kHz range. The touch performance of On-Cell or In-Cell touch displays is seriously affected by this kind of noise, because the distance between the display pixel layer and the capacitive touchscreen panel is getting smaller. SMPS is another noise source that ranges up to 300kHz. The charger for a smart-phone, the USB port in a computer, a tri-phosphor fluorescent light bulb are all examples of sources of SMPS. There have been many attempts to remove such noise. Amplitude modulation with frequency hopping is proposed in [1]. However, when the noise environment changes, this method needs recalibration, resulting in non-constant touch response time. Another method tries to filter the noise from the display [2], but it does not remove other noise sources like HUM or SMPS.
{"title":"A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique","authors":"Hyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee","doi":"10.1109/ISSCC.2013.6487782","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487782","url":null,"abstract":"Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into the touch-screen system. HUM, display noise, and SMPS are such noise sources. The main electrical power source produces HUM, one of the most important sources of noise, which has a 50 or 60Hz component. Display noise is emitted when an LCD or OLED is driven by the internal timing controller, which generates the driving signal in the tens of kHz range. The touch performance of On-Cell or In-Cell touch displays is seriously affected by this kind of noise, because the distance between the display pixel layer and the capacitive touchscreen panel is getting smaller. SMPS is another noise source that ranges up to 300kHz. The charger for a smart-phone, the USB port in a computer, a tri-phosphor fluorescent light bulb are all examples of sources of SMPS. There have been many attempts to remove such noise. Amplitude modulation with frequency hopping is proposed in [1]. However, when the noise environment changes, this method needs recalibration, resulting in non-constant touch response time. Another method tries to filter the noise from the display [2], but it does not remove other noise sources like HUM or SMPS.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"388-389"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82420547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487667
Xiaotie Wu, B. Dama, Prakash Gothoskar, P. Metz, K. Shastri, S. Sunder, Jan Van der Spiegel, Yifan Wang, M. Webster, Will Wilson
The need for more bandwidth driven by streaming video and other data intensive applications has been steadily pushing the optical link speed to the 40G/100G domain. Compared to VCSEL and ring resonator, Mach-Zehnder Interferometer (MZI) is the best solution for long distance (>500m), high data rate (>28Gb/s) optical communications [1-3]. However, high power consumption, low link density and high cost seriously prevent traditional MZI from being the next generation of optical link technology. To fundamentally reduce the cost of MZI, it is highly desirable to make the process CMOS compatible with high efficiency, thus the modulation voltage, size, and power can be reduced to a level where advanced sub-1V CMOS circuits can be used as the driver. This paper presents two CMOS-MZI-based optical transmitters, NRZ or configurable PAM-N (N = 4,16), featuring 20Gb/s data rate and sub-pJ/bit modulation energy (PAM-4) using a 1V supply. The fully CMOS compatible photonic device is highly cost-effective in terms of integration, manufacturability and scalability.
{"title":"A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS","authors":"Xiaotie Wu, B. Dama, Prakash Gothoskar, P. Metz, K. Shastri, S. Sunder, Jan Van der Spiegel, Yifan Wang, M. Webster, Will Wilson","doi":"10.1109/ISSCC.2013.6487667","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487667","url":null,"abstract":"The need for more bandwidth driven by streaming video and other data intensive applications has been steadily pushing the optical link speed to the 40G/100G domain. Compared to VCSEL and ring resonator, Mach-Zehnder Interferometer (MZI) is the best solution for long distance (>500m), high data rate (>28Gb/s) optical communications [1-3]. However, high power consumption, low link density and high cost seriously prevent traditional MZI from being the next generation of optical link technology. To fundamentally reduce the cost of MZI, it is highly desirable to make the process CMOS compatible with high efficiency, thus the modulation voltage, size, and power can be reduced to a level where advanced sub-1V CMOS circuits can be used as the driver. This paper presents two CMOS-MZI-based optical transmitters, NRZ or configurable PAM-N (N = 4,16), featuring 20Gb/s data rate and sub-pJ/bit modulation energy (PAM-4) using a 1V supply. The fully CMOS compatible photonic device is highly cost-effective in terms of integration, manufacturability and scalability.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"32 1","pages":"128-129"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90895980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487756
Lu Ye, Jiashu Chen, Lingkai Kong, P. Cathelin, E. Alon, A. Niknejad
In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.
{"title":"A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS","authors":"Lu Ye, Jiashu Chen, Lingkai Kong, P. Cathelin, E. Alon, A. Niknejad","doi":"10.1109/ISSCC.2013.6487756","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487756","url":null,"abstract":"In order to support higher throughputs, the power consumption of 2-to-5GHz Wi-Fi transmitters (TXs) has been continuously rising, and has hence become increasingly problematic for mobile devices. To extend battery life, the TX must be efficient not only at peak power but also at backoff, due to the use of high Peak-to-Average-Power-Ratio (PAPR) OFDM modulation. Many recent works have aimed to enhance PA efficiency at back-off powers [1-4], but relatively few have integrated these techniques into a complete TX system. For example, previous designs employing digital polar or outphasing architectures often realized phase modulation with off-chip instruments. Similarly, while good close-in spectral performance has been shown, far-out spectral images remain problematic for TXs where the PA itself is digitally modulated. Moreover, previous works often do not include overhead from components such as extra DC-DC converters (for multiple PA supplies) or did not implement on-chip matching networks (MN) and/or output baluns, all of which directly affect the overall efficiency of integrated CMOS PAs.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"35 1","pages":"330-331"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78271526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487797
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signal-to-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 87% logic utilization that is significantly higher than a fully parallel binary LDPC decoder [7]. To achieve high energy efficiency, each processing node detects its own convergence and applies dynamic clock gating, and the decoder terminates when all nodes are clock gated. The dynamic clock gating and termination reduce the energy consumption by 62% for energy efficiency of 3.37nJ/b, or 277pJ/b/iteration, at a 1V supply.
{"title":"A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating","authors":"Youn Sung Park, Yaoyu Tao, Zhengya Zhang","doi":"10.1109/ISSCC.2013.6487797","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487797","url":null,"abstract":"The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signal-to-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 87% logic utilization that is significantly higher than a fully parallel binary LDPC decoder [7]. To achieve high energy efficiency, each processing node detects its own convergence and applies dynamic clock gating, and the decoder terminates when all nodes are clock gated. The dynamic clock gating and termination reduce the energy consumption by 62% for energy efficiency of 3.37nJ/b, or 277pJ/b/iteration, at a 1V supply.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"16 1","pages":"422-423"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78382153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487638
Jun-Han Choi, Sungku Yeo, Changbyung Park, Sehoon Park, J. Lee, G. Cho
Wireless power transfer up to the 5W power level has become a recent trend for mobile phones, which can be classified into two types: inductive type and resonant type. Inductive type usually has higher efficiency but requires short distance and precise alignment between the transmitter and receiver. From the viewpoint of convenience, resonant type has much better freedom from distance and alignment under a handicap of somewhat less efficiency. Among the numerous resonant wireless power transfer (RWPT) mechanisms, the one using 6.78MHz or 13.56MHz band for fRS has been a the mainstream option [1-2]. Major sources of power loss related to efficiency degradation are the transmitter circuits, receiver circuits, and resonant tanks of both sides. The efficiency of the receiver circuit is more important since it is especially related to the thermal emission of hands-on mobile devices and has to meet a strict value because the recent mobile phones already spend most of their thermal margins on the application processor. In this paper, we suggest a new receiver circuit for RWPT with simple structure and high efficiency.
{"title":"A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiency","authors":"Jun-Han Choi, Sungku Yeo, Changbyung Park, Sehoon Park, J. Lee, G. Cho","doi":"10.1109/ISSCC.2013.6487638","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487638","url":null,"abstract":"Wireless power transfer up to the 5W power level has become a recent trend for mobile phones, which can be classified into two types: inductive type and resonant type. Inductive type usually has higher efficiency but requires short distance and precise alignment between the transmitter and receiver. From the viewpoint of convenience, resonant type has much better freedom from distance and alignment under a handicap of somewhat less efficiency. Among the numerous resonant wireless power transfer (RWPT) mechanisms, the one using 6.78MHz or 13.56MHz band for fRS has been a the mainstream option [1-2]. Major sources of power loss related to efficiency degradation are the transmitter circuits, receiver circuits, and resonant tanks of both sides. The efficiency of the receiver circuit is more important since it is especially related to the thermal emission of hands-on mobile devices and has to meet a strict value because the recent mobile phones already spend most of their thermal margins on the application processor. In this paper, we suggest a new receiver circuit for RWPT with simple structure and high efficiency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"589 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76785332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487795
T. Kao, Che-Fu Liang, H. Chiu, Michael Ashburn
Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI) is used to suppress the quantization noise due to its simplicity, but at a cost of gain error and non-linearity. These sub-phase non-idealities result in large fractional spurs [2-5]. Techniques for reducing these spurs include using a PI mismatch and spur-cancellation scheme [2], digital correlation and cancellation [3], use of a successive requantizer with switched loop filter and offset charge-pump [4], and foreground calibration [5]. This paper presents a ring-oscillator based 2MHz bandwidth fractional-N PLL that uses a spectrally shaped segmented-feedback approach to alleviate fractional spurs induced by the PI non-idealities. This approach results in a compact design and, in contrast to previous work, achieves a 26dB spur reduction without need of correlation, cancellation, or calibration methods.
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