Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487772
Muhammad Hassan, P. Asbeck, L. Larson
Envelope Tracking (ET) is an efficiency enhancement technique where the power supply of a linear RF power amplifier (PA) follows the envelope of the RF signal. It is specifically effective for the high peak-to-average power ratio (PAPR) signals of modern communication systems. But due to envelope bandwidth expansion and watt-level power requirements, the design of wide bandwidth and high efficiency power supply modulators remains one of the most challenging aspects of ET systems.
{"title":"A CMOS dual-switching power-supply modulator with 8% efficiency improvement for 20MHz LTE Envelope Tracking RF power amplifiers","authors":"Muhammad Hassan, P. Asbeck, L. Larson","doi":"10.1109/ISSCC.2013.6487772","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487772","url":null,"abstract":"Envelope Tracking (ET) is an efficiency enhancement technique where the power supply of a linear RF power amplifier (PA) follows the envelope of the RF signal. It is specifically effective for the high peak-to-average power ratio (PAPR) signals of modern communication systems. But due to envelope bandwidth expansion and watt-level power requirements, the design of wide bandwidth and high efficiency power supply modulators remains one of the most challenging aspects of ET systems.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72645708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487744
Constantine Sideris, A. Hajimiri
There is high demand for at-home and point-of-care medical diagnostic tools as a step toward fast, low-cost, personal medicine. Integrated biosensors based on magnetic labeling schemes offer higher sensitivity and lower cost due to the elimination of the optics and have emerged as a viable alternative to assays that use fluorescence for biomolecular detection. For instance, the frequency-shift sensor of [1] demonstrates a high-sensitivity example of a cost-effective magnetic particle biosensor in CMOS with no need for external magnets. Despite their cost and sensitivity advantages, magnetic biosensors reported so far suffer from a lack of multi-probe diagnostics similar to fluorescent-based approaches that use multiple colors for simultaneous single-site multiple target differentiation. This is primarily because current approaches measure changes in the magnetic susceptibility, χ, either at low frequencies [2,3] or at a fixed RF frequency [1]. Consequently, these approaches do not provide a clear path for differentiating between a large number of small magnetic particles vs. a smaller number of larger size particles with similar magnetic content.
{"title":"An integrated magnetic spectrometer for multiplexed biosensing","authors":"Constantine Sideris, A. Hajimiri","doi":"10.1109/ISSCC.2013.6487744","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487744","url":null,"abstract":"There is high demand for at-home and point-of-care medical diagnostic tools as a step toward fast, low-cost, personal medicine. Integrated biosensors based on magnetic labeling schemes offer higher sensitivity and lower cost due to the elimination of the optics and have emerged as a viable alternative to assays that use fluorescence for biomolecular detection. For instance, the frequency-shift sensor of [1] demonstrates a high-sensitivity example of a cost-effective magnetic particle biosensor in CMOS with no need for external magnets. Despite their cost and sensitivity advantages, magnetic biosensors reported so far suffer from a lack of multi-probe diagnostics similar to fluorescent-based approaches that use multiple colors for simultaneous single-site multiple target differentiation. This is primarily because current approaches measure changes in the magnetic susceptibility, χ, either at low frequencies [2,3] or at a fixed RF frequency [1]. Consequently, these approaches do not provide a clear path for differentiating between a large number of small magnetic particles vs. a smaller number of larger size particles with similar magnetic content.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84422557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487808
Yao-Hong Liu, Xiongchuan Huang, M. Vidojkovic, A. Ba, P. Harpe, G. Dolmans, H. D. Groot
This paper presents a multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) and IEEE802.15.6 (Medical Body-Area Networks, MBAN). A proprietary 2Mb/s mode is also implemented to support data-streaming applications like hearing aids. Current short-range radios for Zigbee and BT-LE typically consume more than 20mW DC power, which is rather high for autonomous systems with limited battery energy. The dual-mode MBAN/BT-LE transceiver achieves a power consumption of 6.5mW for the RX and 5.9mW for the TX by employing a sliding-IF RX and a polar TX architecture. However, it suffers from limited RX image rejection and needs a PA operating at a higher supply voltage. In this paper, an energy-efficient radio architecture with a suitable LO frequency plan is selected, and several efficiency-enhancement techniques for the critical RF circuits (e.g., a push-pull mixer and a digitally-assisted PA) are utilized. As a result, the presented transceiver dissipates only 3.8mW (RX) and 4.6mW (TX) DC power from a 1.2V supply, while exceeding all of the PHY requirements of above 3 standards.
{"title":"A 1.9nJ/b 2.4GHz multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networks","authors":"Yao-Hong Liu, Xiongchuan Huang, M. Vidojkovic, A. Ba, P. Harpe, G. Dolmans, H. D. Groot","doi":"10.1109/ISSCC.2013.6487808","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487808","url":null,"abstract":"This paper presents a multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) and IEEE802.15.6 (Medical Body-Area Networks, MBAN). A proprietary 2Mb/s mode is also implemented to support data-streaming applications like hearing aids. Current short-range radios for Zigbee and BT-LE typically consume more than 20mW DC power, which is rather high for autonomous systems with limited battery energy. The dual-mode MBAN/BT-LE transceiver achieves a power consumption of 6.5mW for the RX and 5.9mW for the TX by employing a sliding-IF RX and a polar TX architecture. However, it suffers from limited RX image rejection and needs a PA operating at a higher supply voltage. In this paper, an energy-efficient radio architecture with a suitable LO frequency plan is selected, and several efficiency-enhancement techniques for the critical RF circuits (e.g., a push-pull mixer and a digitally-assisted PA) are utilized. As a result, the presented transceiver dissipates only 3.8mW (RX) and 4.6mW (TX) DC power from a 1.2V supply, while exceeding all of the PHY requirements of above 3 standards.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85194515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487600
A. Jerng, Y. Palaskas, E. Klumperink, D. Belot, Songcheol Hong, B. Floyd
Radio-frequency performance is limited by fundamental constraints in dynamic range, as CMOS scaling continues to push supply voltages lower. The receiver needs to reject large in-band and out-of-band blockers while detecting small desired signals. The transmitter needs to maintain high efficiency and low distortion, while processing signals with wider bandwidths and higher peak-to-average ratios to support high data rates. Recent developments in RF transceiver design utilize techniques that cancel noise and distortion in receiver and transmitter signal paths. Digital circuits and calibration are increasingly being used to aid radio performance and allow area reduction. This Forum will present advanced circuit design techniques that demonstrate the current state-of-the-art. System specifications will be discussed to provide context for the required circuit enhancements. The first three talks will focus on noise and distortion cancellation techniques used in receivers. The next three talks will focus on transmitter design including both digital and analog linearization techniques. Finally, the last talk will introduce in-device co-existence issues and solutions for wireless systems that require multiple radios operating concurrently. This Forum is aimed at circuit designers and engineers active in radio-transceiver and wireless-system design.
{"title":"F1: Advanced RF transceiver design techniques","authors":"A. Jerng, Y. Palaskas, E. Klumperink, D. Belot, Songcheol Hong, B. Floyd","doi":"10.1109/ISSCC.2013.6487600","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487600","url":null,"abstract":"Radio-frequency performance is limited by fundamental constraints in dynamic range, as CMOS scaling continues to push supply voltages lower. The receiver needs to reject large in-band and out-of-band blockers while detecting small desired signals. The transmitter needs to maintain high efficiency and low distortion, while processing signals with wider bandwidths and higher peak-to-average ratios to support high data rates. Recent developments in RF transceiver design utilize techniques that cancel noise and distortion in receiver and transmitter signal paths. Digital circuits and calibration are increasingly being used to aid radio performance and allow area reduction. This Forum will present advanced circuit design techniques that demonstrate the current state-of-the-art. System specifications will be discussed to provide context for the required circuit enhancements. The first three talks will focus on noise and distortion cancellation techniques used in receivers. The next three talks will focus on transmitter design including both digital and analog linearization techniques. Finally, the last talk will introduce in-device co-existence issues and solutions for wireless systems that require multiple radios operating concurrently. This Forum is aimed at circuit designers and engineers active in radio-transceiver and wireless-system design.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85230491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487725
Yasuhiro Take, N. Miura, H. Ishikuro, T. Kuroda
Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.
{"title":"3D clock distribution using vertically/horizontally-coupled resonators","authors":"Yasuhiro Take, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ISSCC.2013.6487725","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487725","url":null,"abstract":"Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80824950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487734
R. McLachlan, A. Gillespie, M. Coln, Douglas Chisholm, Denise T. Lee
DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DAC's code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature. However, this preferred architecture for noise and temperature drift suffers from several sources of INL including: resistor mismatch, voltage losses across CMOS switches, and the nonlinearity of each resistor.
{"title":"A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability","authors":"R. McLachlan, A. Gillespie, M. Coln, Douglas Chisholm, Denise T. Lee","doi":"10.1109/ISSCC.2013.6487734","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487734","url":null,"abstract":"DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DAC's code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature. However, this preferred architecture for noise and temperature drift suffers from several sources of INL including: resistor mismatch, voltage losses across CMOS switches, and the nonlinearity of each resistor.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89697664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487787
Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, R. Montoye, Leland Chang, J. Tierno, D. Friedman
Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.
{"title":"A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI","authors":"Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, R. Montoye, Leland Chang, J. Tierno, D. Friedman","doi":"10.1109/ISSCC.2013.6487787","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487787","url":null,"abstract":"Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89908105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487680
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, T. Shyu, Chien-Yung Chou, S. Luo, Jiun-In Guo, Tien-Fu Chen, G. Chuang, Yuan-Hua Chu, L. Cheng, Hong-Men Su, C. Jou, M. Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).
{"title":"A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS","authors":"Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, T. Shyu, Chien-Yung Chou, S. Luo, Jiun-In Guo, Tien-Fu Chen, G. Chuang, Yuan-Hua Chu, L. Cheng, Hong-Men Su, C. Jou, M. Ieong, Cheng-Wen Wu, Jinn-Shyan Wang","doi":"10.1109/ISSCC.2013.6487680","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487680","url":null,"abstract":"This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86799220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487801
M. Konijnenburg, Yeon-Gon Cho, M. Ashouei, T. Gemmeke, Changmoo Kim, J. Hulzink, J. Stuyt, Mookyung Jung, J. Huisken, Soojung Ryu, Jungwook Kim, H. D. Groot
Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2-4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by today's on-node processors.
{"title":"Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS","authors":"M. Konijnenburg, Yeon-Gon Cho, M. Ashouei, T. Gemmeke, Changmoo Kim, J. Hulzink, J. Stuyt, Mookyung Jung, J. Huisken, Soojung Ryu, Jungwook Kim, H. D. Groot","doi":"10.1109/ISSCC.2013.6487801","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487801","url":null,"abstract":"Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2-4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by today's on-node processors.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87380632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487654
Muhammad Awais Bin Altaf, J. Tillak, Y. Kifle, Jerald Yoo
To mitigate seizure-affected patients, SoCs [1-3] have been developed 1) to detect electrical onset of seizure seconds before the clinical onset, and 2) to combine the SoC with neurostimulation. In particular, having detection delay of <;2s (for real-time suppression) while maintaining high detection rate is challenging [4]. However, [2] had a long latency (13.5s) and [3] suffered from a low detection rate (84.4%) with a high false alarm (max. 14.7%) due to an intermittent limit of the Linear Support Vector Machine (LSVM). In this paper, we present a Non-Linear SVM (NLSVM)-based seizure detection SoC which ensures a >95% detection accuracy, <;1% false alarm and <;2s latency.
{"title":"A 1.83µJ/classification nonlinear support-vector-machine-based patient-specific seizure classification SoC","authors":"Muhammad Awais Bin Altaf, J. Tillak, Y. Kifle, Jerald Yoo","doi":"10.1109/ISSCC.2013.6487654","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487654","url":null,"abstract":"To mitigate seizure-affected patients, SoCs [1-3] have been developed 1) to detect electrical onset of seizure seconds before the clinical onset, and 2) to combine the SoC with neurostimulation. In particular, having detection delay of <;2s (for real-time suppression) while maintaining high detection rate is challenging [4]. However, [2] had a long latency (13.5s) and [3] suffered from a low detection rate (84.4%) with a high false alarm (max. 14.7%) due to an intermittent limit of the Linear Support Vector Machine (LSVM). In this paper, we present a Non-Linear SVM (NLSVM)-based seizure detection SoC which ensures a >95% detection accuracy, <;1% false alarm and <;2s latency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78969022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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