Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487763
Luca Fanori, P. Andreani
Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.
{"title":"A 2.5-to-3.3GHz CMOS Class-D VCO","authors":"Luca Fanori, P. Andreani","doi":"10.1109/ISSCC.2013.6487763","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487763","url":null,"abstract":"Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"58 6 1","pages":"346-347"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77569881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487767
Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim
Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.
{"title":"A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS","authors":"Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim","doi":"10.1109/ISSCC.2013.6487767","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487767","url":null,"abstract":"Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"108 1","pages":"354-355"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79405636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487673
Wei Tai, L. Carley, D. Ricketts
In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an output power of 0.7W with a power-added efficiency (PAE) of 10% at 42GHz and a -3dB bandwidth of 9GHz. This is 2.6 times more output power than a recently reported millimeter-Wave (mm-Wave) silicon-based PA [1]. The circuit is a fully integrated mm-Wave PA achieving a leading output power approaching 1 Watt in a silicon process.
{"title":"A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOS","authors":"Wei Tai, L. Carley, D. Ricketts","doi":"10.1109/ISSCC.2013.6487673","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487673","url":null,"abstract":"In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an output power of 0.7W with a power-added efficiency (PAE) of 10% at 42GHz and a -3dB bandwidth of 9GHz. This is 2.6 times more output power than a recently reported millimeter-Wave (mm-Wave) silicon-based PA [1]. The circuit is a fully integrated mm-Wave PA achieving a leading output power approaching 1 Watt in a silicon process.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"109 1","pages":"142-143"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77802625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487601
Leland Chang, S. Morton, Ken Chang, Jin-Man Han, P. Malcovati, V. Stojanović
Across the spectrum of microelectronics applications, power management is critical to the enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.
{"title":"F2: VLSI power-management techniques: Principles and applications","authors":"Leland Chang, S. Morton, Ken Chang, Jin-Man Han, P. Malcovati, V. Stojanović","doi":"10.1109/ISSCC.2013.6487601","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487601","url":null,"abstract":"Across the spectrum of microelectronics applications, power management is critical to the enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"26 1","pages":"502-503"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74286036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487713
Jiashu Chen, Lu Ye, D. Titz, F. Gianesello, R. Pilard, A. Cathelin, F. Ferrero, C. Luxey, A. Niknejad
With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].
{"title":"A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining","authors":"Jiashu Chen, Lu Ye, D. Titz, F. Gianesello, R. Pilard, A. Cathelin, F. Ferrero, C. Luxey, A. Niknejad","doi":"10.1109/ISSCC.2013.6487713","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487713","url":null,"abstract":"With fast-growing demand for high-speed mobile communications and highly saturated spectral usage below 10GHz, mm-Wave frequency bands are emerging as the key playground for future high-data-rate wireless standards. Recent years have witnessed vast technology development on V-band (60GHz) Wireless Personal Area Networks (WPAN) and E-band (80GHz) point-to-point cellular backhauls. However, existing integrated CMOS mm-Wave solutions have relatively poor energy efficiency, especially for the transmitter (TX). This is mainly due to the use of traditional Class-A Power Amplifiers (PAs) that provide good linearity but suffer from low efficiency. In addition, the efficiency of Class-A PAs drop dramatically at power back-offs, making these transmitters even less efficient when conveying non-constant envelope signals. State-of-the-art mm-Wave Class-A PAs show less than 5% efficiency at 6dB back-off [1,2].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"7 1","pages":"232-233"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74358284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487829
S. Koyama, K. Onozawa, Keisuke Tanaka, Y. Kato
We present a CMOS image sensor that enables a compact 3-dimensional (3D) vision camera system comprising a single set of the sensor and a camera lens. In order to make binocular parallax, which is essential for 3D imaging, the input pupil of the camera lens is presumed to consist of the right-eye and the left-eye domains, where the pixels exclusively receiving light beams from the right-eye domain and those from the left-eye domain, are arranged alternately. In addition, the sensor features an on-chip lenticular lens to split the incident light from the two directions and a Digital Micro Lens [1,2] to focus the split light beams onto the dedicated pixels without significant crosstalk. The fabricated 3D image sensor enables not only successful stereovision imaging in color with sufficiently high sensitivity, but also accurate calculation of distance.
{"title":"A 3D vision 2.1Mpixel image sensor for single-lens camera systems","authors":"S. Koyama, K. Onozawa, Keisuke Tanaka, Y. Kato","doi":"10.1109/ISSCC.2013.6487829","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487829","url":null,"abstract":"We present a CMOS image sensor that enables a compact 3-dimensional (3D) vision camera system comprising a single set of the sensor and a camera lens. In order to make binocular parallax, which is essential for 3D imaging, the input pupil of the camera lens is presumed to consist of the right-eye and the left-eye domains, where the pixels exclusively receiving light beams from the right-eye domain and those from the left-eye domain, are arranged alternately. In addition, the sensor features an on-chip lenticular lens to split the incident light from the two directions and a Digital Micro Lens [1,2] to focus the split light beams onto the dedicated pixels without significant crosstalk. The fabricated 3D image sensor enables not only successful stereovision imaging in color with sufficiently high sensitivity, but also accurate calculation of distance.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"20 1","pages":"492-493"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90100176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487660
M. Shulaker, J. V. Rethy, G. Hills, Hong-Yu Chen, G. Gielen, H. Wong, S. Mitra
This paper presents a complete sensor interface implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by using the imperfection-immune paradigm [4], which successfully overcomes major obstacles for CNFET-based circuits: mis-positioned and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200 CNTs depending on transistor sizing, are used to build the circuit. In contrast, earlier demonstrations of CNFET-based circuits included only small stand-alone components such as an adder sum, latch, percolation transport-based decoder, and ring oscillator on a single CNT [4]. Because it is easier to implement digital circuits using immature technologies compared to analog circuits, highly-digital sensor interfaces such as the PLL-based design in [5] are ideal implementations when using a new technology. The implemented capacitive sensor interface is based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architecture, which processes the sensor information entirely in the frequency domain (Fig. 6.8.1). Its funcationality is described in detail in [5].
{"title":"Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs","authors":"M. Shulaker, J. V. Rethy, G. Hills, Hong-Yu Chen, G. Gielen, H. Wong, S. Mitra","doi":"10.1109/ISSCC.2013.6487660","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487660","url":null,"abstract":"This paper presents a complete sensor interface implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by using the imperfection-immune paradigm [4], which successfully overcomes major obstacles for CNFET-based circuits: mis-positioned and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200 CNTs depending on transistor sizing, are used to build the circuit. In contrast, earlier demonstrations of CNFET-based circuits included only small stand-alone components such as an adder sum, latch, percolation transport-based decoder, and ring oscillator on a single CNT [4]. Because it is easier to implement digital circuits using immature technologies compared to analog circuits, highly-digital sensor interfaces such as the PLL-based design in [5] are ideal implementations when using a new technology. The implemented capacitive sensor interface is based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architecture, which processes the sensor information entirely in the frequency domain (Fig. 6.8.1). Its funcationality is described in detail in [5].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"5 1","pages":"112-113"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90144471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487710
Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Y. Chih, T. Ong, T. Chang, S. Natarajan, L. Tran
Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.
{"title":"Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology","authors":"Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Y. Chih, T. Ong, T. Chang, S. Natarajan, L. Tran","doi":"10.1109/ISSCC.2013.6487710","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487710","url":null,"abstract":"Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"19 1","pages":"224-225"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84496976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487724
Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu
Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.
{"title":"A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time","authors":"Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu","doi":"10.1109/ISSCC.2013.6487724","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487724","url":null,"abstract":"Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"144 1","pages":"256-257"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73511993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487791
M. Kossel, T. Toifl, P. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Andersen, T. Morf
Memory links use variable-impedance drivers, feed-forward equalization (FFE) [1], on-die termination (ODT) and slew-rate control to optimize the signal integrity (SI). An asymmetric DRAM link configuration exploits the availability of a fast CMOS technology on the memory controller side to implement powerful equalization, while keeping the circuit complexity on the DRAM side relatively simple. This paper proposes the use of Tomlinson Harashima precoding (THP) [2-4] in a memory controller as replacement of the afore-mentioned SI optimization techniques. THP is a transmitter equalization technique in which post-cursor inter-symbol interference (ISI) is cancelled by means of an infinite impulse response (IIR) filter with modulo-based amplitude limitation; similar to a decision feedback equalizer (DFE) on the receive side. However, in contrast to a DFE, THP does not suffer from error propagation.
{"title":"An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS","authors":"M. Kossel, T. Toifl, P. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Andersen, T. Morf","doi":"10.1109/ISSCC.2013.6487791","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487791","url":null,"abstract":"Memory links use variable-impedance drivers, feed-forward equalization (FFE) [1], on-die termination (ODT) and slew-rate control to optimize the signal integrity (SI). An asymmetric DRAM link configuration exploits the availability of a fast CMOS technology on the memory controller side to implement powerful equalization, while keeping the circuit complexity on the DRAM side relatively simple. This paper proposes the use of Tomlinson Harashima precoding (THP) [2-4] in a memory controller as replacement of the afore-mentioned SI optimization techniques. THP is a transmitter equalization technique in which post-cursor inter-symbol interference (ISI) is cancelled by means of an infinite impulse response (IIR) filter with modulo-based amplitude limitation; similar to a decision feedback equalizer (DFE) on the receive side. However, in contrast to a DFE, THP does not suffer from error propagation.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"17 1","pages":"408-409"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90437430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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