Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487797
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signal-to-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 87% logic utilization that is significantly higher than a fully parallel binary LDPC decoder [7]. To achieve high energy efficiency, each processing node detects its own convergence and applies dynamic clock gating, and the decoder terminates when all nodes are clock gated. The dynamic clock gating and termination reduce the energy consumption by 62% for energy efficiency of 3.37nJ/b, or 277pJ/b/iteration, at a 1V supply.
{"title":"A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating","authors":"Youn Sung Park, Yaoyu Tao, Zhengya Zhang","doi":"10.1109/ISSCC.2013.6487797","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487797","url":null,"abstract":"The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signal-to-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 87% logic utilization that is significantly higher than a fully parallel binary LDPC decoder [7]. To achieve high energy efficiency, each processing node detects its own convergence and applies dynamic clock gating, and the decoder terminates when all nodes are clock gated. The dynamic clock gating and termination reduce the energy consumption by 62% for energy efficiency of 3.37nJ/b, or 277pJ/b/iteration, at a 1V supply.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"16 1","pages":"422-423"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78382153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487710
Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Y. Chih, T. Ong, T. Chang, S. Natarajan, L. Tran
Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.
{"title":"Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology","authors":"Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Y. Chih, T. Ong, T. Chang, S. Natarajan, L. Tran","doi":"10.1109/ISSCC.2013.6487710","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487710","url":null,"abstract":"Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"19 1","pages":"224-225"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84496976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487777
Junsik Kim, Jiyong Lee, S. Park
Light-emitting diodes (LEDs) are widely used in general lightings due to their several advantages including high efficiency, high reliability, long life, and environmental friendliness. Recently, various converter-free methods for non-isolated LED drivers with multiple LED strings connected in series have been introduced, enabling both a higher efficiency and power factor (PF) as well as lower total harmonic distortion (THD) [1-3]. In multiple-string LED drivers, the efficiency and PF are enhanced as the number of LED strings increases because of a low overhead voltage. However, as the operational voltage range decreases, it is difficult to find a proper commutation time using input voltage sensing approaches due to input voltage noise and LED voltage variation [4]. Other concerns are EMI and EMC noise caused by high di/dt and dv/dt in hard commutations. When the LED current is high, negative effects of hard commutation become worse and the required di/dt control circuits are more complicated [5]. To meet EMI and EMC regulations for lightings without adding on-board EMI filters, soft commutation is essential. In order to overcome these problems, we propose a soft self-commutating method using a Source-Coupled Pair (SCP) and reference voltages. The conventional control circuits required for an appropriate commutation time and soft commutation are no longer necessary. The fabricated 6-string LED driver IC is capable of achieving high efficiency (92.2%), high PF (0.996) and low THD (8.6%) under the 22W/110V AC condition.
{"title":"A soft self-commutating method using minimum control circuitry for multiple-string LED drivers","authors":"Junsik Kim, Jiyong Lee, S. Park","doi":"10.1109/ISSCC.2013.6487777","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487777","url":null,"abstract":"Light-emitting diodes (LEDs) are widely used in general lightings due to their several advantages including high efficiency, high reliability, long life, and environmental friendliness. Recently, various converter-free methods for non-isolated LED drivers with multiple LED strings connected in series have been introduced, enabling both a higher efficiency and power factor (PF) as well as lower total harmonic distortion (THD) [1-3]. In multiple-string LED drivers, the efficiency and PF are enhanced as the number of LED strings increases because of a low overhead voltage. However, as the operational voltage range decreases, it is difficult to find a proper commutation time using input voltage sensing approaches due to input voltage noise and LED voltage variation [4]. Other concerns are EMI and EMC noise caused by high di/dt and dv/dt in hard commutations. When the LED current is high, negative effects of hard commutation become worse and the required di/dt control circuits are more complicated [5]. To meet EMI and EMC regulations for lightings without adding on-board EMI filters, soft commutation is essential. In order to overcome these problems, we propose a soft self-commutating method using a Source-Coupled Pair (SCP) and reference voltages. The conventional control circuits required for an appropriate commutation time and soft commutation are no longer necessary. The fabricated 6-string LED driver IC is capable of achieving high efficiency (92.2%), high PF (0.996) and low THD (8.6%) under the 22W/110V AC condition.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"8 1","pages":"376-377"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85725384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487692
A. Paidimarri, D. Griffith, Alice Wang, A. Chandrakasan, G. Burra
Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.
{"title":"A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability","authors":"A. Paidimarri, D. Griffith, Alice Wang, A. Chandrakasan, G. Burra","doi":"10.1109/ISSCC.2013.6487692","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487692","url":null,"abstract":"Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"42 1","pages":"184-185"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85775707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487694
Dong-Woo Jee, D. Sylvester, D. Blaauw, J. Sim
Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential block, is one of the most actively researched blocks. It is required to distribute various frequency ranges for energy-optimal operation, e.g., Hz for internal timer [1], kHz for global clock [2], and MHz for fast data transmission or intensive signal processing [3]. However, free-running oscillators are seriously affected by process variations and should be readjusted by post-fabrication trimming. Though a crystal gives a stable frequency, the use of multiple crystals is generally not allowed by limited form-factor and increased cost. Instead, frequency multiplication from one clean reference is more effective way for higher frequency generation. Considering high-frequency clock is only intermittently used in sensor applications, the clock multiplier should provide a fast settling when turned on as well as low-power dissipation. This paper presents a 423nW, 3.2 MHz all-digital multiplying DLL (MDLL) with a digitally controlled leakage-based oscillator (DCLO) and a fast frequency relocking scheme adaptive to the amount of frequency drift during sleep state, which is required for intermittent operation of sensor node platforms.
{"title":"A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms","authors":"Dong-Woo Jee, D. Sylvester, D. Blaauw, J. Sim","doi":"10.1109/ISSCC.2013.6487694","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487694","url":null,"abstract":"Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential block, is one of the most actively researched blocks. It is required to distribute various frequency ranges for energy-optimal operation, e.g., Hz for internal timer [1], kHz for global clock [2], and MHz for fast data transmission or intensive signal processing [3]. However, free-running oscillators are seriously affected by process variations and should be readjusted by post-fabrication trimming. Though a crystal gives a stable frequency, the use of multiple crystals is generally not allowed by limited form-factor and increased cost. Instead, frequency multiplication from one clean reference is more effective way for higher frequency generation. Considering high-frequency clock is only intermittently used in sensor applications, the clock multiplier should provide a fast settling when turned on as well as low-power dissipation. This paper presents a 423nW, 3.2 MHz all-digital multiplying DLL (MDLL) with a digitally controlled leakage-based oscillator (DCLO) and a fast frequency relocking scheme adaptive to the amount of frequency drift during sleep state, which is required for intermittent operation of sensor node platforms.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"55 1","pages":"188-189"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86930099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487792
J. Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, L. Kim
For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].
{"title":"An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme","authors":"J. Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, L. Kim","doi":"10.1109/ISSCC.2013.6487792","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487792","url":null,"abstract":"For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"2 1","pages":"410-411"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90866534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487667
Xiaotie Wu, B. Dama, Prakash Gothoskar, P. Metz, K. Shastri, S. Sunder, Jan Van der Spiegel, Yifan Wang, M. Webster, Will Wilson
The need for more bandwidth driven by streaming video and other data intensive applications has been steadily pushing the optical link speed to the 40G/100G domain. Compared to VCSEL and ring resonator, Mach-Zehnder Interferometer (MZI) is the best solution for long distance (>500m), high data rate (>28Gb/s) optical communications [1-3]. However, high power consumption, low link density and high cost seriously prevent traditional MZI from being the next generation of optical link technology. To fundamentally reduce the cost of MZI, it is highly desirable to make the process CMOS compatible with high efficiency, thus the modulation voltage, size, and power can be reduced to a level where advanced sub-1V CMOS circuits can be used as the driver. This paper presents two CMOS-MZI-based optical transmitters, NRZ or configurable PAM-N (N = 4,16), featuring 20Gb/s data rate and sub-pJ/bit modulation energy (PAM-4) using a 1V supply. The fully CMOS compatible photonic device is highly cost-effective in terms of integration, manufacturability and scalability.
{"title":"A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS","authors":"Xiaotie Wu, B. Dama, Prakash Gothoskar, P. Metz, K. Shastri, S. Sunder, Jan Van der Spiegel, Yifan Wang, M. Webster, Will Wilson","doi":"10.1109/ISSCC.2013.6487667","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487667","url":null,"abstract":"The need for more bandwidth driven by streaming video and other data intensive applications has been steadily pushing the optical link speed to the 40G/100G domain. Compared to VCSEL and ring resonator, Mach-Zehnder Interferometer (MZI) is the best solution for long distance (>500m), high data rate (>28Gb/s) optical communications [1-3]. However, high power consumption, low link density and high cost seriously prevent traditional MZI from being the next generation of optical link technology. To fundamentally reduce the cost of MZI, it is highly desirable to make the process CMOS compatible with high efficiency, thus the modulation voltage, size, and power can be reduced to a level where advanced sub-1V CMOS circuits can be used as the driver. This paper presents two CMOS-MZI-based optical transmitters, NRZ or configurable PAM-N (N = 4,16), featuring 20Gb/s data rate and sub-pJ/bit modulation energy (PAM-4) using a 1V supply. The fully CMOS compatible photonic device is highly cost-effective in terms of integration, manufacturability and scalability.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"32 1","pages":"128-129"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90895980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487828
O. Shcherbakova, L. Pancheri, G. Betta, N. Massari, D. Stoppa
In the last few years, both the scientific and industrial communities have shown an increasing interest in range imaging, due to its potential exploitation in various application domains such as robotics, security and surveillance, vehicle safety, gaming, and mobile applications. Among the diversity of techniques available for range detection, Time-of-Flight (ToF) offers advantages in terms of compact system realization, good performance, and low required computational power. The last works on ToF sensors, presenting demodulation sensors based on photon-mixing devices [1, 2], and time-counting sensors based on single-photon avalanche diodes [3], have shown a trend towards higher resolutions, with a consequent reduction of pixel size, higher modulation frequencies, and demodulation contrast to allow better distance precision. In this paper, we introduce a range camera concept that exploits linear-mode avalanche photodiodes (APD) as in-pixel demodulating detectors [4]. Thanks to photocurrent gain modulation, APDs can combine optical sensing and light-signal demodulation in a single device. The main advantage of the APD implementation is the possibility to operate at high frequencies, due to its very wide bandwidth.
{"title":"3D camera based on linear-mode gain-modulated avalanche photodiodes","authors":"O. Shcherbakova, L. Pancheri, G. Betta, N. Massari, D. Stoppa","doi":"10.1109/ISSCC.2013.6487828","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487828","url":null,"abstract":"In the last few years, both the scientific and industrial communities have shown an increasing interest in range imaging, due to its potential exploitation in various application domains such as robotics, security and surveillance, vehicle safety, gaming, and mobile applications. Among the diversity of techniques available for range detection, Time-of-Flight (ToF) offers advantages in terms of compact system realization, good performance, and low required computational power. The last works on ToF sensors, presenting demodulation sensors based on photon-mixing devices [1, 2], and time-counting sensors based on single-photon avalanche diodes [3], have shown a trend towards higher resolutions, with a consequent reduction of pixel size, higher modulation frequencies, and demodulation contrast to allow better distance precision. In this paper, we introduce a range camera concept that exploits linear-mode avalanche photodiodes (APD) as in-pixel demodulating detectors [4]. Thanks to photocurrent gain modulation, APDs can combine optical sensing and light-signal demodulation in a single device. The main advantage of the APD implementation is the possibility to operate at high frequencies, due to its very wide bandwidth.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"490-491"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82110070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487724
Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu
Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.
{"title":"A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time","authors":"Tejasvi Anand, Mrunmay Talegaonkar, A. Elshazly, B. Young, P. Hanumolu","doi":"10.1109/ISSCC.2013.6487724","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487724","url":null,"abstract":"Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state power at 2.5GHz output frequency.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"144 1","pages":"256-257"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73511993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487791
M. Kossel, T. Toifl, P. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Andersen, T. Morf
Memory links use variable-impedance drivers, feed-forward equalization (FFE) [1], on-die termination (ODT) and slew-rate control to optimize the signal integrity (SI). An asymmetric DRAM link configuration exploits the availability of a fast CMOS technology on the memory controller side to implement powerful equalization, while keeping the circuit complexity on the DRAM side relatively simple. This paper proposes the use of Tomlinson Harashima precoding (THP) [2-4] in a memory controller as replacement of the afore-mentioned SI optimization techniques. THP is a transmitter equalization technique in which post-cursor inter-symbol interference (ISI) is cancelled by means of an infinite impulse response (IIR) filter with modulo-based amplitude limitation; similar to a decision feedback equalizer (DFE) on the receive side. However, in contrast to a DFE, THP does not suffer from error propagation.
{"title":"An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS","authors":"M. Kossel, T. Toifl, P. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Andersen, T. Morf","doi":"10.1109/ISSCC.2013.6487791","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487791","url":null,"abstract":"Memory links use variable-impedance drivers, feed-forward equalization (FFE) [1], on-die termination (ODT) and slew-rate control to optimize the signal integrity (SI). An asymmetric DRAM link configuration exploits the availability of a fast CMOS technology on the memory controller side to implement powerful equalization, while keeping the circuit complexity on the DRAM side relatively simple. This paper proposes the use of Tomlinson Harashima precoding (THP) [2-4] in a memory controller as replacement of the afore-mentioned SI optimization techniques. THP is a transmitter equalization technique in which post-cursor inter-symbol interference (ISI) is cancelled by means of an infinite impulse response (IIR) filter with modulo-based amplitude limitation; similar to a decision feedback equalizer (DFE) on the receive side. However, in contrast to a DFE, THP does not suffer from error propagation.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"17 1","pages":"408-409"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90437430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：