Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487714
Lingkai Kong, D. Seo, E. Alon
The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate this adoption, the cost of current mm-Wave solutions should also be reduced. Especially for short range designs (<;1m), overall cost may be dominated by packaging and testing. This paper therefore presents a low-power 60GHz CMOS 4-element phased-array QPSK transceiver with integrated slot-loop antennas. Utilizing such antennas as well as circuit stacking techniques, the transceiver achieves 10.4Gb/s with a range of >40cm in all directions while consuming only 115mW (TX+RX).
{"title":"A 50mW-TX 65mW-RX 60GHz 4-element phased-array transceiver with integrated antennas in 65nm CMOS","authors":"Lingkai Kong, D. Seo, E. Alon","doi":"10.1109/ISSCC.2013.6487714","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487714","url":null,"abstract":"The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate this adoption, the cost of current mm-Wave solutions should also be reduced. Especially for short range designs (<;1m), overall cost may be dominated by packaging and testing. This paper therefore presents a low-power 60GHz CMOS 4-element phased-array QPSK transceiver with integrated slot-loop antennas. Utilizing such antennas as well as circuit stacking techniques, the transceiver achieves 10.4Gb/s with a range of >40cm in all directions while consuming only 115mW (TX+RX).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"84 1","pages":"234-235"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83863164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487674
F. Caster, L. Gilreath, S. Pan, Z. Wang, F. Capolino, P. Heydari
Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RX's spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).
{"title":"A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control","authors":"F. Caster, L. Gilreath, S. Pan, Z. Wang, F. Capolino, P. Heydari","doi":"10.1109/ISSCC.2013.6487674","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487674","url":null,"abstract":"Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RX's spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"71 1","pages":"144-145"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86161717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487669
Yi Zhao, L. Vera, J. Long, D. Harame
This paper describes a 10Gb/s, digitally-controlled distributed amplifier (DA) implemented in 0.18μm SiGe (60GHz peak-fT) with 6Vpp differential output swing, <;20ps symmetric rise/fall times, negligible additive jitter and >10dB return loss across 30GHz bandwidth; performance suitable for driving a dual (i.e., balanced) MZ modulator. Unlike conventional DAs, which use a passive transmission line at the input to feed each amplifier cell with the correct signal phase, the gain cells in the prototype modulator driver are driven by digital latches. The fully-digital interface at the DA input leads to a scalable design by eliminating the performance impairments of the input transmission line.
{"title":"A 10Gb/s 6Vpp differential modulator driver in 0.18μm SiGe-BiCMOS","authors":"Yi Zhao, L. Vera, J. Long, D. Harame","doi":"10.1109/ISSCC.2013.6487669","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487669","url":null,"abstract":"This paper describes a 10Gb/s, digitally-controlled distributed amplifier (DA) implemented in 0.18μm SiGe (60GHz peak-fT) with 6Vpp differential output swing, <;20ps symmetric rise/fall times, negligible additive jitter and >10dB return loss across 30GHz bandwidth; performance suitable for driving a dual (i.e., balanced) MZ modulator. Unlike conventional DAs, which use a passive transmission line at the input to feed each amplifier cell with the correct signal phase, the gain cells in the prototype modulator driver are driven by digital latches. The fully-digital interface at the DA input leads to a scalable design by eliminating the performance impairments of the input transmission line.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"555 1","pages":"132-133"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77149753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487705
N. Miura, Mitsuko Saito, M. Taguchi, T. Kuroda
Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant power (e.g., 1% battery charge of a smartphone when 10 pictures are transferred through WLAN), making local memory card storage still attractive in mobile devices. As storage capacity increases, the I/O speed should also increase accordingly. However, conventional memory cards require strong ESD protection, limiting high-speed data transfer. A non-contact memory card [1] is one of the solutions to this problem. No signal terminals are exposed for mechanical contact, which relaxes ESD constraints. A data transfer rate of 6Gb/s/ch by inductive coupling [1] and 12Gb/s/ch by transmission-line coupling [2] are reported. The post-UHS-II speed over 5Gb/s can be covered with around 10mW power consumption. Moreover, by supplying power wirelessly, mechanical connections can be completely removed, which could provide features such as waterproof capability or a new attach-remove user interface. A >50% high-efficient wireless power delivery has been reported [3]. However, it mainly supplies a large amount of active power, and the efficiency drops to ~10% in low-power standby mode. Shutting down the power delivery in standby would require a power-on sequence and an unacceptably long suspend (~10s) for each new command. For high-speed card access, the power delivery and the wireless data receiver (RX) should always be active, consuming about 2mW in RX and in total 20mW including loss in the wireless power delivery. This standby power is almost identical to that of typical smartphones, tablet-PCs, or camcorders and the battery life halves.
{"title":"A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×","authors":"N. Miura, Mitsuko Saito, M. Taguchi, T. Kuroda","doi":"10.1109/ISSCC.2013.6487705","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487705","url":null,"abstract":"Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant power (e.g., 1% battery charge of a smartphone when 10 pictures are transferred through WLAN), making local memory card storage still attractive in mobile devices. As storage capacity increases, the I/O speed should also increase accordingly. However, conventional memory cards require strong ESD protection, limiting high-speed data transfer. A non-contact memory card [1] is one of the solutions to this problem. No signal terminals are exposed for mechanical contact, which relaxes ESD constraints. A data transfer rate of 6Gb/s/ch by inductive coupling [1] and 12Gb/s/ch by transmission-line coupling [2] are reported. The post-UHS-II speed over 5Gb/s can be covered with around 10mW power consumption. Moreover, by supplying power wirelessly, mechanical connections can be completely removed, which could provide features such as waterproof capability or a new attach-remove user interface. A >50% high-efficient wireless power delivery has been reported [3]. However, it mainly supplies a large amount of active power, and the efficiency drops to ~10% in low-power standby mode. Shutting down the power delivery in standby would require a power-on sequence and an unacceptably long suspend (~10s) for each new command. For high-speed card access, the power delivery and the wireless data receiver (RX) should always be active, consuming about 2mW in RX and in total 20mW including loss in the wireless power delivery. This standby power is almost identical to that of typical smartphones, tablet-PCs, or camcorders and the battery life halves.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"79 5 1","pages":"214-215"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77299603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487827
C. Niclass, M. Soga, H. Matsubara, Masaru Ogawa, M. Kagami
A number of potentially low-cost time-of-flight (ToF) 3D image sensors aiming at consumer electronics applications have recently appeared in CMOS. Diffused-light sensors taking advantage of SPAD pixels, conventional and pinned-photodiode lock-in pixels demonstrate centimeter-ranging performance in distances of typically up to 6m, and with the exception of, under low background light (BG) conditions. In those approaches, however, performance tends to rapidly deteriorate in severe BG conditions, such as outdoors, and long-distance ranges have yet to be reported. Another common limitation is their inability to cope with multi-echo target environments. Higher optical signal-to-background ratio (SBR), and hence better performance, is typically achieved by laser-scanning approaches, e.g. employing polygonal or MEMS mirrors. With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driving-assistance systems (ADAS), we introduce an SoC that performs time-correlated single-photon counting (TCSPC) and complete DSP for a 100m-range ToF sensor. The chip provides the system-level electronics with a serial and low-bit-rate digital interface for: multi-echo distance, distance reliability, intensity, and BG-only intensity, thus mitigating system-level complexity and cost.
{"title":"A 0.18µm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensor","authors":"C. Niclass, M. Soga, H. Matsubara, Masaru Ogawa, M. Kagami","doi":"10.1109/ISSCC.2013.6487827","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487827","url":null,"abstract":"A number of potentially low-cost time-of-flight (ToF) 3D image sensors aiming at consumer electronics applications have recently appeared in CMOS. Diffused-light sensors taking advantage of SPAD pixels, conventional and pinned-photodiode lock-in pixels demonstrate centimeter-ranging performance in distances of typically up to 6m, and with the exception of, under low background light (BG) conditions. In those approaches, however, performance tends to rapidly deteriorate in severe BG conditions, such as outdoors, and long-distance ranges have yet to be reported. Another common limitation is their inability to cope with multi-echo target environments. Higher optical signal-to-background ratio (SBR), and hence better performance, is typically achieved by laser-scanning approaches, e.g. employing polygonal or MEMS mirrors. With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driving-assistance systems (ADAS), we introduce an SoC that performs time-correlated single-photon counting (TCSPC) and complete DSP for a 100m-range ToF sensor. The chip provides the system-level electronics with a serial and low-bit-rate digital interface for: multi-echo distance, distance reliability, intensity, and BG-only intensity, thus mitigating system-level complexity and cost.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"136 1","pages":"488-489"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77459009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487682
Chao-Tsung Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan
The latest video coding standard High Efficiency Video Coding (HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.
最新的视频编码标准HEVC (High Efficiency video coding)[1]比H.264/AVC的编码效率提高了50%，以满足日益增长的视频流需求、更好的视频质量和更高的分辨率。使用更复杂的工具实现编码增益，例如在分层结构中使用更大和可变大小的编码单元(CU)，更大的变换和更长的插值滤波器。本文提出了一种支持四元全高清(QFHD, 3840×2160)视频解码的HEVC草案标准集成电路。它通过三个主要贡献解决了HEVC(“H.265”)的新设计挑战:1)一个适应可变大小最大编码单元(LCU)的系统流水线方案，并为内存优化提供了一个两阶段的子流水线;2)统一的处理引擎，以解决分层编码结构和许多预测和转换块大小的面积有效的方式;3)运动补偿(MC)缓存，它减少了LCU的DRAM带宽，并满足了由于长滤波器而产生的高吞吐量要求。
{"title":"A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications","authors":"Chao-Tsung Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan","doi":"10.1109/ISSCC.2013.6487682","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487682","url":null,"abstract":"The latest video coding standard High Efficiency Video Coding (HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"162-163"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91043046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487601
Leland Chang, S. Morton, Ken Chang, Jin-Man Han, P. Malcovati, V. Stojanović
Across the spectrum of microelectronics applications, power management is critical to the enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.
{"title":"F2: VLSI power-management techniques: Principles and applications","authors":"Leland Chang, S. Morton, Ken Chang, Jin-Man Han, P. Malcovati, V. Stojanović","doi":"10.1109/ISSCC.2013.6487601","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487601","url":null,"abstract":"Across the spectrum of microelectronics applications, power management is critical to the enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"26 1","pages":"502-503"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74286036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487795
T. Kao, Che-Fu Liang, H. Chiu, Michael Ashburn
Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI) is used to suppress the quantization noise due to its simplicity, but at a cost of gain error and non-linearity. These sub-phase non-idealities result in large fractional spurs [2-5]. Techniques for reducing these spurs include using a PI mismatch and spur-cancellation scheme [2], digital correlation and cancellation [3], use of a successive requantizer with switched loop filter and offset charge-pump [4], and foreground calibration [5]. This paper presents a ring-oscillator based 2MHz bandwidth fractional-N PLL that uses a spectrally shaped segmented-feedback approach to alleviate fractional spurs induced by the PI non-idealities. This approach results in a compact design and, in contrast to previous work, achieves a 26dB spur reduction without need of correlation, cancellation, or calibration methods.
{"title":"A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation","authors":"T. Kao, Che-Fu Liang, H. Chiu, Michael Ashburn","doi":"10.1109/ISSCC.2013.6487795","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487795","url":null,"abstract":"Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI) is used to suppress the quantization noise due to its simplicity, but at a cost of gain error and non-linearity. These sub-phase non-idealities result in large fractional spurs [2-5]. Techniques for reducing these spurs include using a PI mismatch and spur-cancellation scheme [2], digital correlation and cancellation [3], use of a successive requantizer with switched loop filter and offset charge-pump [4], and foreground calibration [5]. This paper presents a ring-oscillator based 2MHz bandwidth fractional-N PLL that uses a spectrally shaped segmented-feedback approach to alleviate fractional spurs induced by the PI non-idealities. This approach results in a compact design and, in contrast to previous work, achieves a 26dB spur reduction without need of correlation, cancellation, or calibration methods.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"34 1","pages":"416-417"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77312382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487763
Luca Fanori, P. Andreani
Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.
{"title":"A 2.5-to-3.3GHz CMOS Class-D VCO","authors":"Luca Fanori, P. Andreani","doi":"10.1109/ISSCC.2013.6487763","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487763","url":null,"abstract":"Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"58 6 1","pages":"346-347"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77569881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487673
Wei Tai, L. Carley, D. Ricketts
In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an output power of 0.7W with a power-added efficiency (PAE) of 10% at 42GHz and a -3dB bandwidth of 9GHz. This is 2.6 times more output power than a recently reported millimeter-Wave (mm-Wave) silicon-based PA [1]. The circuit is a fully integrated mm-Wave PA achieving a leading output power approaching 1 Watt in a silicon process.
{"title":"A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOS","authors":"Wei Tai, L. Carley, D. Ricketts","doi":"10.1109/ISSCC.2013.6487673","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487673","url":null,"abstract":"In this paper, we report a fully integrated power amplifier (PA) architecture that combines the power of 16 on-chip PAs using a 16-way zero-degree combiner to achieve an output power of 0.7W with a power-added efficiency (PAE) of 10% at 42GHz and a -3dB bandwidth of 9GHz. This is 2.6 times more output power than a recently reported millimeter-Wave (mm-Wave) silicon-based PA [1]. The circuit is a fully integrated mm-Wave PA achieving a leading output power approaching 1 Watt in a silicon process.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"109 1","pages":"142-143"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77802625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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