Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487714
Lingkai Kong, D. Seo, E. Alon
The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate this adoption, the cost of current mm-Wave solutions should also be reduced. Especially for short range designs (<;1m), overall cost may be dominated by packaging and testing. This paper therefore presents a low-power 60GHz CMOS 4-element phased-array QPSK transceiver with integrated slot-loop antennas. Utilizing such antennas as well as circuit stacking techniques, the transceiver achieves 10.4Gb/s with a range of >40cm in all directions while consuming only 115mW (TX+RX).
{"title":"A 50mW-TX 65mW-RX 60GHz 4-element phased-array transceiver with integrated antennas in 65nm CMOS","authors":"Lingkai Kong, D. Seo, E. Alon","doi":"10.1109/ISSCC.2013.6487714","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487714","url":null,"abstract":"The 60GHz band has gained great interest as an enabler for multi-Gb/s wireless links. Recent efforts [1-4] have focused on reducing transceiver power to drive adoption of 60GHz in mobile devices. To further accelerate this adoption, the cost of current mm-Wave solutions should also be reduced. Especially for short range designs (<;1m), overall cost may be dominated by packaging and testing. This paper therefore presents a low-power 60GHz CMOS 4-element phased-array QPSK transceiver with integrated slot-loop antennas. Utilizing such antennas as well as circuit stacking techniques, the transceiver achieves 10.4Gb/s with a range of >40cm in all directions while consuming only 115mW (TX+RX).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"84 1","pages":"234-235"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83863164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487674
F. Caster, L. Gilreath, S. Pan, Z. Wang, F. Capolino, P. Heydari
Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RX's spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).
{"title":"A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control","authors":"F. Caster, L. Gilreath, S. Pan, Z. Wang, F. Capolino, P. Heydari","doi":"10.1109/ISSCC.2013.6487674","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487674","url":null,"abstract":"Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RX's spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"71 1","pages":"144-145"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86161717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487669
Yi Zhao, L. Vera, J. Long, D. Harame
This paper describes a 10Gb/s, digitally-controlled distributed amplifier (DA) implemented in 0.18μm SiGe (60GHz peak-fT) with 6Vpp differential output swing, <;20ps symmetric rise/fall times, negligible additive jitter and >10dB return loss across 30GHz bandwidth; performance suitable for driving a dual (i.e., balanced) MZ modulator. Unlike conventional DAs, which use a passive transmission line at the input to feed each amplifier cell with the correct signal phase, the gain cells in the prototype modulator driver are driven by digital latches. The fully-digital interface at the DA input leads to a scalable design by eliminating the performance impairments of the input transmission line.
{"title":"A 10Gb/s 6Vpp differential modulator driver in 0.18μm SiGe-BiCMOS","authors":"Yi Zhao, L. Vera, J. Long, D. Harame","doi":"10.1109/ISSCC.2013.6487669","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487669","url":null,"abstract":"This paper describes a 10Gb/s, digitally-controlled distributed amplifier (DA) implemented in 0.18μm SiGe (60GHz peak-fT) with 6Vpp differential output swing, <;20ps symmetric rise/fall times, negligible additive jitter and >10dB return loss across 30GHz bandwidth; performance suitable for driving a dual (i.e., balanced) MZ modulator. Unlike conventional DAs, which use a passive transmission line at the input to feed each amplifier cell with the correct signal phase, the gain cells in the prototype modulator driver are driven by digital latches. The fully-digital interface at the DA input leads to a scalable design by eliminating the performance impairments of the input transmission line.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"555 1","pages":"132-133"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77149753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487705
N. Miura, Mitsuko Saito, M. Taguchi, T. Kuroda
Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant power (e.g., 1% battery charge of a smartphone when 10 pictures are transferred through WLAN), making local memory card storage still attractive in mobile devices. As storage capacity increases, the I/O speed should also increase accordingly. However, conventional memory cards require strong ESD protection, limiting high-speed data transfer. A non-contact memory card [1] is one of the solutions to this problem. No signal terminals are exposed for mechanical contact, which relaxes ESD constraints. A data transfer rate of 6Gb/s/ch by inductive coupling [1] and 12Gb/s/ch by transmission-line coupling [2] are reported. The post-UHS-II speed over 5Gb/s can be covered with around 10mW power consumption. Moreover, by supplying power wirelessly, mechanical connections can be completely removed, which could provide features such as waterproof capability or a new attach-remove user interface. A >50% high-efficient wireless power delivery has been reported [3]. However, it mainly supplies a large amount of active power, and the efficiency drops to ~10% in low-power standby mode. Shutting down the power delivery in standby would require a power-on sequence and an unacceptably long suspend (~10s) for each new command. For high-speed card access, the power delivery and the wireless data receiver (RX) should always be active, consuming about 2mW in RX and in total 20mW including loss in the wireless power delivery. This standby power is almost identical to that of typical smartphones, tablet-PCs, or camcorders and the battery life halves.
{"title":"A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×","authors":"N. Miura, Mitsuko Saito, M. Taguchi, T. Kuroda","doi":"10.1109/ISSCC.2013.6487705","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487705","url":null,"abstract":"Memory cards are widely used in electronic systems to expand internal storage area or are used as detachable media to carry data. Although cloud computing has recently drawn attention, data transfer consumes significant power (e.g., 1% battery charge of a smartphone when 10 pictures are transferred through WLAN), making local memory card storage still attractive in mobile devices. As storage capacity increases, the I/O speed should also increase accordingly. However, conventional memory cards require strong ESD protection, limiting high-speed data transfer. A non-contact memory card [1] is one of the solutions to this problem. No signal terminals are exposed for mechanical contact, which relaxes ESD constraints. A data transfer rate of 6Gb/s/ch by inductive coupling [1] and 12Gb/s/ch by transmission-line coupling [2] are reported. The post-UHS-II speed over 5Gb/s can be covered with around 10mW power consumption. Moreover, by supplying power wirelessly, mechanical connections can be completely removed, which could provide features such as waterproof capability or a new attach-remove user interface. A >50% high-efficient wireless power delivery has been reported [3]. However, it mainly supplies a large amount of active power, and the efficiency drops to ~10% in low-power standby mode. Shutting down the power delivery in standby would require a power-on sequence and an unacceptably long suspend (~10s) for each new command. For high-speed card access, the power delivery and the wireless data receiver (RX) should always be active, consuming about 2mW in RX and in total 20mW including loss in the wireless power delivery. This standby power is almost identical to that of typical smartphones, tablet-PCs, or camcorders and the battery life halves.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"79 5 1","pages":"214-215"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77299603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487827
C. Niclass, M. Soga, H. Matsubara, Masaru Ogawa, M. Kagami
A number of potentially low-cost time-of-flight (ToF) 3D image sensors aiming at consumer electronics applications have recently appeared in CMOS. Diffused-light sensors taking advantage of SPAD pixels, conventional and pinned-photodiode lock-in pixels demonstrate centimeter-ranging performance in distances of typically up to 6m, and with the exception of, under low background light (BG) conditions. In those approaches, however, performance tends to rapidly deteriorate in severe BG conditions, such as outdoors, and long-distance ranges have yet to be reported. Another common limitation is their inability to cope with multi-echo target environments. Higher optical signal-to-background ratio (SBR), and hence better performance, is typically achieved by laser-scanning approaches, e.g. employing polygonal or MEMS mirrors. With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driving-assistance systems (ADAS), we introduce an SoC that performs time-correlated single-photon counting (TCSPC) and complete DSP for a 100m-range ToF sensor. The chip provides the system-level electronics with a serial and low-bit-rate digital interface for: multi-echo distance, distance reliability, intensity, and BG-only intensity, thus mitigating system-level complexity and cost.
{"title":"A 0.18µm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensor","authors":"C. Niclass, M. Soga, H. Matsubara, Masaru Ogawa, M. Kagami","doi":"10.1109/ISSCC.2013.6487827","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487827","url":null,"abstract":"A number of potentially low-cost time-of-flight (ToF) 3D image sensors aiming at consumer electronics applications have recently appeared in CMOS. Diffused-light sensors taking advantage of SPAD pixels, conventional and pinned-photodiode lock-in pixels demonstrate centimeter-ranging performance in distances of typically up to 6m, and with the exception of, under low background light (BG) conditions. In those approaches, however, performance tends to rapidly deteriorate in severe BG conditions, such as outdoors, and long-distance ranges have yet to be reported. Another common limitation is their inability to cope with multi-echo target environments. Higher optical signal-to-background ratio (SBR), and hence better performance, is typically achieved by laser-scanning approaches, e.g. employing polygonal or MEMS mirrors. With the emerging need for high-resolution light detection and ranging (LIDAR) technologies in advanced driving-assistance systems (ADAS), we introduce an SoC that performs time-correlated single-photon counting (TCSPC) and complete DSP for a 100m-range ToF sensor. The chip provides the system-level electronics with a serial and low-bit-rate digital interface for: multi-echo distance, distance reliability, intensity, and BG-only intensity, thus mitigating system-level complexity and cost.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"136 1","pages":"488-489"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77459009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487682
Chao-Tsung Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan
The latest video coding standard High Efficiency Video Coding (HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.
最新的视频编码标准HEVC (High Efficiency video coding)[1]比H.264/AVC的编码效率提高了50%，以满足日益增长的视频流需求、更好的视频质量和更高的分辨率。使用更复杂的工具实现编码增益，例如在分层结构中使用更大和可变大小的编码单元(CU)，更大的变换和更长的插值滤波器。本文提出了一种支持四元全高清(QFHD, 3840×2160)视频解码的HEVC草案标准集成电路。它通过三个主要贡献解决了HEVC(“H.265”)的新设计挑战:1)一个适应可变大小最大编码单元(LCU)的系统流水线方案，并为内存优化提供了一个两阶段的子流水线;2)统一的处理引擎，以解决分层编码结构和许多预测和转换块大小的面积有效的方式;3)运动补偿(MC)缓存，它减少了LCU的DRAM带宽，并满足了由于长滤波器而产生的高吞吐量要求。
{"title":"A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications","authors":"Chao-Tsung Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan","doi":"10.1109/ISSCC.2013.6487682","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487682","url":null,"abstract":"The latest video coding standard High Efficiency Video Coding (HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"3 1","pages":"162-163"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91043046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487642
T. Tsai, Kai Chen
Energy harvesting is an attractive technique to take advantage of renewable energy and make systems, such as wireless sensor nodes, less dependent on external power sources. A photovoltaic (PV) energy-harvesting charger can convert energy from solar panels to charge batteries or super capacitors. To manage the variation in illumination, maximum power point tracking (MPPT) is essential to lock the output power of solar panels on the maximum power points [1, 2]. For any generic solar cell, its output current is determined by the output voltage in an exponential relation. Without knowing the characteristics of the solar cell in advance, it is necessary to monitor a feedback parameter to reach its maximum power point. Current measurement is needed at the output of the boost converter [1] or in the output path of the solar cell [2]. Motivated by the topology in [2], we propose a mixed-signal integration to avoid power hungry digital signal processing. In this paper, we report a charger with an integrated MPPT controller that can provide fast tracking for wide-range illumination levels while keeping high conversion efficiency. Also, a battery management unit is implemented and integrated on the same IC.
{"title":"A 3.4mW photovoltaic energy-harvesting charger with integrated maximum power point tracking and battery management","authors":"T. Tsai, Kai Chen","doi":"10.1109/ISSCC.2013.6487642","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487642","url":null,"abstract":"Energy harvesting is an attractive technique to take advantage of renewable energy and make systems, such as wireless sensor nodes, less dependent on external power sources. A photovoltaic (PV) energy-harvesting charger can convert energy from solar panels to charge batteries or super capacitors. To manage the variation in illumination, maximum power point tracking (MPPT) is essential to lock the output power of solar panels on the maximum power points [1, 2]. For any generic solar cell, its output current is determined by the output voltage in an exponential relation. Without knowing the characteristics of the solar cell in advance, it is necessary to monitor a feedback parameter to reach its maximum power point. Current measurement is needed at the output of the boost converter [1] or in the output path of the solar cell [2]. Motivated by the topology in [2], we propose a mixed-signal integration to avoid power hungry digital signal processing. In this paper, we report a charger with an integrated MPPT controller that can provide fast tracking for wide-range illumination levels while keeping high conversion efficiency. Also, a battery management unit is implemented and integrated on the same IC.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"17 1","pages":"72-73"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88753006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487769
Zhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu
There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of -98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].
{"title":"A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners","authors":"Zhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu","doi":"10.1109/ISSCC.2013.6487769","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487769","url":null,"abstract":"There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. In recent years, next generations of DVB standards (e.g. DVB-T2 and DVB-C2) are proposed, which adopt 256 QAM and even 4k QAM modulation to obtain higher performance. Often the DTV tuners employ a direct-conversion Zero-IF architecture, which demands the use of a wideband fractional-N synthesizer as the local oscillator (LO) to cover the frequency range of 50 to 900MHz. This LO needs to meet a very stringent phase noise requirement with an adequate target phase noise of -98dBc/Hz at a 10kHz offset and integrated rms phase error less than 0.25° [1]. However, it is well known that the performance of fractional-N PLLs is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise and raise reference and fractional spurs [2].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"12 1","pages":"358-359"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90601705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487792
J. Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, L. Kim
For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].
{"title":"An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme","authors":"J. Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, L. Kim","doi":"10.1109/ISSCC.2013.6487792","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487792","url":null,"abstract":"For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"2 1","pages":"410-411"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90866534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487762
J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski
An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.
{"title":"A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS","authors":"J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski","doi":"10.1109/ISSCC.2013.6487762","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487762","url":null,"abstract":"An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"54 1","pages":"342-343"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89399324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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