Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651904
Ben Niewenhuis, R. D. Blanton, M. Bhargava, K. Mai
Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated in a 65nm bulk CMOS process in support of these claims. While approximately 20% of the total population of scan elements are unreliable across temperature variations, we find that simple unanimous selection schemes can result in mean error rates of less than 0.1% for the selected populations across all measurements collected.
{"title":"SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states","authors":"Ben Niewenhuis, R. D. Blanton, M. Bhargava, K. Mai","doi":"10.1109/TEST.2013.6651904","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651904","url":null,"abstract":"Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated in a 65nm bulk CMOS process in support of these claims. While approximately 20% of the total population of scan elements are unreliable across temperature variations, we find that simple unanimous selection schemes can result in mean error rates of less than 0.1% for the selected populations across all measurements collected.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"168 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86512060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651930
Kun-Han Tsai, S. Sheng
The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.
{"title":"Design rule check on the clock gating logic for testability and beyond","authors":"Kun-Han Tsai, S. Sheng","doi":"10.1109/TEST.2013.6651930","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651930","url":null,"abstract":"The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"14 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85931215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651909
K. Ichiyama, M. Ishida, Kenichi Nagatani, Toshifumi Watanabe
Recently, there is an increasing need for methods of functionally testing RF devices to provide lower cost alternatives to testing RF communication systems. In this paper, a real-time functional testing method of RF-ICs using a digital tester is proposed as an alternative to conventional RF testing. The method is based on a concept of direct modulation. By employing the proposed method, the QPSK and 16-QAM signals can be generated with digital tester drivers. The method can directly compare the baseband data with its expected data through digital tester comparators without demodulation. Therefore, the proposed method does not require any modulator or demodulator. Moreover, the method can perform both a stress test of RF receivers by injecting modulation error and a margin test of RF transmitters by using a dual-threshold comparator.
{"title":"A functional test of 2-GHz/4-GHz RF digital communication device using digital tester","authors":"K. Ichiyama, M. Ishida, Kenichi Nagatani, Toshifumi Watanabe","doi":"10.1109/TEST.2013.6651909","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651909","url":null,"abstract":"Recently, there is an increasing need for methods of functionally testing RF devices to provide lower cost alternatives to testing RF communication systems. In this paper, a real-time functional testing method of RF-ICs using a digital tester is proposed as an alternative to conventional RF testing. The method is based on a concept of direct modulation. By employing the proposed method, the QPSK and 16-QAM signals can be generated with digital tester drivers. The method can directly compare the baseband data with its expected data through digital tester comparators without demodulation. Therefore, the proposed method does not require any modulator or demodulator. Moreover, the method can perform both a stress test of RF receivers by injecting modulation error and a margin test of RF transmitters by using a dual-threshold comparator.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"20 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88073497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651921
A. Nassery, J. Jeong, S. Ozev
In this paper we present a self-test method for RF transceivers to determine IQ imbalance, time skews, IIP3, IIP5, AM/AM, and AM/PM distortion with no hardware overhead. The analysis is done through the loop-back set-up over two frames, each of which is 200us in duration. The overall measurement time is less than 10ms including the computation time. The determined parameters can be used for digital calibration, which greatly enhances reliability and yield by widening the tolerance of the parameters. We show through hardware measurements that the target performance parameters can be determined accurately and the EVM can be reduced more than 5 folds, making even highly impaired systems usable. The only additional component to enable our approach is an attenuator in the loop-back path, which can be placed outside the chip. Hence, we call this self test and calibration approach a zero overhead approach.
{"title":"Zero-overhead self test and calibration of RF transceivers","authors":"A. Nassery, J. Jeong, S. Ozev","doi":"10.1109/TEST.2013.6651921","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651921","url":null,"abstract":"In this paper we present a self-test method for RF transceivers to determine IQ imbalance, time skews, IIP3, IIP5, AM/AM, and AM/PM distortion with no hardware overhead. The analysis is done through the loop-back set-up over two frames, each of which is 200us in duration. The overall measurement time is less than 10ms including the computation time. The determined parameters can be used for digital calibration, which greatly enhances reliability and yield by widening the tolerance of the parameters. We show through hardware measurements that the target performance parameters can be determined accurately and the EVM can be reduced more than 5 folds, making even highly impaired systems usable. The only additional component to enable our approach is an attenuator in the loop-back path, which can be placed outside the chip. Hence, we call this self test and calibration approach a zero overhead approach.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"96 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78676915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651883
H. Okawara
Mixed signal ATE (Automated Test Equipment) often integrates a waveform sampler for testing UHF signals. While performing under-sampling, slow jitter greatly influences the captured signal which is reconstructed into a meaningful waveform by manner of coherent waveform reconstruction. The purpose of this work is to remove slow jitter effects from a high-speed digital signal measured by a waveform sampler and to reconstruct a clear waveform and eye pattern. The test signal is a PRBS (Pseudo Random Binary Sequence) bit stream with slow jitter. The PRBS signal becomes an extreme wideband multi-tone from a spectrum point of view, so capturing such a signal with a waveform sampler needs a carefully organized test plan based on the coherent condition. Measured data is reconstructed into a meaningful waveform by reshuffling the sequence of the sampled points. Jitter in the signal is a kind of PM (Phase Modulation) which smears the spectrum. So the point of processing is to demodulate the PM signal and then restore the original multi-tone components. An elegant mathematical equation is introduced to perform the carrier tone recovery. Because of the multi-tone structure, processing needs to be applied to each one of the tone components. First, the PM effect is removed from each tone, and then each tone needs to be compensated amplitude loss by referencing the original tone power. Finally processing successfully reconstructs a clear PRBS waveform and a big eye opening. This paper reports the signal processing in detail with showing 7 Gbps 127-bit PRBS waveform.
{"title":"Advanced method to refine waveform smeared by jitter in waveform sampler measurement","authors":"H. Okawara","doi":"10.1109/TEST.2013.6651883","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651883","url":null,"abstract":"Mixed signal ATE (Automated Test Equipment) often integrates a waveform sampler for testing UHF signals. While performing under-sampling, slow jitter greatly influences the captured signal which is reconstructed into a meaningful waveform by manner of coherent waveform reconstruction. The purpose of this work is to remove slow jitter effects from a high-speed digital signal measured by a waveform sampler and to reconstruct a clear waveform and eye pattern. The test signal is a PRBS (Pseudo Random Binary Sequence) bit stream with slow jitter. The PRBS signal becomes an extreme wideband multi-tone from a spectrum point of view, so capturing such a signal with a waveform sampler needs a carefully organized test plan based on the coherent condition. Measured data is reconstructed into a meaningful waveform by reshuffling the sequence of the sampled points. Jitter in the signal is a kind of PM (Phase Modulation) which smears the spectrum. So the point of processing is to demodulate the PM signal and then restore the original multi-tone components. An elegant mathematical equation is introduced to perform the carrier tone recovery. Because of the multi-tone structure, processing needs to be applied to each one of the tone components. First, the PM effect is removed from each tone, and then each tone needs to be compensated amplitude loss by referencing the original tone power. Finally processing successfully reconstructs a clear PRBS waveform and a big eye opening. This paper reports the signal processing in detail with showing 7 Gbps 127-bit PRBS waveform.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"203 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79000831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651898
Jakub Janicki, J. Tyszer, Wu-Tung Cheng, Yu Huang, M. Kassab, N. Mukherjee, J. Rajski, Yan Dong, G. Giles
The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.
{"title":"EDT bandwidth management - Practical scenarios for large SoC designs","authors":"Jakub Janicki, J. Tyszer, Wu-Tung Cheng, Yu Huang, M. Kassab, N. Mukherjee, J. Rajski, Yan Dong, G. Giles","doi":"10.1109/TEST.2013.6651898","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651898","url":null,"abstract":"The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"84 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76131646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651887
D. Watanabe, S. Masuda, H. Hara, T. Ataka, A. Seki, A. Ono, T. Okayasu
To enable high-volume testing of LSIs with high-speed optical and electrical interfaces, we developed a proof-of-concept device of an optical LSI test system for use in mass-production testing. Key technologies include high-density and high-performance optical functional devices and a device interface enabling simultaneous connection of optical and electrical interfaces. Our proposed system, using PLZT thin-film modulators, supports multi-channel optical bit-error-rate (BER) testing of devices with signal rates up to 30 Gb/s with results that correlate reasonably well with those measured by conventional BER test system (BERTs). Moreover, our newly developed opto-electronic hybrid interface socket enables high-volume testing with good insertion losses and repeatability. Additionally, our flexible system architecture can be used for testing at various laser wavelengths and with various parameters for optical LSIs in combination with off-the-shelf instruments for meeting optical characterization requirements.
{"title":"30-Gb/s optical and electrical test solution for high-volume testing","authors":"D. Watanabe, S. Masuda, H. Hara, T. Ataka, A. Seki, A. Ono, T. Okayasu","doi":"10.1109/TEST.2013.6651887","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651887","url":null,"abstract":"To enable high-volume testing of LSIs with high-speed optical and electrical interfaces, we developed a proof-of-concept device of an optical LSI test system for use in mass-production testing. Key technologies include high-density and high-performance optical functional devices and a device interface enabling simultaneous connection of optical and electrical interfaces. Our proposed system, using PLZT thin-film modulators, supports multi-channel optical bit-error-rate (BER) testing of devices with signal rates up to 30 Gb/s with results that correlate reasonably well with those measured by conventional BER test system (BERTs). Moreover, our newly developed opto-electronic hybrid interface socket enables high-volume testing with good insertion losses and repeatability. Additionally, our flexible system architecture can be used for testing at various laser wavelengths and with various parameters for optical LSIs in combination with off-the-shelf instruments for meeting optical characterization requirements.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"28 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79691306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651923
S. Arasu, M. Nourani, J. Carulli, K. Butler, V. Reddy
A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.
{"title":"A design-for-reliability approach based on grading library cells for aging effects","authors":"S. Arasu, M. Nourani, J. Carulli, K. Butler, V. Reddy","doi":"10.1109/TEST.2013.6651923","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651923","url":null,"abstract":"A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"1 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77920791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651931
P. Venkataramani, V. Agrawal
A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.
{"title":"ATE test time reduction using asynchronous clock period","authors":"P. Venkataramani, V. Agrawal","doi":"10.1109/TEST.2013.6651931","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651931","url":null,"abstract":"A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"27 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80751556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651926
Hongyan Zhang, L. Bauer, M. Kochte, E. Schneider, Claus Braun, M. Imhof, H. Wunderlich, J. Henkel
Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.
{"title":"Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures","authors":"Hongyan Zhang, L. Bauer, M. Kochte, E. Schneider, Claus Braun, M. Imhof, H. Wunderlich, J. Henkel","doi":"10.1109/TEST.2013.6651926","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651926","url":null,"abstract":"Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"29 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84289564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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