Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651922
N. Azuma, T. Makita, S. Ueyama, M. Nagata, Satoru Takahashi, M. Murakami, K. Hori, Satoshi Tanaka, M. Yamaguchi
The tolerance of RF ICs against on-chip in-band interferers is diagnosed from the viewpoints of the quality of wireless channels compliant with LTE standards. The on-chip interferers inevitably propagate from other active circuits like digital backend processors through silicon substrate coupling in the same die of system-level integration. An in-system diagnosis platform of RF ICs presented in this paper relates the impacts of such interferers on the circuit-level response and system-level communication performance metrics. The figures of communication quality at a system level, like EVM, BER and throughput are concurrently evaluated with the strengths of interferers in different forms and at different locations in a silicon chip. The interferers are measured as the in-band signal to spurious power ratio at the output of RF ICs, the magnitude of substrate voltage fluctuations at the proximity of RF ICs, and related with the amount of power current consumed by base-band digital ICs. The tolerance of RF ICs is represented by the maximum strength of on-chip interferers for sustaining prescribed communication performance. The diagnosis system is divided into two parts, (i) a system-level RF simulator handling modulation and demodulation of real communication vectors in LTE format and also enabling hardware connectivity with RF ICs, and (ii) a silicon emulator of on-chip interferers coupled to the RF ICs. A 65 nm CMOS chip incorporates an on-chip arbitrary noise generator, an on-chip waveform capture, and RF IC for LTE receiver front end, and demonstrates the entire diagnosis.
{"title":"In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers","authors":"N. Azuma, T. Makita, S. Ueyama, M. Nagata, Satoru Takahashi, M. Murakami, K. Hori, Satoshi Tanaka, M. Yamaguchi","doi":"10.1109/TEST.2013.6651922","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651922","url":null,"abstract":"The tolerance of RF ICs against on-chip in-band interferers is diagnosed from the viewpoints of the quality of wireless channels compliant with LTE standards. The on-chip interferers inevitably propagate from other active circuits like digital backend processors through silicon substrate coupling in the same die of system-level integration. An in-system diagnosis platform of RF ICs presented in this paper relates the impacts of such interferers on the circuit-level response and system-level communication performance metrics. The figures of communication quality at a system level, like EVM, BER and throughput are concurrently evaluated with the strengths of interferers in different forms and at different locations in a silicon chip. The interferers are measured as the in-band signal to spurious power ratio at the output of RF ICs, the magnitude of substrate voltage fluctuations at the proximity of RF ICs, and related with the amount of power current consumed by base-band digital ICs. The tolerance of RF ICs is represented by the maximum strength of on-chip interferers for sustaining prescribed communication performance. The diagnosis system is divided into two parts, (i) a system-level RF simulator handling modulation and demodulation of real communication vectors in LTE format and also enabling hardware connectivity with RF ICs, and (ii) a silicon emulator of on-chip interferers coupled to the RF ICs. A 65 nm CMOS chip incorporates an on-chip arbitrary noise generator, an on-chip waveform capture, and RF IC for LTE receiver front end, and demonstrates the entire diagnosis.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"65 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72817879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651899
Yang Xue, O. Poku, Xin Li, Shawn Blanton
Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite these advances, it is often the case however that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. Imperfect resolution greatly hinders any follow-on, information-extraction analyses (e.g., physical failure analysis, volume diagnosis, etc.) due to the resulting ambiguity. To address this major challenge, a novel, unsupervised learning methodology that uses ordinarily-available tester and simulation data is described that significantly improves resolution with virtually no negative impact on accuracy. Simulation experiments using a variety of fault types (SSL, MSL, bridges, opens and cell-level input-pattern faults) reveal that the number of failed ICs that have perfect resolution can be more than doubled, and overall resolution is improved by 22%. Application to silicon data also demonstrates significant improvement in resolution (38% overall and the number of chips with ideal resolution is nearly tripled) and verification using PFA demonstrates that accuracy is maintained.
{"title":"PADRE: Physically-Aware Diagnostic Resolution Enhancement","authors":"Yang Xue, O. Poku, Xin Li, Shawn Blanton","doi":"10.1109/TEST.2013.6651899","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651899","url":null,"abstract":"Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite these advances, it is often the case however that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. Imperfect resolution greatly hinders any follow-on, information-extraction analyses (e.g., physical failure analysis, volume diagnosis, etc.) due to the resulting ambiguity. To address this major challenge, a novel, unsupervised learning methodology that uses ordinarily-available tester and simulation data is described that significantly improves resolution with virtually no negative impact on accuracy. Simulation experiments using a variety of fault types (SSL, MSL, bridges, opens and cell-level input-pattern faults) reveal that the number of failed ICs that have perfect resolution can be more than doubled, and overall resolution is improved by 22%. Application to silicon data also demonstrates significant improvement in resolution (38% overall and the number of chips with ideal resolution is nearly tripled) and verification using PFA demonstrates that accuracy is maintained.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"50 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87613030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.
{"title":"Delay testing and characterization of post-bond interposer wires in 2.5-D ICs","authors":"Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng","doi":"10.1109/TEST.2013.6651906","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651906","url":null,"abstract":"Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"73 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84344219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651908
S. Carlo, Giulio Gambardella, Ippazio Martella, P. Prinetto, Daniele Rolfo, Pascal Trotta
High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents effective fault mitigation strategies for CUDA-based GPUs against permanent faults. The methodology to apply these strategies, on the software to be executed, is fully described and verified. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementation, even in presence of multiple permanent faults.
{"title":"Fault mitigation strategies for CUDA GPUs","authors":"S. Carlo, Giulio Gambardella, Ippazio Martella, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/TEST.2013.6651908","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651908","url":null,"abstract":"High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents effective fault mitigation strategies for CUDA-based GPUs against permanent faults. The methodology to apply these strategies, on the software to be executed, is fully described and verified. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementation, even in presence of multiple permanent faults.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"7 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75221624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651920
Siva Sudani, Li Xu, Degang Chen
For spectral testing of Built-in Self-Test Analog to Digital Converters, it is a very challenging task to precisely control the amplitude and frequency of input sinusoid signal. Amplitude over-range results in clipping ADC output and non-coherent sampling results in spectral leakage. In this paper, a new method is proposed that provides accurate spectral results even when the input to ADC is both over-ranged and non-coherently sampled. This relaxes the condition to have precise control over the input signal and thus decreases the cost. The method includes fundamental identification, removal and residue interpolation to obtain accurate spectral results. Simulations show the functionality and robustness of proposed method with both non-coherency and amplitude over-range. Measurement results of a commercially available 16-bit SAR ADC are used to verify the method for both functionality and robustness.
{"title":"Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping","authors":"Siva Sudani, Li Xu, Degang Chen","doi":"10.1109/TEST.2013.6651920","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651920","url":null,"abstract":"For spectral testing of Built-in Self-Test Analog to Digital Converters, it is a very challenging task to precisely control the amplitude and frequency of input sinusoid signal. Amplitude over-range results in clipping ADC output and non-coherent sampling results in spectral leakage. In this paper, a new method is proposed that provides accurate spectral results even when the input to ADC is both over-ranged and non-coherently sampled. This relaxes the condition to have precise control over the input signal and thus decreases the cost. The method includes fundamental identification, removal and residue interpolation to obtain accurate spectral results. Simulations show the functionality and robustness of proposed method with both non-coherency and amplitude over-range. Measurement results of a commercially available 16-bit SAR ADC are used to verify the method for both functionality and robustness.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"9 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82238424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651893
S. Goel, S. Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, F. Lee, V. Chickermane, B. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Lee, Jungi Choi, Sang-Duek Kim
Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.
{"title":"Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study","authors":"S. Goel, S. Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, F. Lee, V. Chickermane, B. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Lee, Jungi Choi, Sang-Duek Kim","doi":"10.1109/TEST.2013.6651893","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651893","url":null,"abstract":"Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"70 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76706790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651897
K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.
{"title":"SmartScan - Hierarchical test compression for pin-limited low power designs","authors":"K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj","doi":"10.1109/TEST.2013.6651897","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651897","url":null,"abstract":"IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"105 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82690645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651890
N. Sumikawa, Li-C. Wang, M. Abadir
This work presents three pattern mining methodologies for inter-wafer abnormality analysis. Given a large population of wafers, the first methodology identifies wafers with abnormal patterns based on a test or a group of tests. Given a wafer of interest, the second methodology searches for a test perspective that reveals the abnormality of the wafer. Given a particular pattern of interest, the third methodology implements a monitor to detect wafers containing similar patterns. This paper discusses key elements for implementing each of the methodologies and demonstrates their usefulness based on experiments applied to a high-quality SoC product line.
{"title":"A pattern mining framework for inter-wafer abnormality analysis","authors":"N. Sumikawa, Li-C. Wang, M. Abadir","doi":"10.1109/TEST.2013.6651890","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651890","url":null,"abstract":"This work presents three pattern mining methodologies for inter-wafer abnormality analysis. Given a large population of wafers, the first methodology identifies wafers with abnormal patterns based on a test or a group of tests. Given a wafer of interest, the second methodology searches for a test perspective that reveals the abnormality of the wafer. Given a particular pattern of interest, the third methodology implements a monitor to detect wafers containing similar patterns. This paper discusses key elements for implementing each of the methodologies and demonstrates their usefulness based on experiments applied to a high-quality SoC product line.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"70 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91066997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651903
Jennifer Dworak, A. Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton
IEEE P1687 is a valuable tool for accessing on-chip instruments during test, diagnosis, debug, and board configuration. However, most of these instruments should not be available to an end user in the field. We propose a method for hiding instruments in a P1687 network that utilizes a “locking” segment insertion bit (LSIB) that can only be opened when pre-defined values, corresponding to a key, are present in particular bits in the chain. We also introduce “trap” bits, which can further reduce the effectiveness of brute force attacks by permanently locking an LSIB when an incorrect value is written to the trap's update register. Only a global reset will allow the LSIB to become operable again. In this paper, we investigate the cost and effectiveness of LSIBs and traps in several different configurations and show that these relatively small modifications to the P1687 network can make undocumented instrument access exceedingly difficult.
{"title":"Don't forget to lock your SIB: hiding instruments using P1687","authors":"Jennifer Dworak, A. Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton","doi":"10.1109/TEST.2013.6651903","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651903","url":null,"abstract":"IEEE P1687 is a valuable tool for accessing on-chip instruments during test, diagnosis, debug, and board configuration. However, most of these instruments should not be available to an end user in the field. We propose a method for hiding instruments in a P1687 network that utilizes a “locking” segment insertion bit (LSIB) that can only be opened when pre-defined values, corresponding to a key, are present in particular bits in the chain. We also introduce “trap” bits, which can further reduce the effectiveness of brute force attacks by permanently locking an LSIB when an incorrect value is written to the trap's update register. Only a global reset will allow the LSIB to become operable again. In this paper, we investigate the cost and effectiveness of LSIBs and traps in several different configurations and show that these relatively small modifications to the P1687 network can make undocumented instrument access exceedingly difficult.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"36 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90219163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/TEST.2013.6651912
Degang Chen, Zhongjun Yu, Krunal Maniar, M. Nowrozi
Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.
{"title":"Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations","authors":"Degang Chen, Zhongjun Yu, Krunal Maniar, M. Nowrozi","doi":"10.1109/TEST.2013.6651912","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651912","url":null,"abstract":"Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"64 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83900436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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