Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035300
Sajjad Pagarkar
Volume manufacturing often highlights aspects of post silicon data analysis that are otherwise overlooked. Yield-overkill, in simple terms, can be defined as failing perfectly good/functional devices due to device testability. Such yield overkill is often linked to tight test conditions using advanced fault models and functional tests. Transition Delay Fault Model (TDF) is one such widely used fault model to detect speed related manufacturing defects. “How do I know whether a given TDF fallout is real or an artifact of some test/process/design combination that may never ever get exercised in the system (functional testing)?”. We deal with analyzing such situations on a daily basis. Often the decisions are more scientific, where a successful PFA of a TDF failure may reveal process issues (thinned oxide, weak metal, broken via etc) but many a times could be a ghost hunt - burning debug cycles (vector, design, system correlation, FA etc) and eventually living with the yield overkill. With complexities in semiconductor design and manufacturing ever increasing (faster designs in small process nodes with increasing quality requirements) solving such real time low level problems is going to be critical for companies to maintain their profitability. The EDA industry has come a long way in abstracting advance fault models - however, the EDA industry needs to go further and address the fine subtleties of design/test/process interactions ensuring rightful balance between cost and quality.
{"title":"Challenges of testing 100M chips","authors":"Sajjad Pagarkar","doi":"10.1109/TEST.2014.7035300","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035300","url":null,"abstract":"Volume manufacturing often highlights aspects of post silicon data analysis that are otherwise overlooked. Yield-overkill, in simple terms, can be defined as failing perfectly good/functional devices due to device testability. Such yield overkill is often linked to tight test conditions using advanced fault models and functional tests. Transition Delay Fault Model (TDF) is one such widely used fault model to detect speed related manufacturing defects. “How do I know whether a given TDF fallout is real or an artifact of some test/process/design combination that may never ever get exercised in the system (functional testing)?”. We deal with analyzing such situations on a daily basis. Often the decisions are more scientific, where a successful PFA of a TDF failure may reveal process issues (thinned oxide, weak metal, broken via etc) but many a times could be a ghost hunt - burning debug cycles (vector, design, system correlation, FA etc) and eventually living with the yield overkill. With complexities in semiconductor design and manufacturing ever increasing (faster designs in small process nodes with increasing quality requirements) solving such real time low level problems is going to be critical for companies to maintain their profitability. The EDA industry has come a long way in abstracting advance fault models - however, the EDA industry needs to go further and address the fine subtleties of design/test/process interactions ensuring rightful balance between cost and quality.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"77 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88559274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035313
M. Swaminathan
Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding of components into the package substrate and stacking of ICs and packages using wirebond and package on package (POP) technologies. This has led to the development of technologies that can lead to the miniaturization of electronic systems with coining of terms such as SIP (System in Package) and SOP (System on Package). More recently, the semiconductor industry has started focusing more on 3D integration using Through Silicon Vias (TSV). This is being quoted as a revolution in the electronics industry by several leading technologists. 3D technology, an alternative solution to the scaling problems being faced by the semiconductor industry provides a 3rd dimension for connecting transistors, ICs and packages together with short interconnections, with the possibility for miniaturization, as never before. The semiconductor industry is investing heavily on TSVs as it provides opportunities for improved performance, bandwidth, lower power, reduced delay, lower cost and overall system miniaturization. However, 3D integration poses several challenges related to managing signal, power and thermal integrity - three aspects of the problem that are pristine for ensuring system performance. In addition testing such integrated and miniaturized systems can be challenging as well. In this talk, a few approaches for managing signal, power and thermal integrity are presented in the context of 3D integration along with a few approaches for test and characterization.
{"title":"Managing signal, power and thermal integrity for 3D integration","authors":"M. Swaminathan","doi":"10.1109/TEST.2014.7035313","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035313","url":null,"abstract":"Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding of components into the package substrate and stacking of ICs and packages using wirebond and package on package (POP) technologies. This has led to the development of technologies that can lead to the miniaturization of electronic systems with coining of terms such as SIP (System in Package) and SOP (System on Package). More recently, the semiconductor industry has started focusing more on 3D integration using Through Silicon Vias (TSV). This is being quoted as a revolution in the electronics industry by several leading technologists. 3D technology, an alternative solution to the scaling problems being faced by the semiconductor industry provides a 3rd dimension for connecting transistors, ICs and packages together with short interconnections, with the possibility for miniaturization, as never before. The semiconductor industry is investing heavily on TSVs as it provides opportunities for improved performance, bandwidth, lower power, reduced delay, lower cost and overall system miniaturization. However, 3D integration poses several challenges related to managing signal, power and thermal integrity - three aspects of the problem that are pristine for ensuring system performance. In addition testing such integrated and miniaturized systems can be challenging as well. In this talk, a few approaches for managing signal, power and thermal integrity are presented in the context of 3D integration along with a few approaches for test and characterization.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"59 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80283061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035289
S. Ajouri
Although there is a desire to implement Adaptive test, desire may not be enough to overcome the friction of making it happen. Issues with inconsistent data, data formats, data availability, lack of system infrastructure, antiquated methodologies, and the need to rely on outside sources and experts.
{"title":"The desire-friction ratio of Adaptive test","authors":"S. Ajouri","doi":"10.1109/TEST.2014.7035289","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035289","url":null,"abstract":"Although there is a desire to implement Adaptive test, desire may not be enough to overcome the friction of making it happen. Issues with inconsistent data, data formats, data availability, lack of system infrastructure, antiquated methodologies, and the need to rely on outside sources and experts.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"7 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78896526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035280
M. Soma
Is it possible to create analog fault models that are theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements? This presentation challenges the audience to face this question heads-on, given the variety of analog fault models in use in the past twenty years. We will review various efforts, from those relying on mapping manufacturing defects to devices and circuits to others relying on process variations, block-level parametric variations, and circuit-level specification variations. While the impediments to the development of a standard analog fault model are obvious, the procedures to create such a model have never been elucidated, always left as future work to be done later. Well, the future is now. The presentation, with audience participation, seeks to outline possible procedures to solve this problem defined in the past yet still continuing to affect current and future technologies.
{"title":"Analog fault models: Back to the future?","authors":"M. Soma","doi":"10.1109/TEST.2014.7035280","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035280","url":null,"abstract":"Is it possible to create analog fault models that are theoretically valid, experimentally verifiable, and computationally efficient to support test developments and quality improvements? This presentation challenges the audience to face this question heads-on, given the variety of analog fault models in use in the past twenty years. We will review various efforts, from those relying on mapping manufacturing defects to devices and circuits to others relying on process variations, block-level parametric variations, and circuit-level specification variations. While the impediments to the development of a standard analog fault model are obvious, the procedures to create such a model have never been elucidated, always left as future work to be done later. Well, the future is now. The presentation, with audience participation, seeks to outline possible procedures to solve this problem defined in the past yet still continuing to affect current and future technologies.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"96 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76730610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035327
A. Gattiker
Big data is now a ubiquitous part of life — both in test and in many other areas. This talk discusses some of the big problems facing us in test and looks at analogous problems outside of the test domain. It aims to both step back and abstract test-specific problems into general problems and point out similarities and contrasts between test and non-test problems. It also highlights interesting aspects of applying some test-like techniques in non-test settings such as cognitive computing.
{"title":"Big data and test","authors":"A. Gattiker","doi":"10.1109/TEST.2014.7035327","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035327","url":null,"abstract":"Big data is now a ubiquitous part of life — both in test and in many other areas. This talk discusses some of the big problems facing us in test and looks at analogous problems outside of the test domain. It aims to both step back and abstract test-specific problems into general problems and point out similarities and contrasts between test and non-test problems. It also highlights interesting aspects of applying some test-like techniques in non-test settings such as cognitive computing.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"66 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78873990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035291
M. Roos
Adaptive test is a must have to be competitive in the future, and we need better data to support it, and that data has to come from the testers. Now, could someone please tell us how to do it? Because it seems that everyone wants AT, but only a few are willing to pay extra for it.
{"title":"ATE and test equipment vendors; Hardware not software","authors":"M. Roos","doi":"10.1109/TEST.2014.7035291","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035291","url":null,"abstract":"Adaptive test is a must have to be competitive in the future, and we need better data to support it, and that data has to come from the testers. Now, could someone please tell us how to do it? Because it seems that everyone wants AT, but only a few are willing to pay extra for it.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"123 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86279139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035312
Yue Liang
As Si technology advances along with more complex fabrication process, new challenges arise during the advanced technology bring-up stage, especially due to convoluted interaction among process, device and circuit. New test structures and technology bring-up methodologies are necessary to account for process induced variation. Layout and circuit design need to be optimized to mitigate the process impact. This talk discusses these challenges and current approaches to address them.
{"title":"Yield and performance improvement through technology-design co-optimization in advanced technology nodes","authors":"Yue Liang","doi":"10.1109/TEST.2014.7035312","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035312","url":null,"abstract":"As Si technology advances along with more complex fabrication process, new challenges arise during the advanced technology bring-up stage, especially due to convoluted interaction among process, device and circuit. New test structures and technology bring-up methodologies are necessary to account for process induced variation. Layout and circuit design need to be optimized to mitigate the process impact. This talk discusses these challenges and current approaches to address them.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"98 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83588110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035288
Carl Bowen
Adaptive test seems a logical solution to address the challenge of increasing IP complexity and shrinking test time budgets. Might slow adoption be a consequence of the Engineering community focus on technical implementation methods, at the expense of addressing the emotional concerns of the Quality and Supply Chain community?
{"title":"Concerns over predictability of supply and quality","authors":"Carl Bowen","doi":"10.1109/TEST.2014.7035288","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035288","url":null,"abstract":"Adaptive test seems a logical solution to address the challenge of increasing IP complexity and shrinking test time budgets. Might slow adoption be a consequence of the Engineering community focus on technical implementation methods, at the expense of addressing the emotional concerns of the Quality and Supply Chain community?","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"18 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74388170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/TEST.2014.7035285
Mani Vadari
Of late, microgrids are getting a lot of attention, not just to support national security at military bases, but also to provide more resilient power supplies at other types of facilities, to allow for increased penetration of renewables, and other reasons. College campuses, military bases, and even corporate campuses are exploring microgrid options. This has spurred creation of new technologies and control mechanisms that allow these systems to operate in a grid-connected mode and also independently for extended periods of time. In this presentation, we propose a radical new concept: a top-down breakup of the distribution grid into an interconnected set of microgrids. Such an architecture would dramatically change how utilities address storm response while also delivering utilities' other mandates. We call this the “dynamic microgrid”, a new concept that will move the microgrid from its present niche to a mainstream position. Dynamic microgrids have the potential to be a key element of the ultimate self-healing grid - the Holy Grail of the smart grid. They'd allow the grid to divide itself into smaller self-sustaining grids, which can then be stitched back to form the regular distribution grid.
{"title":"Dynamic microgrids - A potential solution for enhanced resiliency in distribution systems","authors":"Mani Vadari","doi":"10.1109/TEST.2014.7035285","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035285","url":null,"abstract":"Of late, microgrids are getting a lot of attention, not just to support national security at military bases, but also to provide more resilient power supplies at other types of facilities, to allow for increased penetration of renewables, and other reasons. College campuses, military bases, and even corporate campuses are exploring microgrid options. This has spurred creation of new technologies and control mechanisms that allow these systems to operate in a grid-connected mode and also independently for extended periods of time. In this presentation, we propose a radical new concept: a top-down breakup of the distribution grid into an interconnected set of microgrids. Such an architecture would dramatically change how utilities address storm response while also delivering utilities' other mandates. We call this the “dynamic microgrid”, a new concept that will move the microgrid from its present niche to a mainstream position. Dynamic microgrids have the potential to be a key element of the ultimate self-healing grid - the Holy Grail of the smart grid. They'd allow the grid to divide itself into smaller self-sustaining grids, which can then be stitched back to form the regular distribution grid.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"1 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84068214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-01-01DOI: 10.1109/TEST.2014.7035364
Julio Vazquez Hernandez
{"title":"Error prediction and detection methodologies for reliable circuit operation under NBTI","authors":"Julio Vazquez Hernandez","doi":"10.1109/TEST.2014.7035364","DOIUrl":"https://doi.org/10.1109/TEST.2014.7035364","url":null,"abstract":"","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"71 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2014-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81732550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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