The cost of maintaining current levels of hardware reliability appears to be un-affordable in the post-22 nm late CMOS design era. In the first part of this talk, we will examine the reasons behind such a projection, based on the modeled trends in technology, circuits and microarchitecture. Then, in the second part, we will present a vision of cross-layer resilience optimization, which forms the basis of an IBM-led project sponsored by DARPA under its PERFECT program. The goal is to demonstrate through parameterized, cross-layer modeling that such an approach can help provide cost- and energy-efficient resilience in a class of future embedded systems of interest to DARPA, U.S. Department of Defense and also to the general IT appliance industry. The modeling framework is targeted to be flexible enough that customized trade-off analyses are expected to be of value to other R&D efforts geared toward high-end server, mainframe, cloud and large-scale supercomputing market segments as well.
{"title":"Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges","authors":"P. Bose","doi":"10.1109/TEST.2013.6651873","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651873","url":null,"abstract":"The cost of maintaining current levels of hardware reliability appears to be un-affordable in the post-22 nm late CMOS design era. In the first part of this talk, we will examine the reasons behind such a projection, based on the modeled trends in technology, circuits and microarchitecture. Then, in the second part, we will present a vision of cross-layer resilience optimization, which forms the basis of an IBM-led project sponsored by DARPA under its PERFECT program. The goal is to demonstrate through parameterized, cross-layer modeling that such an approach can help provide cost- and energy-efficient resilience in a class of future embedded systems of interest to DARPA, U.S. Department of Defense and also to the general IT appliance industry. The modeling framework is targeted to be flexible enough that customized trade-off analyses are expected to be of value to other R&D efforts geared toward high-end server, mainframe, cloud and large-scale supercomputing market segments as well.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"27 1","pages":"10"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87609961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The requirements for the recent mobile devices are significantly different from those for the conventional PC-oriented devices in many aspects: power consumption, performance and production ramp-up speed. These unique requirements have created many challenges in process technology, design, and manufacturing. Mobile devices are battery-sensitive, but still need the horsepower to run performance-hungry applications. We need a very tight DTCO (Design and Technology Co-Optimization), and a steep production ramp with high yield. Samsung Electronics has been focusing on the development and manufacturing of mobile devices for many years. The unique challenges associated with mobile devices will be addressed in the talk, along with our experience in overcoming them.
{"title":"Keynote address tuesday: Challenges in mobile devices: Process, design and manufacturing","authors":"Kwang-Hyun Kim","doi":"10.1109/TEST.2013.6651871","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651871","url":null,"abstract":"The requirements for the recent mobile devices are significantly different from those for the conventional PC-oriented devices in many aspects: power consumption, performance and production ramp-up speed. These unique requirements have created many challenges in process technology, design, and manufacturing. Mobile devices are battery-sensitive, but still need the horsepower to run performance-hungry applications. We need a very tight DTCO (Design and Technology Co-Optimization), and a steep production ramp with high yield. Samsung Electronics has been focusing on the development and manufacturing of mobile devices for many years. The unique challenges associated with mobile devices will be addressed in the talk, along with our experience in overcoming them.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"1 1","pages":"8"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87302066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Intel architecture scales from Exa-scale computing to hand-held and deeply embedded devices. A consistent architecture spanning many product domains brings benefits to silicon and product developers. But it also creates a validation challenge that is nonlinear in nature due to the differences in product complexity, use cases, and user expectations. In this talk, John will address how Intel views the reliability/resilience of large scale systems, how we test for user experience that might help users decide what is good for them, how we attempt to balance all the conflicting validation requirements in today's rapidly evolving landscape spanning consumption devices with short life spans to enterprise applications with very high uptime and reliability expectations. In addition, he will comment on the developments in formal methods and their applicability to large-scale commercial validation/verification efforts.
{"title":"Keynote address wednesday: Compute continuum and the nonlinear validation challenge","authors":"John D. Barton","doi":"10.1109/TEST.2013.6651872","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651872","url":null,"abstract":"Summary form only given. Intel architecture scales from Exa-scale computing to hand-held and deeply embedded devices. A consistent architecture spanning many product domains brings benefits to silicon and product developers. But it also creates a validation challenge that is nonlinear in nature due to the differences in product complexity, use cases, and user expectations. In this talk, John will address how Intel views the reliability/resilience of large scale systems, how we test for user experience that might help users decide what is good for them, how we attempt to balance all the conflicting validation requirements in today's rapidly evolving landscape spanning consumption devices with short life spans to enterprise applications with very high uptime and reliability expectations. In addition, he will comment on the developments in formal methods and their applicability to large-scale commercial validation/verification efforts.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"68 1","pages":"9"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83868709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Best paper award winners","authors":"Z. Yu, D. Chen","doi":"10.1109/TEST.2013.6651867","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651867","url":null,"abstract":"","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"222 1","pages":"4"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85550943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Welcome message","authors":"G. W. Roberts, R. Aitken","doi":"10.1109/TEST.2013.6651865","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651865","url":null,"abstract":"","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"6 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85877609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This panel discusses entrepreneurship in the ATE industry. The ATE industry needs breakthrough innovations in order to continue to scale down the cost of test in the presence of ever increasing technology challenges.
{"title":"Test/ATE vision 2020 - Entrepreneurship in test CEO panel","authors":"K. Lanier","doi":"10.1109/TEST.2012.6401525","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401525","url":null,"abstract":"This panel discusses entrepreneurship in the ATE industry. The ATE industry needs breakthrough innovations in order to continue to scale down the cost of test in the presence of ever increasing technology challenges.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"26 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75528981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it's own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.
{"title":"\"Managing process variance in analog designs\"","authors":"E. Atwood","doi":"10.1109/TEST.2012.6401527","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401527","url":null,"abstract":"Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it's own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"6 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79989298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The fast growing mobile market has led to a demand for low power ICs, in order to extend battery life and keep a phone from literally burning a hole in the user's pocket. The microprocessor and high-end System on a Chip field both have a demand for faster ICs. But this is not enough. Mobile devices want to be faster, and high-end devices want to be cooler, if possible. Designers have to be able to tradeoff these conflicting goals to produce products fast enough and cool enough (in both senses of that word) for the marketplace. DFT and test engineers have to deal with this new environment. They have to be able to determine if a particular part hits its speed goals. They have to be able to handle the problems arising from large amounts of switching. For low power parts they have to make sure that scan and BIST do not draw more power than the part can handle, and work around circuitry that turns off parts of the design not in use. Test EDA suppliers have to figure out ways of making their tools work for both high speed and low power designs, and how to help their customers make these nearly impossible tradeoffs. This panel explores these problems and their impact on EDA tools. Three test experts from the design world will answer questions on how they deal with the problems of low power and high speed designs posed by the moderator. Then two panelists from the test EDA sector will suggest how their tools can help — or admit that their tools need more work in that area. Then the discussion will be opened to the audience to allow them to give their solutions to these problems or to pose still tougher problems for us to solve.
{"title":"Testing high-frequency and low-power designs: Do the standard rules and tools apply?","authors":"S. Davidson","doi":"10.1109/TEST.2012.6401529","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401529","url":null,"abstract":"The fast growing mobile market has led to a demand for low power ICs, in order to extend battery life and keep a phone from literally burning a hole in the user's pocket. The microprocessor and high-end System on a Chip field both have a demand for faster ICs. But this is not enough. Mobile devices want to be faster, and high-end devices want to be cooler, if possible. Designers have to be able to tradeoff these conflicting goals to produce products fast enough and cool enough (in both senses of that word) for the marketplace. DFT and test engineers have to deal with this new environment. They have to be able to determine if a particular part hits its speed goals. They have to be able to handle the problems arising from large amounts of switching. For low power parts they have to make sure that scan and BIST do not draw more power than the part can handle, and work around circuitry that turns off parts of the design not in use. Test EDA suppliers have to figure out ways of making their tools work for both high speed and low power designs, and how to help their customers make these nearly impossible tradeoffs. This panel explores these problems and their impact on EDA tools. Three test experts from the design world will answer questions on how they deal with the problems of low power and high speed designs posed by the moderator. Then two panelists from the test EDA sector will suggest how their tools can help — or admit that their tools need more work in that area. Then the discussion will be opened to the audience to allow them to give their solutions to these problems or to pose still tougher problems for us to solve.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"19 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86702114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the erosion of printed circuit board test points, a shift to high density interconnect (HDI) and continuing requirements that involve signal integrity verification of high-speed routes, board test is becoming much more complex. Assistance from embedded instruments in the ICs at board level test and multi-vendor embedded instrument access and solutions are becoming critical. In particular, to verify the board runs at-speed and to compensate for the loss of structural test capability, built-in IC-to-IC tests using embedded instruments will become a must. Many ICs already use these instruments for IC level testing, however their function needs to be extended for re-use at board-level test. However, a potential roadblock to this is that IC providers frequently make these instruments proprietary, often with custom functions and access. Can agreement be reached on providing "standardized functions and open access", that can be transferred by "standardized documentation" from the IC design community to manufacturing board test? This requires IC design, IC test, and board design and test engineers to work closely together to agree on the function and features of the test instruments. The board engineers know they need something, but possibly do not know what is available or they address the IC design requirements too late in the game! The objectives of the panel are as follows: — To increase awareness of the IC design and test communities that assistance from embedded instruments in ICs and multi-vendor embedded instrument access and solutions are critical to the future success of board test. — Discuss the industry acceptance to re-use applicable IC instruments at board level test, as well as argue the potential pros and cons of open instrument access. — Provide opinions on designing standardized instruments in ICs, with the intent of passing the information on to customers, as well as adding board design and manufacturing test requirements to IC design, test, verification and characterization.
{"title":"Are the IC guys helping or hindering board test?","authors":"Z. Conroy","doi":"10.1109/TEST.2012.6401530","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401530","url":null,"abstract":"With the erosion of printed circuit board test points, a shift to high density interconnect (HDI) and continuing requirements that involve signal integrity verification of high-speed routes, board test is becoming much more complex. Assistance from embedded instruments in the ICs at board level test and multi-vendor embedded instrument access and solutions are becoming critical. In particular, to verify the board runs at-speed and to compensate for the loss of structural test capability, built-in IC-to-IC tests using embedded instruments will become a must. Many ICs already use these instruments for IC level testing, however their function needs to be extended for re-use at board-level test. However, a potential roadblock to this is that IC providers frequently make these instruments proprietary, often with custom functions and access. Can agreement be reached on providing \"standardized functions and open access\", that can be transferred by \"standardized documentation\" from the IC design community to manufacturing board test? This requires IC design, IC test, and board design and test engineers to work closely together to agree on the function and features of the test instruments. The board engineers know they need something, but possibly do not know what is available or they address the IC design requirements too late in the game! The objectives of the panel are as follows: — To increase awareness of the IC design and test communities that assistance from embedded instruments in ICs and multi-vendor embedded instrument access and solutions are critical to the future success of board test. — Discuss the industry acceptance to re-use applicable IC instruments at board level test, as well as argue the potential pros and cons of open instrument access. — Provide opinions on designing standardized instruments in ICs, with the intent of passing the information on to customers, as well as adding board design and manufacturing test requirements to IC design, test, verification and characterization.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"41 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73845987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Is there any real industrial test problem that requires research collaboration, or is there no such thing? We will hear from both industrial and research folks about their experiences, both successful and otherwise. How do we get past statements like these and move on to genuine and effective collaboration? █ Industry: You have to make it truly work for us … █ Research: You have to fund my students first … and give us your designs █ Industry: bye !! … █ Research: So we still have no industrial test bench, … and funding : Following this panel session, there will be an invited poster session from both industry and research demonstrating their problems, technologies and their willingness to look for cooperation. Visit these posters and tell them either you solved their problem 10 years ago, or ask for a check to solve them.…
{"title":"Are industrial test problems real problems? I thought research has resolved them all!","authors":"Xinli Gu","doi":"10.1109/TEST.2012.6401526","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401526","url":null,"abstract":"Is there any real industrial test problem that requires research collaboration, or is there no such thing? We will hear from both industrial and research folks about their experiences, both successful and otherwise. How do we get past statements like these and move on to genuine and effective collaboration? █ Industry: You have to make it truly work for us … █ Research: You have to fund my students first … and give us your designs █ Industry: bye !! … █ Research: So we still have no industrial test bench, … and funding : Following this panel session, there will be an invited poster session from both industry and research demonstrating their problems, technologies and their willingness to look for cooperation. Visit these posters and tell them either you solved their problem 10 years ago, or ask for a check to solve them.…","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"46 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80599907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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