Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437631
C. Lisbôa, F. Kastensmidt, E. H. Neto, G. Wirth, L. Carro
Transients spanning more than one clock cycle will challenge soft error tolerant designs for future technologies. To face this problem, a low overhead technique that uses bulk built-in current sensors and recomputation is proposed here.
{"title":"Using built-in sensors to cope with long duration transient faults in future technologies","authors":"C. Lisbôa, F. Kastensmidt, E. H. Neto, G. Wirth, L. Carro","doi":"10.1109/TEST.2007.4437631","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437631","url":null,"abstract":"Transients spanning more than one clock cycle will challenge soft error tolerant designs for future technologies. To face this problem, a low overhead technique that uses bulk built-in current sensors and recomputation is proposed here.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"1 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80920021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437596
V. Devanathan, C. Ravikumar, V. Kamakoti
Process variation is an increasingly dominant phenomenon affecting both power and performance in sub-100 nm technologies. Cost considerations often do not permit over-designing the power supply infrastructure for test mode, considering the worst-case scenario. Test application must not over-exercise the power supply grids, lest the tests will damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. We argue that false delay test failures can be avoided by generating "safe" patterns that are tolerant to on-chip variations. A statistical framework for power-safe pattern generation is proposed, which uses process variation information, power grid topology and regional constraints on switching activity. Experimental results are provided on benchmark circuits to demonstrate the effectiveness of the framework.
{"title":"A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test","authors":"V. Devanathan, C. Ravikumar, V. Kamakoti","doi":"10.1109/TEST.2007.4437596","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437596","url":null,"abstract":"Process variation is an increasingly dominant phenomenon affecting both power and performance in sub-100 nm technologies. Cost considerations often do not permit over-designing the power supply infrastructure for test mode, considering the worst-case scenario. Test application must not over-exercise the power supply grids, lest the tests will damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. We argue that false delay test failures can be avoided by generating \"safe\" patterns that are tolerant to on-chip variations. A statistical framework for power-safe pattern generation is proposed, which uses process variation information, power grid topology and regional constraints on switching activity. Experimental results are provided on benchmark circuits to demonstrate the effectiveness of the framework.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"20 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88579540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437601
Tee Chwee Liong, Andy Pascual
QFN is increasingly being used on wireless cards, handhelds etc. However, QFN unique solder joints pose great challenges for AXI. This paper discusses lack of industry specification for QFN inspection, how AXI methodology was improved to detect QFN solder joint defect, design for inspection and future work.
{"title":"Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI)","authors":"Tee Chwee Liong, Andy Pascual","doi":"10.1109/TEST.2007.4437601","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437601","url":null,"abstract":"QFN is increasingly being used on wireless cards, handhelds etc. However, QFN unique solder joints pose great challenges for AXI. This paper discusses lack of industry specification for QFN inspection, how AXI methodology was improved to detect QFN solder joint defect, design for inspection and future work.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"35 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90983500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437647
I. Pomeranz, S. Reddy
An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with n drops below a certain level. We introduce three parameters of an n-detection test set to measure saturation of the test generation process: (1) the fraction of faults detected n times or less by the test set, (2) the fraction of faults detected fewer than n times by the test set, and (3) the test set size relative to the size of a one-detection test set. We demonstrate that the behavior of each one of these parameters follows a unique pattern as n is increased, and certain features of this behavior can be used to identify saturation. All the parameters are easy to compute during the test generation process.
{"title":"On the saturation of n-detection test sets with increased n","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/TEST.2007.4437647","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437647","url":null,"abstract":"An n-detection test set contains n different tests for each target fault. The value of n is typically determined based on test set size constraints, and certain values have become standard. In this work we investigate appropriate values for n by considering the saturation of the n-detection test generation process. As n is increased, eventually the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with n drops below a certain level. We introduce three parameters of an n-detection test set to measure saturation of the test generation process: (1) the fraction of faults detected n times or less by the test set, (2) the fraction of faults detected fewer than n times by the test set, and (3) the test set size relative to the size of a one-detection test set. We demonstrate that the behavior of each one of these parameters follows a unique pattern as n is increased, and certain features of this behavior can be used to identify saturation. All the parameters are easy to compute during the test generation process.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"11 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76747916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437562
Anuja Sehgal, J. Fitzgerald, J. Rearick
The application of SOC-style test partitioning to a monolithic microprocessor design results in considerable benefits, including simpler and faster ATPG, reduced ECO impact, faster debug, and, most surprisingly, reduced test application time. These results challenge the orthodoxy that flat, top-level ATPG is the best method to produce an optimal pattern set. The granularity of the partitioning was the key factor in achieving the results: a 33-element partition of the AMDtrade Athlon CPU chip resulted in better than a ~80% reduction in test time compared to aflat model of the entire chip. This paper describes the ATPG experiments and quantifies the design overhead required for implementing wrapper cells at partition boundaries.
{"title":"Test cost reduction for the AMD™ Athlon processor using test partitioning","authors":"Anuja Sehgal, J. Fitzgerald, J. Rearick","doi":"10.1109/TEST.2007.4437562","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437562","url":null,"abstract":"The application of SOC-style test partitioning to a monolithic microprocessor design results in considerable benefits, including simpler and faster ATPG, reduced ECO impact, faster debug, and, most surprisingly, reduced test application time. These results challenge the orthodoxy that flat, top-level ATPG is the best method to produce an optimal pattern set. The granularity of the partitioning was the key factor in achieving the results: a 33-element partition of the AMDtrade Athlon CPU chip resulted in better than a ~80% reduction in test time compared to aflat model of the entire chip. This paper describes the ATPG experiments and quantifies the design overhead required for implementing wrapper cells at partition boundaries.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"33 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75068892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437655
Hanqing Xing, Hanjun Jiang, Degang Chen, R. Geiger
Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. On-chip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to plusmn0.2 LSB accuracy level using only 7-bit linear DACs.
{"title":"A fully digital-compatible BIST strategy for ADC linearity testing","authors":"Hanqing Xing, Hanjun Jiang, Degang Chen, R. Geiger","doi":"10.1109/TEST.2007.4437655","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437655","url":null,"abstract":"Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. On-chip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to plusmn0.2 LSB accuracy level using only 7-bit linear DACs.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"8 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74389359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437595
B. Moore, C. Sellathamby, P. Cauvet, H. Fleury, M. Paulson, M. Reja, Lin Fu, B. Bai, E. Reid, I. Filanovsky, Steven Slupsky
A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.
{"title":"High throughput non-contact SiP testing","authors":"B. Moore, C. Sellathamby, P. Cauvet, H. Fleury, M. Paulson, M. Reja, Lin Fu, B. Bai, E. Reid, I. Filanovsky, Steven Slupsky","doi":"10.1109/TEST.2007.4437595","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437595","url":null,"abstract":"A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"22 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81684030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437586
F. Frederick, T. McLaurin
The ability to apply a slow shift clock and an at-speed capture or functional clock is required to keep the average power down during test. A clock control macro (CCM) that can be attached to a PLL has been designed to meet the functional and structural test clocking needs of the Cortextrade-A8 microprocessor core. This includes a glitchless multiplexer, the ability to control separate clocks in isolation and the ability to switch between the reference clock and the PLL VCO clock. This clock control macro is different from previous ARM CCMs in that it has extra capability and it was coded to be synthesizable for reuse.
{"title":"Design for test features of the ARM clock control macro","authors":"F. Frederick, T. McLaurin","doi":"10.1109/TEST.2007.4437586","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437586","url":null,"abstract":"The ability to apply a slow shift clock and an at-speed capture or functional clock is required to keep the average power down during test. A clock control macro (CCM) that can be attached to a PLL has been designed to meet the functional and structural test clocking needs of the Cortextrade-A8 microprocessor core. This includes a glitchless multiplexer, the ability to control separate clocks in isolation and the ability to switch between the reference clock and the PLL VCO clock. This clock control macro is different from previous ARM CCMs in that it has extra capability and it was coded to be synthesizable for reuse.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"112 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85463422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437648
Gaurav Bhargava, Dale Meehl, J. Sage
Multi-capture-clock scan patterns for the traditional stuck-at-fault model have been used to reduce down pattern counts while still maintaining high test coverage. This paper studies how the same test patterns provide a decent N-detect fault coverage.
{"title":"Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns","authors":"Gaurav Bhargava, Dale Meehl, J. Sage","doi":"10.1109/TEST.2007.4437648","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437648","url":null,"abstract":"Multi-capture-clock scan patterns for the traditional stuck-at-fault model have been used to reduce down pattern counts while still maintaining high test coverage. This paper studies how the same test patterns provide a decent N-detect fault coverage.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"24 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80986852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/TEST.2007.4437602
O. Poku, R. D. Blanton
An objective of delay fault diagnosis is to enable characterization of the source and nature of timing failure in an integrated circuit. However, the most commonly studied defect models (the gate-delay and path-delay fault models) do not adequately capture the complex timing characteristics that a delay fault can exhibit. In this work, we present a novel diagnostic technique that is used to extract an accurate delay fault model we call a segment network fault without the need for any timing information. In our simulation-based experiments, we successfully diagnose delay faults of varying complexity demonstrating the usefulness of the new delay fault model for the purposes of delay defect characterization.
{"title":"Delay defect diagnosis using segment network faults","authors":"O. Poku, R. D. Blanton","doi":"10.1109/TEST.2007.4437602","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437602","url":null,"abstract":"An objective of delay fault diagnosis is to enable characterization of the source and nature of timing failure in an integrated circuit. However, the most commonly studied defect models (the gate-delay and path-delay fault models) do not adequately capture the complex timing characteristics that a delay fault can exhibit. In this work, we present a novel diagnostic technique that is used to extract an accurate delay fault model we call a segment network fault without the need for any timing information. In our simulation-based experiments, we successfully diagnose delay faults of varying complexity demonstrating the usefulness of the new delay fault model for the purposes of delay defect characterization.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"1 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89511243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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