Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810685
Junhyung Um, Taewhan Kim, C. Liu
Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs. Specifically, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. In addition, we extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically, and this can be done within the context of a standard HDL synthesis environment.
{"title":"Optimal allocation of carry-save-adders in arithmetic optimization","authors":"Junhyung Um, Taewhan Kim, C. Liu","doi":"10.1109/ICCAD.1999.810685","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810685","url":null,"abstract":"Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs. Specifically, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. In addition, we extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically, and this can be done within the context of a standard HDL synthesis environment.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"5 1","pages":"410-413"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75669308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810672
G. Qu, M. Potkonjak
Design systems to provide various quality of service (QoS) guarantees have received a lot of attention due to the increasing popularity of real-time multimedia and wireless communication applications. Meanwhile, low power consumption is always one of the goals for system design, especially for battery-operated systems. With the design trend of integrating multiple processor cores and memory on a single chip, we address the problem of how to partition a set of applications among processors, such that all the individual QoS requirements are met and the total energy consumption is minimized. We exploit the advantages provided by the variable voltage design methodology to choose the voltage for each application on the same processor optimally for this purpose. We also discuss how to partition applications among the processors to achieve the same goal. We formulate the problem on an abstract QoS model and present how to allocate resources (e.g., CPU time) and determine the voltage profile for every single processor. Experiments on media benchmarks have also been studied.
{"title":"Power minimization using system-level partitioning of applications with quality of service requirements","authors":"G. Qu, M. Potkonjak","doi":"10.1109/ICCAD.1999.810672","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810672","url":null,"abstract":"Design systems to provide various quality of service (QoS) guarantees have received a lot of attention due to the increasing popularity of real-time multimedia and wireless communication applications. Meanwhile, low power consumption is always one of the goals for system design, especially for battery-operated systems. With the design trend of integrating multiple processor cores and memory on a single chip, we address the problem of how to partition a set of applications among processors, such that all the individual QoS requirements are met and the total energy consumption is minimized. We exploit the advantages provided by the variable voltage design methodology to choose the voltage for each application on the same processor optimally for this purpose. We also discuss how to partition applications among the processors to achieve the same goal. We formulate the problem on an abstract QoS model and present how to allocate resources (e.g., CPU time) and determine the voltage profile for every single processor. Experiments on media benchmarks have also been studied.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"315 1","pages":"343-346"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77624909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Function inlining is a compiler optimization that generally increases performance at the expense of larger code size. However, current inlining techniques do not meet the special demands in the design of embedded systems, since they are based on simple heuristics, and they generate code of unpredictable size. This paper presents a novel approach to function inlining in C compilers for embedded processors, which aims at maximum program speedup under a global limit on code size. The core of this approach is a branch-and-bound algorithm which allows one to quickly explore the large search space. In an application study, we show how this algorithm can be applied to maximize the execution speed of an application under a given code size constraint.
{"title":"Function inlining under code size constraints for embedded processors","authors":"R. Leupers, P. Marwedel","doi":"10.5555/339492.340022","DOIUrl":"https://doi.org/10.5555/339492.340022","url":null,"abstract":"Function inlining is a compiler optimization that generally increases performance at the expense of larger code size. However, current inlining techniques do not meet the special demands in the design of embedded systems, since they are based on simple heuristics, and they generate code of unpredictable size. This paper presents a novel approach to function inlining in C compilers for embedded processors, which aims at maximum program speedup under a global limit on code size. The core of this approach is a branch-and-bound algorithm which allows one to quickly explore the large search space. In an application study, we show how this algorithm can be applied to maximize the execution speed of an application under a given code size constraint.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"20 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75531446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810700
T. Henzinger, Xiaojun Liu, S. Qadeer, S. Rajamani
We describe the formal specification and verification of the VGI parallel DSP chip (V. Srini et al., 1998), which contains 64 compute processors with /spl sim/30 K gates in each processor. Our effort coincided with the "informal" verification stage of the chip. By interacting with the designers, we produced an abstract but executable specification of the design which embodies the programmer's view of the system. Given the size of the design, an automatic check that even one of the 64 processors satisfies its specification is well beyond the scope of current verification tools. However, the check can be decomposed using assume-guarantee reasoning. For VGI, the implementation and specification operate at different time scales: several steps of the implementation correspond to a single step in the specification. We generalized both the assume-guarantee method and our model checker MOCHA to allow compositional verification for such applications. We used our proof rule to decompose the verification problem of the VGI chip into smaller proof obligations that were discharged automatically by MOCHA. Using our formal approach, we uncovered and fixed subtle bugs that were unknown to the designers.
{"title":"Formal specification and verification of a dataflow processor array","authors":"T. Henzinger, Xiaojun Liu, S. Qadeer, S. Rajamani","doi":"10.1109/ICCAD.1999.810700","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810700","url":null,"abstract":"We describe the formal specification and verification of the VGI parallel DSP chip (V. Srini et al., 1998), which contains 64 compute processors with /spl sim/30 K gates in each processor. Our effort coincided with the \"informal\" verification stage of the chip. By interacting with the designers, we produced an abstract but executable specification of the design which embodies the programmer's view of the system. Given the size of the design, an automatic check that even one of the 64 processors satisfies its specification is well beyond the scope of current verification tools. However, the check can be decomposed using assume-guarantee reasoning. For VGI, the implementation and specification operate at different time scales: several steps of the implementation correspond to a single step in the specification. We generalized both the assume-guarantee method and our model checker MOCHA to allow compositional verification for such applications. We used our proof rule to decompose the verification problem of the VGI chip into smaller proof obligations that were discharged automatically by MOCHA. Using our formal approach, we uncovered and fixed subtle bugs that were unknown to the designers.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"136 1","pages":"494-499"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77941895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810679
Jing-Rebecca Li, Jacob K. White
Krylov-subspace based methods for generating low-order models of complicated interconnect are extremely effective, but there is no optimality theory for the resulting models. Alternatively, methods based on truncating a balanced realization (TBR), in which the observability and controllability gramians have been diagonalized, do have an optimality property but are too computationally expensive to use on complicated problems. In this paper we present a method for computing reduced-order models of interconnect by projection via the orthogonalized union of the approximate dominant eigenspaces of the system's controllability and observability gramians. The approximate dominant eigenspaces are obtained efficiently using an iterative Lyapunov equation solver, Vector ADI, which requires only linear matrix-vector solves. A spiral inductor and a transmission line example are used to demonstrate that the new method accurately approximates the TBR results and gives much more accurate wideband models than Krylov subspace-based moment matching methods.
{"title":"Efficient model reduction of interconnect via approximate system gramians","authors":"Jing-Rebecca Li, Jacob K. White","doi":"10.1109/ICCAD.1999.810679","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810679","url":null,"abstract":"Krylov-subspace based methods for generating low-order models of complicated interconnect are extremely effective, but there is no optimality theory for the resulting models. Alternatively, methods based on truncating a balanced realization (TBR), in which the observability and controllability gramians have been diagonalized, do have an optimality property but are too computationally expensive to use on complicated problems. In this paper we present a method for computing reduced-order models of interconnect by projection via the orthogonalized union of the approximate dominant eigenspaces of the system's controllability and observability gramians. The approximate dominant eigenspaces are obtained efficiently using an iterative Lyapunov equation solver, Vector ADI, which requires only linear matrix-vector solves. A spiral inductor and a transmission line example are used to demonstrate that the new method accurately approximates the TBR results and gives much more accurate wideband models than Krylov subspace-based moment matching methods.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"74 1","pages":"380-383"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88569638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810715
Jun Yuan, Kurt Shultz, C. Pixley, H. Miller, A. Aziz
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulation to a legal input space, while input biasing, which can be considered as a probabilistic constraint, makes it easier to cover interesting "corner" cases. In this paper, we propose to use constraints and biasing to form a simulation environment instead of using an explicit testbench in hierarchical functional verification. Both constraints and input biasing can depend on the state of the design and thus are very expressive in modeling the environment. We present a novel method that unifies the handling of constraints and biasing via the use of Binary Decision Diagrams (BDDs). The distribution of input vectors under the effect of constraints and input biasing are determined by what we refer to as the constrained probabilities. A BDD representing the constraints is first built, then an algorithm is applied to bias the branching probabilities in the BDD. During simulation, this annotated BDD is used to generate input vectors whose distribution matches their predetermined constrained probabilities. The simulation generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe a partitioning method to minimize the size of BDDs used in simulation generation. Our techniques were used in the verification of a set of commercial designs; experimental results demonstrated their effectiveness.
{"title":"Modeling design constraints and biasing in simulation using BDDs","authors":"Jun Yuan, Kurt Shultz, C. Pixley, H. Miller, A. Aziz","doi":"10.1109/ICCAD.1999.810715","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810715","url":null,"abstract":"Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulation to a legal input space, while input biasing, which can be considered as a probabilistic constraint, makes it easier to cover interesting \"corner\" cases. In this paper, we propose to use constraints and biasing to form a simulation environment instead of using an explicit testbench in hierarchical functional verification. Both constraints and input biasing can depend on the state of the design and thus are very expressive in modeling the environment. We present a novel method that unifies the handling of constraints and biasing via the use of Binary Decision Diagrams (BDDs). The distribution of input vectors under the effect of constraints and input biasing are determined by what we refer to as the constrained probabilities. A BDD representing the constraints is first built, then an algorithm is applied to bias the branching probabilities in the BDD. During simulation, this annotated BDD is used to generate input vectors whose distribution matches their predetermined constrained probabilities. The simulation generation is a one-pass process, i.e., no backtracking or retry is needed. Also, we describe a partitioning method to minimize the size of BDDs used in simulation generation. Our techniques were used in the verification of a set of commercial designs; experimental results demonstrated their effectiveness.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"50 1","pages":"584-589"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91278363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810695
B. Vinnakota
Advances in technology and increasing integration are expected to degrade the effectiveness of I/sub ddq/ test. Total leakage currents per IC are expected to be very large, making it difficult to detect the impact of a single defect (T.W. Williams et al., 1996; M. Sachdev, 1997). Test methods which detect faults by monitoring the dynamic supply current have been suggested as one alternative. Almost all the dynamic current techniques proposed in the literature are adversely affected by the impact of process variations. Many are also susceptible to timing and magnitude errors in measurement. The energy consumption ratio (ECR) is a new dynamic current-based test metric (B. Vinnakota et al., 1998), that addresses some of these problems. ECR-based test offers several advantages over other dynamic test methods and the I/sub ddq/ test such as tolerance to process variations, reduced test process complexity and a proven ability to detect faults that escape other techniques. The ECR has been validated through extensive simulation and through application to a 50K gate sub-micron biomedical IC (W. Jiang and B. Vinnakota, 1999). Our contributions are directed towards further validating the real quality of the ECR.
{"title":"Deep submicron defect detection with the energy consumption ratio","authors":"B. Vinnakota","doi":"10.1109/ICCAD.1999.810695","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810695","url":null,"abstract":"Advances in technology and increasing integration are expected to degrade the effectiveness of I/sub ddq/ test. Total leakage currents per IC are expected to be very large, making it difficult to detect the impact of a single defect (T.W. Williams et al., 1996; M. Sachdev, 1997). Test methods which detect faults by monitoring the dynamic supply current have been suggested as one alternative. Almost all the dynamic current techniques proposed in the literature are adversely affected by the impact of process variations. Many are also susceptible to timing and magnitude errors in measurement. The energy consumption ratio (ECR) is a new dynamic current-based test metric (B. Vinnakota et al., 1998), that addresses some of these problems. ECR-based test offers several advantages over other dynamic test methods and the I/sub ddq/ test such as tolerance to process variations, reduced test process complexity and a proven ability to detect faults that escape other techniques. The ECR has been validated through extensive simulation and through application to a 50K gate sub-micron biomedical IC (W. Jiang and B. Vinnakota, 1999). Our contributions are directed towards further validating the real quality of the ECR.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"103 1","pages":"467-470"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90746583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810630
Yanbin Jiang, S. Sapatnekar
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state-space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.
{"title":"An integrated algorithm for combined placement and libraryless technology mapping","authors":"Yanbin Jiang, S. Sapatnekar","doi":"10.1109/ICCAD.1999.810630","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810630","url":null,"abstract":"This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state-space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"7 1","pages":"102-105"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91263796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810666
A. Gomes, A. Chatterjee
We propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.
{"title":"Robust optimization based backtrace method for analog circuits","authors":"A. Gomes, A. Chatterjee","doi":"10.1109/ICCAD.1999.810666","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810666","url":null,"abstract":"We propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"15 1","pages":"304-307"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87575898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810655
I. Kourtev, E. Friedman
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic programming (QP) problem is introduced. The concept of a permissible range, or a valid interval, for the clock skew of each local data path is key to this QP approach. From a reliability perspective, the ideal clock schedule corresponds to each clock skew within the circuit being at the center of the respective permissible range. However, this ideal clock schedule is nor practically implementable because of limitations imposed by the connectivity among the registers within the circuit. To evaluate the reliability, a quadratic cost function is introduced as the Euclidean distance between the ideal schedule and a given practically feasible clock schedule. This cost function is the minimization objective of the described algorithms for the solution of the previously mentioned quadratic program. Furthermore, the work described here substantially differs from previous research in that it permits complete control over specific clock signal delays or skews within the circuit. Specifically, the algorithms described here can be employed to obtain results with explicitly specified target values of important clock delays/skews with a circuit, such as for example, the clock delays/skews for I/O registers. An additional benefit is a potential reduction in clock period of up to 10%. An efficient mathematical algorithm is derived for the solution of the QP problem with O(r/sup 3/) run time complexity and O(r/sup 2/) storage complexity, where r is the number of registers in the circuit. The algorithm is implemented as a C++ program and demonstrated on the ISCAS'89 suite of benchmark circuits as well as on a number of industrial circuits. The work described here yields additional insights into the correlation between circuit structure and circuit timing by characterizing the degree to which specific signal paths limit the overall performance and reliability of a circuit. This information is directly applicable to logic and architectural synthesis.
{"title":"Clock skew scheduling for improved reliability via quadratic programming","authors":"I. Kourtev, E. Friedman","doi":"10.1109/ICCAD.1999.810655","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810655","url":null,"abstract":"This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic programming (QP) problem is introduced. The concept of a permissible range, or a valid interval, for the clock skew of each local data path is key to this QP approach. From a reliability perspective, the ideal clock schedule corresponds to each clock skew within the circuit being at the center of the respective permissible range. However, this ideal clock schedule is nor practically implementable because of limitations imposed by the connectivity among the registers within the circuit. To evaluate the reliability, a quadratic cost function is introduced as the Euclidean distance between the ideal schedule and a given practically feasible clock schedule. This cost function is the minimization objective of the described algorithms for the solution of the previously mentioned quadratic program. Furthermore, the work described here substantially differs from previous research in that it permits complete control over specific clock signal delays or skews within the circuit. Specifically, the algorithms described here can be employed to obtain results with explicitly specified target values of important clock delays/skews with a circuit, such as for example, the clock delays/skews for I/O registers. An additional benefit is a potential reduction in clock period of up to 10%. An efficient mathematical algorithm is derived for the solution of the QP problem with O(r/sup 3/) run time complexity and O(r/sup 2/) storage complexity, where r is the number of registers in the circuit. The algorithm is implemented as a C++ program and demonstrated on the ISCAS'89 suite of benchmark circuits as well as on a number of industrial circuits. The work described here yields additional insights into the correlation between circuit structure and circuit timing by characterizing the degree to which specific signal paths limit the overall performance and reliability of a circuit. This information is directly applicable to logic and architectural synthesis.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"70 1","pages":"239-243"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83743606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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