Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810683
Huiqun Liu, D. F. Wong
Presents an optimal algorithm to solve the schedule compression problem, which is an open problem proposed by S. Trimberger (1998) for time-multiplexed FPGA partitioning. Time-multiplexed FPGAs have the potential to dramatically improve logic density by time-sharing logic. Schedule compression is an important step in partitioning for time-multiplexed FPGAs and can greatly influence the quality of the partitioning solution. We exactly solve the schedule compression problem by converting it to a constrained min-max path problem. We further extend our algorithm to minimize the communication cost during schedule compression. Experiments show that our optimal algorithm outperforms the existing heuristics and runs very efficiently.
{"title":"A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning","authors":"Huiqun Liu, D. F. Wong","doi":"10.1109/ICCAD.1999.810683","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810683","url":null,"abstract":"Presents an optimal algorithm to solve the schedule compression problem, which is an open problem proposed by S. Trimberger (1998) for time-multiplexed FPGA partitioning. Time-multiplexed FPGAs have the potential to dramatically improve logic density by time-sharing logic. Schedule compression is an important step in partitioning for time-multiplexed FPGAs and can greatly influence the quality of the partitioning solution. We exactly solve the schedule compression problem by converting it to a constrained min-max path problem. We further extend our algorithm to minimize the communication cost during schedule compression. Experiments show that our optimal algorithm outperforms the existing heuristics and runs very efficiently.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"25 1","pages":"400-405"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86119830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810697
P. Panda
With increasing design complexity and chip area, on-chip memory has become an important component whose integration needs to be addressed during system design. Modern embedded DRAM technology allows for large amounts of on-chip memory space. However, in order to utilize the available memory intelligently, the memory has to be appropriately customized for the specific application. We address the topic of incorporating the application-specific customization of memory bank configuration into behavioral synthesis. The strategy involves a partitioning of behavioral arrays into memory banks based on a cost function that estimates the performance implications. For a given candidate partition, we present a heuristic for determining the access sequence that minimizes page misses in a bank while respecting data dependences. The output of the exploration is a graph displaying the variation of delay and memory area with the bank configuration. Our experiments on several memory-intensive examples confirm that the exploration results can provide critical feedback to the designer about the optimal memory configuration for a given application.
{"title":"Memory bank customization and assignment in behavioral synthesis","authors":"P. Panda","doi":"10.1109/ICCAD.1999.810697","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810697","url":null,"abstract":"With increasing design complexity and chip area, on-chip memory has become an important component whose integration needs to be addressed during system design. Modern embedded DRAM technology allows for large amounts of on-chip memory space. However, in order to utilize the available memory intelligently, the memory has to be appropriately customized for the specific application. We address the topic of incorporating the application-specific customization of memory bank configuration into behavioral synthesis. The strategy involves a partitioning of behavioral arrays into memory banks based on a cost function that estimates the performance implications. For a given candidate partition, we present a heuristic for determining the access sequence that minimizes page misses in a bank while respecting data dependences. The output of the exploration is a graph displaying the variation of delay and memory area with the bank configuration. Our experiments on several memory-intensive examples confirm that the exploration results can provide critical feedback to the designer about the optimal memory configuration for a given application.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"4 1","pages":"477-481"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84880679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810648
M. Golumbic, A. Mintz
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. The independent stage includes logic operations such as decomposition, extraction, factoring, substitution and elimination. These operations are done with some kind of division (Boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals. In this paper, we present an algorithm for factoring that uses graph partitioning rather than division. Central to our approach is to combine this with the use of special classes of Boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. Our method has been implemented in the SIS environment, and an empirical evaluation indicates that we usually get significantly better results than algebraic factoring and are quite competitive with Boolean factoring but with lower computation costs.
{"title":"Factoring logic functions using graph partitioning","authors":"M. Golumbic, A. Mintz","doi":"10.1109/ICCAD.1999.810648","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810648","url":null,"abstract":"Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical properties and the dependent stage where mapping to a physical cell library is done. The independent stage includes logic operations such as decomposition, extraction, factoring, substitution and elimination. These operations are done with some kind of division (Boolean, algebraic), with the goal being to obtain a logically equivalent factored form which minimizes the number of literals. In this paper, we present an algorithm for factoring that uses graph partitioning rather than division. Central to our approach is to combine this with the use of special classes of Boolean functions, such as read-once functions, to devise new combinatorial algorithms for logic minimization. Our method has been implemented in the SIS environment, and an empirical evaluation indicates that we usually get significantly better results than algebraic factoring and are quite competitive with Boolean factoring but with lower computation costs.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"26 1 1","pages":"195-198"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90426655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810652
Altan Odabasioglu, M. Çelik, L. Pileggi
Krylov space methods initiated a new era for RLC circuit model order reduction. Although theoretically well-founded, these algorithms can fail to produce useful results for some types of circuits. In particular controlling accuracy and ensuring passivity are required to fully utilize these algorithms in practice. In this paper we propose a methodology for passive reduction of RLC circuits based on extensions of PRIMA, that is both broad and practical. This work is made possible by uncovering the algebraic connections between this passive model order reduction algorithm and other Krylov space methods. In addition, a convergence criteria based on an error measure for PRIMA is presented as a first step towards intelligent order selection schemes. With these extensions and error criterion examples demonstrate that accurate approximations are possible well into the RF frequency range even with expansions about s=0.
{"title":"Practical considerations for passive reduction of RLC circuits","authors":"Altan Odabasioglu, M. Çelik, L. Pileggi","doi":"10.1109/ICCAD.1999.810652","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810652","url":null,"abstract":"Krylov space methods initiated a new era for RLC circuit model order reduction. Although theoretically well-founded, these algorithms can fail to produce useful results for some types of circuits. In particular controlling accuracy and ensuring passivity are required to fully utilize these algorithms in practice. In this paper we propose a methodology for passive reduction of RLC circuits based on extensions of PRIMA, that is both broad and practical. This work is made possible by uncovering the algebraic connections between this passive model order reduction algorithm and other Krylov space methods. In addition, a convergence criteria based on an error measure for PRIMA is presented as a first step towards intelligent order selection schemes. With these extensions and error criterion examples demonstrate that accurate approximations are possible well into the RF frequency range even with expansions about s=0.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"138 1","pages":"214-219"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78731360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810665
M. Cuviello, S. Dey, Xiaoliang Bai, Yi Zhao
System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.
{"title":"Fault modeling and simulation for crosstalk in system-on-chip interconnects","authors":"M. Cuviello, S. Dey, Xiaoliang Bai, Yi Zhao","doi":"10.1109/ICCAD.1999.810665","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810665","url":null,"abstract":"System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"2014 1","pages":"297-303"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78926682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1007/978-1-4757-3415-7_1
Hung-Ming Chen, H. Zhou, Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, N. Sherwani
{"title":"Integrated floorplanning and interconnect planning","authors":"Hung-Ming Chen, H. Zhou, Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, N. Sherwani","doi":"10.1007/978-1-4757-3415-7_1","DOIUrl":"https://doi.org/10.1007/978-1-4757-3415-7_1","url":null,"abstract":"","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"198 1","pages":"354-357"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76959729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810628
T. Serdar, C. Sechen
Describes AKORD, a transistor-level and mixed transistor/gate-level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post-placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD dynamically supports: (1) transistor folding without the usage of device libraries that contain variants of the same device; (2) device merging, including information about optimal transistor chain formation; and (3) well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.
{"title":"AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths","authors":"T. Serdar, C. Sechen","doi":"10.1109/ICCAD.1999.810628","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810628","url":null,"abstract":"Describes AKORD, a transistor-level and mixed transistor/gate-level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post-placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD dynamically supports: (1) transistor folding without the usage of device libraries that contain variants of the same device; (2) device merging, including information about optimal transistor chain formation; and (3) well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"256 1","pages":"91-97"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74511705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810622
M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov
A new adaptive approach to solving large-dimension harmonic balance (HB) problems in RF circuit simulation is presented. The method is based on adjusting the order of the equation system according to the degree of nonlinearity of each node in the circuit. A block-diagonal preconditioner is used to construct an algorithm for order reduction during the iterative HB process.
{"title":"New methods for speeding up computation of Newton updates in harmonic balance","authors":"M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov","doi":"10.1109/ICCAD.1999.810622","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810622","url":null,"abstract":"A new adaptive approach to solving large-dimension harmonic balance (HB) problems in RF circuit simulation is presented. The method is based on adjusting the order of the equation system according to the degree of nonlinearity of each node in the circuit. A block-diagonal preconditioner is used to construct an algorithm for order reduction during the iterative HB process.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"103 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80801030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810631
Min Zhao, S. Sapatnekar
Domino logic is a high-performance circuit configuration that is usually embedded in a static logic environment and tightly coupled with the clocking scheme. In this paper the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided In addition, an efficient static mapping algorithm is described.
{"title":"Timing-driven partitioning for two-phase domino and mixed static/domino implementations","authors":"Min Zhao, S. Sapatnekar","doi":"10.1109/ICCAD.1999.810631","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810631","url":null,"abstract":"Domino logic is a high-performance circuit configuration that is usually embedded in a static logic environment and tightly coupled with the clocking scheme. In this paper the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided In addition, an efficient static mapping algorithm is described.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"4 1","pages":"107-110"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84658523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810668
H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.
{"title":"What is the cost of delay insensitivity?","authors":"H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev","doi":"10.1109/ICCAD.1999.810668","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810668","url":null,"abstract":"Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"23 1","pages":"316-323"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85190098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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