Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810642
J. Cong, Jie Fang, Kei-Yong Khoo
ECO routing is a very important design capability in advanced IC, MCM and PCB designs when additional routings need to be made at the latter stage of the physical design. ECO is difficult in two aspects: first, there are a large number of existing interconnects which become obstacles in the region. A hierarchical approach is not applicable in this situation, and we need to search a large, congested region thoroughly. Second, advances in circuit designs require variable width and variable spacing on interconnects. Thus, a gridless routing algorithm is needed. We propose to use an implicit representation of a non-uniform grid graph for a gridless maze routing algorithm. A novel slit-tree plus interval-tree data structure is developed, combined with a cache structure, to support efficient queries into the connection graph. Our experiments show that this data structure is very small in memory usage while very fast in answering maze expansion related queries. This makes the framework very useful in the ECO type of routing.
{"title":"An implicit connection graph maze routing algorithm for ECO routing","authors":"J. Cong, Jie Fang, Kei-Yong Khoo","doi":"10.1109/ICCAD.1999.810642","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810642","url":null,"abstract":"ECO routing is a very important design capability in advanced IC, MCM and PCB designs when additional routings need to be made at the latter stage of the physical design. ECO is difficult in two aspects: first, there are a large number of existing interconnects which become obstacles in the region. A hierarchical approach is not applicable in this situation, and we need to search a large, congested region thoroughly. Second, advances in circuit designs require variable width and variable spacing on interconnects. Thus, a gridless routing algorithm is needed. We propose to use an implicit representation of a non-uniform grid graph for a gridless maze routing algorithm. A novel slit-tree plus interval-tree data structure is developed, combined with a cache structure, to support efficient queries into the connection graph. Our experiments show that this data structure is very small in memory usage while very fast in answering maze expansion related queries. This makes the framework very useful in the ECO type of routing.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"11 1","pages":"163-167"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90991953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810646
R. Murgai
Typically, cell parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. The performance optimization algorithms, however, assume a single value for each parameter. No work has been done to study the impact of separate rise and fall values on the complexity of optimization. We take the first step towards understanding this impact. We pick two problems that have polynomial-time complexities if a single value for each cell parameter is assumed. The first problem is that of buffer insertion on a fixed topology net to maximize the required time at the source of the net. The second is the gate resizing problem (and the more general technology mapping problem) for minimizing the circuit delay under the simplest, load-independent delay model. We show that under separate rise and fall parameters, both these problems become NP-complete. To the best of our knowledge, this is the first such result showing the effect of rise and fall parameters on the complexity of performance optimization problems. We then address the important question of devising a good practical algorithm for local fanout optimization.
{"title":"Performance optimization under rise and fall parameters","authors":"R. Murgai","doi":"10.1109/ICCAD.1999.810646","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810646","url":null,"abstract":"Typically, cell parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. The performance optimization algorithms, however, assume a single value for each parameter. No work has been done to study the impact of separate rise and fall values on the complexity of optimization. We take the first step towards understanding this impact. We pick two problems that have polynomial-time complexities if a single value for each cell parameter is assumed. The first problem is that of buffer insertion on a fixed topology net to maximize the required time at the source of the net. The second is the gate resizing problem (and the more general technology mapping problem) for minimizing the circuit delay under the simplest, load-independent delay model. We show that under separate rise and fall parameters, both these problems become NP-complete. To the best of our knowledge, this is the first such result showing the effect of rise and fall parameters on the complexity of performance optimization problems. We then address the important question of devising a good practical algorithm for local fanout optimization.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"112 1","pages":"185-190"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87651654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper we propose two new transformations of replacing wires. One transformation simultaneously replaces multiple input wires of a gate by a new set of input wires and the other performs gate decomposition during the alternative wire process. To accomplish such complex transformations, we discuss some theoretical foundations for replacing multiple wires. Understanding how wires/gates can be replaced by other wires/gates allows us to speedup the process tremendously.
{"title":"Synthesis for multiple input wires replacement of a gate for wiring consideration","authors":"Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu","doi":"10.1109/ICCAD.1999.810633","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810633","url":null,"abstract":"The alternative wire technique attempts to replace a target wire by another wire without changing the logic functionality. In this paper we propose two new transformations of replacing wires. One transformation simultaneously replaces multiple input wires of a gate by a new set of input wires and the other performs gate decomposition during the alternative wire process. To accomplish such complex transformations, we discuss some theoretical foundations for replacing multiple wires. Understanding how wires/gates can be replaced by other wires/gates allows us to speedup the process tremendously.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"1085 1","pages":"115-118"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86470972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810714
J. P. Bergmann, M. Horowitz
State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing the state and edge coverage provided by tests with that which is possible in the design's state graph, the designer can estimate how well tested the design is and identify areas that need better testing. Unfortunately, for many interesting designs, the full state graph may be too large to fully explore, or if it is explorable, the resulting coverage may be so low as to provide limited feedback. Several techniques have been proposed that identify and work with an interesting subset of the design's state machines, but they still require computing the full state graph before projecting it. In this paper we discuss projection directed state exploration, in which a projection from the full graph is found while exploring only the relevant portion of the full graph. Even with this limited exploration, BDD size blowup is still a problem. To deal with this, we have also developed several interactive tools that provide feedback to the designer, and allow them to add hints to help with the exploration.
{"title":"Improving coverage analysis and test generation for large designs","authors":"J. P. Bergmann, M. Horowitz","doi":"10.1109/ICCAD.1999.810714","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810714","url":null,"abstract":"State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing the state and edge coverage provided by tests with that which is possible in the design's state graph, the designer can estimate how well tested the design is and identify areas that need better testing. Unfortunately, for many interesting designs, the full state graph may be too large to fully explore, or if it is explorable, the resulting coverage may be so low as to provide limited feedback. Several techniques have been proposed that identify and work with an interesting subset of the design's state machines, but they still require computing the full state graph before projecting it. In this paper we discuss projection directed state exploration, in which a projection from the full graph is found while exploring only the relevant portion of the full graph. Even with this limited exploration, BDD size blowup is still a problem. To deal with this, we have also developed several interactive tools that provide feedback to the designer, and allow them to add hints to help with the exploration.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"31 1","pages":"580-583"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79335746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810649
B. Sheehan
Time Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (/spl sim/10/sup 7/ nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.
{"title":"TICER: Realizable reduction of extracted RC circuits","authors":"B. Sheehan","doi":"10.1109/ICCAD.1999.810649","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810649","url":null,"abstract":"Time Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (/spl sim/10/sup 7/ nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"13 1","pages":"200-203"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88047089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810705
J. H. Jiang, I. Jiang
With increasing density and capacity due to technology scaling, augmenting data (especially in semiconductor memories) burden selection circuitry with exponentially growing capacitive loads. This tendency violates stringent timing requirements. This work ameliorates the situation for k-stage tree-type decision circuitry. We show that for a k-stage binary decision tree, there always exists an optimum solution such that, after the select-signal arrangement, the worst case loading among select signals equals a lower bound. Our proposed procedure not only provides an optimum solution but also minimizes the loading variance. The worst case loading can be reduced up to nearly k/2 times, thus speeding up and saving power up to W2 times or so for the select signal with the heaviest loading. In contrast, excluding one unit-loading select signal, the empirical variance of the remaining (k-1) signals is always less than 1 instead of diverging. Hence, our approach, for timing-driven layout synthesis, is competent to design high-performance tree-type decision circuitry with more accurate timing and power prediction. In addition, by the presented approach, we can have the alternative of optimizing either for k-stage or for (k-1)-stage, meanwhile possibly minimizing the other. Our algorithm, also, can easily be extended for a general k-stage decision tree with r descendants per node, not restricted to a binary tree; the resultant worst case loading could be quite close to the lower bound and reduced up to nearly k(r-1)/r times.
{"title":"Optimum loading dispersion for high-speed tree-type decision circuitry","authors":"J. H. Jiang, I. Jiang","doi":"10.1109/ICCAD.1999.810705","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810705","url":null,"abstract":"With increasing density and capacity due to technology scaling, augmenting data (especially in semiconductor memories) burden selection circuitry with exponentially growing capacitive loads. This tendency violates stringent timing requirements. This work ameliorates the situation for k-stage tree-type decision circuitry. We show that for a k-stage binary decision tree, there always exists an optimum solution such that, after the select-signal arrangement, the worst case loading among select signals equals a lower bound. Our proposed procedure not only provides an optimum solution but also minimizes the loading variance. The worst case loading can be reduced up to nearly k/2 times, thus speeding up and saving power up to W2 times or so for the select signal with the heaviest loading. In contrast, excluding one unit-loading select signal, the empirical variance of the remaining (k-1) signals is always less than 1 instead of diverging. Hence, our approach, for timing-driven layout synthesis, is competent to design high-performance tree-type decision circuitry with more accurate timing and power prediction. In addition, by the presented approach, we can have the alternative of optimizing either for k-stage or for (k-1)-stage, meanwhile possibly minimizing the other. Our algorithm, also, can easily be extended for a general k-stage decision tree with r descendants per node, not restricted to a binary tree; the resultant worst case loading could be quite close to the lower bound and reduced up to nearly k(r-1)/r times.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"11 1","pages":"520-524"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82811312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810615
J. Lou, Wei Chen, Massoud Pedram
An algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each super-cell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm.
{"title":"Concurrent logic restructuring and placement for timing closure","authors":"J. Lou, Wei Chen, Massoud Pedram","doi":"10.1109/ICCAD.1999.810615","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810615","url":null,"abstract":"An algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and then generates the set of non-inferior re-mapping solutions for each super-cell. The best mapping and placement solutions for all super-cells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"5 1","pages":"31-35"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88405603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810681
K. Chakrabarty
We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and is therefore NP-complete. However a commonly-encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible.
{"title":"Test scheduling for core-based systems","authors":"K. Chakrabarty","doi":"10.1109/ICCAD.1999.810681","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810681","url":null,"abstract":"We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and is therefore NP-complete. However a commonly-encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"26 1","pages":"391-394"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84576821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810696
P. Pant, A. Chatterjee
A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.
提出了一种基于因果分析的路径延迟故障诊断方法。我们力求对y . c .介绍的方法提供更好的理解。Hsu和S.K. Gupta(1998)，其目标是设计有效的路径延迟故障诊断表示和算法。结果表明，所获得的诊断分辨率非常高，并且包含了观察到的延迟故障的所有可能原因。
{"title":"Efficient diagnosis of path delay faults in digital logic circuits","authors":"P. Pant, A. Chatterjee","doi":"10.1109/ICCAD.1999.810696","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810696","url":null,"abstract":"A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"36 1","pages":"471-475"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85790383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810701
D. Lungeanu, C. Shi
The paper presents a novel protocol for parallel and distributed simulation of VLSI systems. It is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. Second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. All these features make it very convenient and practical, extending the class of applications to at least all VHDL circuits, including delta cycle. The proposed protocol has been implemented and used for VHDL simulation. Experimental results on several large VHDL circuits (between 1411 and 14704 processes) have shown promising linear speedups. We also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. This protocol may have a strong impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.
{"title":"Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization","authors":"D. Lungeanu, C. Shi","doi":"10.1109/ICCAD.1999.810701","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810701","url":null,"abstract":"The paper presents a novel protocol for parallel and distributed simulation of VLSI systems. It is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. Second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. All these features make it very convenient and practical, extending the class of applications to at least all VHDL circuits, including delta cycle. The proposed protocol has been implemented and used for VHDL simulation. Experimental results on several large VHDL circuits (between 1411 and 14704 processes) have shown promising linear speedups. We also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. This protocol may have a strong impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"75 1","pages":"500-504"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86063446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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