Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810617
A. Xie, P. Beerel
This paper presents a binary decision diagram (BDD) based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experiments suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency matrix of the graphs.
{"title":"Implicit enumeration of strongly connected components","authors":"A. Xie, P. Beerel","doi":"10.1109/ICCAD.1999.810617","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810617","url":null,"abstract":"This paper presents a binary decision diagram (BDD) based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experiments suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency matrix of the graphs.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"14 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74177785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810651
Xiaodong Yang, W. Ku, Chung-Kuan Cheng
A new category of moments-Amplitude and Phase moments (AP moments) are introduced for RLC interconnect delay estimation. We show that there are tight relationships between AP moments, circuit moments and central moments. The first order AP moment represents the Elmore delay while the higher order AP moments can be used to represent the error between the Elmore delay and the exact 50% delay from the view of gain and phase-shift variation. With the help of the physical meaning revealed by the AP moments, a closed-form 50% delay model-AP delay model is proposed for RLC interconnect delay estimation in terms of the first four AP moments. We also propose a new two-pole model (AP two-pole model) by matching the first two phase moments of the transfer function. The AP two-pole model can be used for more generally timing parameters estimation. The input signal's impact on delay estimation can be incorporated into these two delay models by simply combining the input signal's AP moments with the transfer function's AP moments. In our experiments these two models show significant accuracy improvement over the Elmore delay model.
{"title":"RLC interconnect delay estimation via moments of amplitude and phase response","authors":"Xiaodong Yang, W. Ku, Chung-Kuan Cheng","doi":"10.1109/ICCAD.1999.810651","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810651","url":null,"abstract":"A new category of moments-Amplitude and Phase moments (AP moments) are introduced for RLC interconnect delay estimation. We show that there are tight relationships between AP moments, circuit moments and central moments. The first order AP moment represents the Elmore delay while the higher order AP moments can be used to represent the error between the Elmore delay and the exact 50% delay from the view of gain and phase-shift variation. With the help of the physical meaning revealed by the AP moments, a closed-form 50% delay model-AP delay model is proposed for RLC interconnect delay estimation in terms of the first four AP moments. We also propose a new two-pole model (AP two-pole model) by matching the first two phase moments of the transfer function. The AP two-pole model can be used for more generally timing parameters estimation. The input signal's impact on delay estimation can be incorporated into these two delay models by simply combining the input signal's AP moments with the transfer function's AP moments. In our experiments these two models show significant accuracy improvement over the Elmore delay model.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"90 1","pages":"208-213"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77904241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810688
R. Ho, K. Mai, H. Kapadia, M. Horowitz
Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by D. Sylvester and K. Keutzer (1998) examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. We show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.
{"title":"Interconnect scaling implications for CAD","authors":"R. Ho, K. Mai, H. Kapadia, M. Horowitz","doi":"10.1109/ICCAD.1999.810688","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810688","url":null,"abstract":"Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by D. Sylvester and K. Keutzer (1998) examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. We show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"22 1","pages":"425-429"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80266601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810619
H. Higuchi, F. Somenzi
Proposes lazy group sifting for dynamic variable reordering during state traversal of finite state machines (FSMs). The proposed method relaxes the idea of pairwise grouping of the present state variables and their corresponding next state variables. This is done to produce better variable orderings during image computation without causing BDD (binary decision diagram) size blowup in the substitution of next state variables with present state variables at the end of image computation. Experimental results show that our approach is more robust in state traversal than the approaches that either unconditionally group variable pairs or never group them.
{"title":"Lazy group sifting for efficient symbolic state traversal of FSMs","authors":"H. Higuchi, F. Somenzi","doi":"10.1109/ICCAD.1999.810619","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810619","url":null,"abstract":"Proposes lazy group sifting for dynamic variable reordering during state traversal of finite state machines (FSMs). The proposed method relaxes the idea of pairwise grouping of the present state variables and their corresponding next state variables. This is done to produce better variable orderings during image computation without causing BDD (binary decision diagram) size blowup in the substitution of next state variables with present state variables at the end of image computation. Experimental results show that our approach is more robust in state traversal than the approaches that either unconditionally group variable pairs or never group them.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"11 1","pages":"45-49"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79518243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new surface integral formulation and discretization approach for computing electromagnetoquasistatic impedance of general conductors is described. The key advantages of the formulation is that it avoids volume discretization of the conductors and the substrate, and a single discretization is accurate over the entire frequency range. Computational results from an on-chip inductor, a connector and a transmission line are used to show that the formulation is accurate and is "acceleration" ready. That is, the results demonstrate that an efficiently computed preconditioner insures rapid iterative method convergence and tests with projection show the required kernels can be approximated easily using a coarse grid.
{"title":"A wide frequency range surface integral formulation for 3-D RLC extraction","authors":"Junfeng Wang, J. Tausch, Jacob K. White","doi":"10.5555/339492.340057","DOIUrl":"https://doi.org/10.5555/339492.340057","url":null,"abstract":"A new surface integral formulation and discretization approach for computing electromagnetoquasistatic impedance of general conductors is described. The key advantages of the formulation is that it avoids volume discretization of the conductors and the substrate, and a single discretization is accurate over the entire frequency range. Computational results from an on-chip inductor, a connector and a transmission line are used to show that the formulation is accurate and is \"acceleration\" ready. That is, the results demonstrate that an efficiently computed preconditioner insures rapid iterative method convergence and tests with projection show the required kernels can be approximated easily using a coarse grid.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"14 1","pages":"453-457"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87787336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810621
A. Mehrotra, A. Sangiovanni-Vincentelli
Considers the important problem of noise analysis of non-autonomous nonlinear RF circuits in the presence of input signal phase noise. We formulate this problem as a stochastic differential equation and solve it in the presence of circuit white-noise sources. We show that the output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary-not cyclostationary (as would be predicted by traditional analyses). We also show that effect of the input signal phase noise is to act as additional white noise source. This result is derived using a full nonlinear analysis of the problem and cannot be predicted by traditional linear analysis-based techniques. Input signal phase noise can be an important portion of the overall output noise of the non-autonomous circuit. In our opinion, existing analyses have not considered this effect in a rigorous manner. We also relate this solution to results of the existing nonlinear time-domain and frequency-domain methods of noise analysis and point out the modifications required for the present techniques. We illustrate our technique using an example.
{"title":"Noise analysis of non-autonomous radio frequency circuits","authors":"A. Mehrotra, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1999.810621","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810621","url":null,"abstract":"Considers the important problem of noise analysis of non-autonomous nonlinear RF circuits in the presence of input signal phase noise. We formulate this problem as a stochastic differential equation and solve it in the presence of circuit white-noise sources. We show that the output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary-not cyclostationary (as would be predicted by traditional analyses). We also show that effect of the input signal phase noise is to act as additional white noise source. This result is derived using a full nonlinear analysis of the problem and cannot be predicted by traditional linear analysis-based techniques. Input signal phase noise can be an important portion of the overall output noise of the non-autonomous circuit. In our opinion, existing analyses have not considered this effect in a rigorous manner. We also relate this solution to results of the existing nonlinear time-domain and frequency-domain methods of noise analysis and point out the modifications required for the present techniques. We illustrate our technique using an example.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"27 1","pages":"55-60"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79091971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810647
Y. Tamiya
In this paper, we propose a new method to optimize a performance of a very large circuit. We find the best set of local transformations to be applied to the circuit, by inserting "padding nodes" on noncritical edges of the circuit, and calculating separator sets of the circuit using separator sets. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. According to our experimental results, our method has accomplished all circuits, while Singh's (1992) selection function method has aborted with three large circuits because of memory overflow. The results also shows our method has a comparable capability in delay optimization to Singh's method.
{"title":"Performance optimization using separator sets","authors":"Y. Tamiya","doi":"10.1109/ICCAD.1999.810647","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810647","url":null,"abstract":"In this paper, we propose a new method to optimize a performance of a very large circuit. We find the best set of local transformations to be applied to the circuit, by inserting \"padding nodes\" on noncritical edges of the circuit, and calculating separator sets of the circuit using separator sets. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. According to our experimental results, our method has accomplished all circuits, while Singh's (1992) selection function method has aborted with three large circuits because of memory overflow. The results also shows our method has a comparable capability in delay optimization to Singh's method.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"20 1","pages":"191-194"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72795080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810664
Arani Sinha, S. Gupta, M. Breuer
Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 /spl mu/m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To facilitate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.
{"title":"Validation and test generation for oscillatory noise in VLSI interconnects","authors":"Arani Sinha, S. Gupta, M. Breuer","doi":"10.1109/ICCAD.1999.810664","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810664","url":null,"abstract":"Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 /spl mu/m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To facilitate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"36 1","pages":"289-296"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79248472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810644
S. Dutt, V. Shanmugavel, S. Trimberger
The ability to reconfigure around manufacturing defects and operational faults increases FPGA chip yield, reduces system downtime and maintenance in field operation, and increases reliabilities of mission- and life-critical systems. The fault reconfiguration technique discussed in this work uses the principle of node covering in which reconfiguration is achieved by constructing replacement chains of cells from faulty cells to spare/unused ones. A key issue in such reconfiguration is efficient incremental rerouting in the FPGA. Previous methods for node-covering based reconfiguration are "static" in the sense that extra interconnects are added a-priori as part of the initial circuit routing so that a specific fault pattern (e.g. one fault per row) can be tolerated. This, however, results in worst-case track overheads and also in an inflexibility to tolerate other realistic fault patterns. We develop dynamic reconfiguration and incremental rerouting techniques that are fault specific. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. When faults occur the routed nets have to be minimally perturbed to allow these interconnects to be inserted "on-the-fly" for reconfiguration. These requirements are addressed in our minimally incremental rerouting technique Conv-T-DAG, which uses a cost-directed depth-first search strategy. We prove several results that establishes the near-optimality of Conv-T-DAG in terms of track overhead. To the best of our knowledge this is the first time that an incremental rerouting technique has been developed for FPGAs. For several benchmark circuits, the static approach to tolerating one fault per row resulted in a 43% to 34% track overhead. Using the dynamic reconfiguration approach and Conv-T-DAG results in an average overhead of only 16%-an improvement of more than 50%. Over all circuits, the reconfiguration time per fault ranges from 16.8 to 72.9 secs. Simulation of smaller fault sets of one to four faults show very small track overheads ranging from 1.75% to 4.49%. Conv-T-DAG can also be used for interconnect fault tolerance.
{"title":"Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays","authors":"S. Dutt, V. Shanmugavel, S. Trimberger","doi":"10.1109/ICCAD.1999.810644","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810644","url":null,"abstract":"The ability to reconfigure around manufacturing defects and operational faults increases FPGA chip yield, reduces system downtime and maintenance in field operation, and increases reliabilities of mission- and life-critical systems. The fault reconfiguration technique discussed in this work uses the principle of node covering in which reconfiguration is achieved by constructing replacement chains of cells from faulty cells to spare/unused ones. A key issue in such reconfiguration is efficient incremental rerouting in the FPGA. Previous methods for node-covering based reconfiguration are \"static\" in the sense that extra interconnects are added a-priori as part of the initial circuit routing so that a specific fault pattern (e.g. one fault per row) can be tolerated. This, however, results in worst-case track overheads and also in an inflexibility to tolerate other realistic fault patterns. We develop dynamic reconfiguration and incremental rerouting techniques that are fault specific. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. When faults occur the routed nets have to be minimally perturbed to allow these interconnects to be inserted \"on-the-fly\" for reconfiguration. These requirements are addressed in our minimally incremental rerouting technique Conv-T-DAG, which uses a cost-directed depth-first search strategy. We prove several results that establishes the near-optimality of Conv-T-DAG in terms of track overhead. To the best of our knowledge this is the first time that an incremental rerouting technique has been developed for FPGAs. For several benchmark circuits, the static approach to tolerating one fault per row resulted in a 43% to 34% track overhead. Using the dynamic reconfiguration approach and Conv-T-DAG results in an average overhead of only 16%-an improvement of more than 50%. Over all circuits, the reconfiguration time per fault ranges from 16.8 to 72.9 secs. Simulation of smaller fault sets of one to four faults show very small track overheads ranging from 1.75% to 4.49%. Conv-T-DAG can also be used for interconnect fault tolerance.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"69 1","pages":"173-176"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85100416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810645
David S. Kung, R. Puri
The effectiveness of logic synthesis to satisfy increasingly tight timing constraints in deep-submicron high-performance circuits heavily depends on the range and variety of logic gates available in the standard cell library. Primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. Since CMOS logic circuit delays not only depend on the drive strength of each gate but also on its PM width ratio, it is crucial to provide good PM width ratios for each cell. The main contribution of this paper is the development of a theoretical framework through which library designers can determine "optimal" PM width ratio for each logic gate in their high-performance standard cell library. This theoretical framework utilizes new gate delay models that explicitly represent the dependence of delay on P/N width ratio and load. These delay models yield highly accurate delay for CMOS gates in a 0.12 /spl mu/m L/sub eff/ deep-submicron technology.
{"title":"Optimal P/N width ratio selection for standard cell libraries","authors":"David S. Kung, R. Puri","doi":"10.1109/ICCAD.1999.810645","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810645","url":null,"abstract":"The effectiveness of logic synthesis to satisfy increasingly tight timing constraints in deep-submicron high-performance circuits heavily depends on the range and variety of logic gates available in the standard cell library. Primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. Since CMOS logic circuit delays not only depend on the drive strength of each gate but also on its PM width ratio, it is crucial to provide good PM width ratios for each cell. The main contribution of this paper is the development of a theoretical framework through which library designers can determine \"optimal\" PM width ratio for each logic gate in their high-performance standard cell library. This theoretical framework utilizes new gate delay models that explicitly represent the dependence of delay on P/N width ratio and load. These delay models yield highly accurate delay for CMOS gates in a 0.12 /spl mu/m L/sub eff/ deep-submicron technology.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"50 1","pages":"178-184"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81774037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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