Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496563
N. Bobby, S. Srivatsa, L. Kishore, A. Rajiv, S. S. Suresh
Adaptive Viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented FastRadix 2 ACS in Viterbi decoder and Adaptive Viterbi decoder. The area consumption was more in Viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20% where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, Adaptive Radix2 acs in Viterbi decoder. But the experimental result proves power consumption is less in Adaptive FastRadix 2 ACS in Viterbi decoder than FastRadix 2 ACS in Viterbi decoder.
{"title":"Comparison of fast radix 2 ACS with adaptive fast radix 2 ACS in Viterbi Decoder","authors":"N. Bobby, S. Srivatsa, L. Kishore, A. Rajiv, S. S. Suresh","doi":"10.1109/ICEVENT.2013.6496563","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496563","url":null,"abstract":"Adaptive Viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, we have implemented FastRadix 2 ACS in Viterbi decoder and Adaptive Viterbi decoder. The area consumption was more in Viterbi compared to Adaptive Viterbi decoder. But the power utilization reduced drastically to 20% where as in Viterbi decoder the power consumed was 80%. In our previous work we have implemented Adaptive fast ACS, Adaptive Radix2 acs in Viterbi decoder. But the experimental result proves power consumption is less in Adaptive FastRadix 2 ACS in Viterbi decoder than FastRadix 2 ACS in Viterbi decoder.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"275 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76512225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496552
M. Rama, S. Raja
Graphical password, text password are authentication of users on websites because of its simplicity and easy. User's passwords are easy to hack by using different malicious programs and threats. First, Users select easy to remember password because nowadays they using many accounts on different websites. To login to websites they need to remember all passwords. So users would choose easy to remember passwords, but these passwords are not safe. Reusing passwords across different websites may cause users to lose their information which is stored in websites once the password hacked or compromised by attacker. Second, hackers can install malicious software to get the passwords, when user typing their username and password into unknown public computers. In this paper, developing web based security analysis of one Time password authentication schemes using mobile application. A user authentication protocol which involves user's cell phone and short message service to prevent password stealing and reuse attacks. User's only need to remember a long term password for login on different websites.
{"title":"Web based security analysis of OPASS authentication schemes using mobile application","authors":"M. Rama, S. Raja","doi":"10.1109/ICEVENT.2013.6496552","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496552","url":null,"abstract":"Graphical password, text password are authentication of users on websites because of its simplicity and easy. User's passwords are easy to hack by using different malicious programs and threats. First, Users select easy to remember password because nowadays they using many accounts on different websites. To login to websites they need to remember all passwords. So users would choose easy to remember passwords, but these passwords are not safe. Reusing passwords across different websites may cause users to lose their information which is stored in websites once the password hacked or compromised by attacker. Second, hackers can install malicious software to get the passwords, when user typing their username and password into unknown public computers. In this paper, developing web based security analysis of one Time password authentication schemes using mobile application. A user authentication protocol which involves user's cell phone and short message service to prevent password stealing and reuse attacks. User's only need to remember a long term password for login on different websites.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"44 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80122487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496569
M. Maruthusivarani, T. Ramakrishnan, D. Santhi, K. Muthukkutti
Blood vessel segmentation can be used for automatic retinal disease screening system. In this paper, comparison of automatic blood vessel segmentation methods in retinal images is presented and discussed. Morphological operation for the automatic segmentation of blood vessels in retinal images has been proposed and the results are compared with matched filter technique using local entropy thresholding. Blood vessels in retinal images are enhanced by the application of matched filter. The gray levels are spatially distributed by using local entropy based thresholding. Label filtering is performed by connected pixel labeling to eliminate the misclassified and isolated pixels. The blood vessels are segmented by using morphological opening based on structuring element. These methods were evaluated on the publicly available DRIVE database and the database contains retinal images along with the ground truth data that has been precisely marked by the experts. Morphological operation is more suitable for blood vessel segmentation as compared to the local entropy thresholding.
{"title":"Comparison of automatic blood vessel segmentation methods in retinal images","authors":"M. Maruthusivarani, T. Ramakrishnan, D. Santhi, K. Muthukkutti","doi":"10.1109/ICEVENT.2013.6496569","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496569","url":null,"abstract":"Blood vessel segmentation can be used for automatic retinal disease screening system. In this paper, comparison of automatic blood vessel segmentation methods in retinal images is presented and discussed. Morphological operation for the automatic segmentation of blood vessels in retinal images has been proposed and the results are compared with matched filter technique using local entropy thresholding. Blood vessels in retinal images are enhanced by the application of matched filter. The gray levels are spatially distributed by using local entropy based thresholding. Label filtering is performed by connected pixel labeling to eliminate the misclassified and isolated pixels. The blood vessels are segmented by using morphological opening based on structuring element. These methods were evaluated on the publicly available DRIVE database and the database contains retinal images along with the ground truth data that has been precisely marked by the experts. Morphological operation is more suitable for blood vessel segmentation as compared to the local entropy thresholding.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83200464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496551
A. Jayanthiladevi, H. M. Premlatha, G. Nawaz
Communication is one of the important areas of electronics and always been a focus for exchange of information among parties at locations physically apart. There may be different mode of communication. The communication may be wired or wireless between two links. Initially the mobile communication was limited to between one pair of users on single channel pair. Mobile communication has undergone many generations. With the rapid development of communication networks, it is expected that fourth generation mobile systems will be launched within decades. Fourth generation (4G) mobile systems focus on seamlessly integrating the existing wireless technologies including GSM, wireless LAN, and Bluetooth. This contrasts with third generation (3G), which merely focuses on developing new standards and hardware. 4G systems will support comprehensive and personalized services providing stable system performance and quality service. The future of mobile communication is FAMOUS-Future Advanced Mobile Universal Systems. The data rates targeted are 20 MBPS. That will be the FOURTH GENERATION (4G) in the mobile communication technology. 4G must be hastened, as some of the video applications cannot be contained within 3G.This paper highlights that current systems must be implemented with a view of facilitate to seamless integration into 4G infrastructure. Finally, it narrates how 4G mobile communication will bring a new level of connectivity and convenience in communication.
{"title":"Analysis study of seamless integration and intelligent solution in any situation by the future advanced mobile universal systems 4G - (FAMOUS 4G)","authors":"A. Jayanthiladevi, H. M. Premlatha, G. Nawaz","doi":"10.1109/ICEVENT.2013.6496551","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496551","url":null,"abstract":"Communication is one of the important areas of electronics and always been a focus for exchange of information among parties at locations physically apart. There may be different mode of communication. The communication may be wired or wireless between two links. Initially the mobile communication was limited to between one pair of users on single channel pair. Mobile communication has undergone many generations. With the rapid development of communication networks, it is expected that fourth generation mobile systems will be launched within decades. Fourth generation (4G) mobile systems focus on seamlessly integrating the existing wireless technologies including GSM, wireless LAN, and Bluetooth. This contrasts with third generation (3G), which merely focuses on developing new standards and hardware. 4G systems will support comprehensive and personalized services providing stable system performance and quality service. The future of mobile communication is FAMOUS-Future Advanced Mobile Universal Systems. The data rates targeted are 20 MBPS. That will be the FOURTH GENERATION (4G) in the mobile communication technology. 4G must be hastened, as some of the video applications cannot be contained within 3G.This paper highlights that current systems must be implemented with a view of facilitate to seamless integration into 4G infrastructure. Finally, it narrates how 4G mobile communication will bring a new level of connectivity and convenience in communication.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"90 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77263632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496557
Vinothkumar B, Kumar, T. Tntroductton
One of the most important challenges for practical face recognition systems is to make recognition more reliable under uncontrolled lighting conditions. We tackle this by using novel illumination-insensitive preprocessing method. The proposed face recognition system consists of a preprocessing stage, a hybrid Fourier-based facial feature extraction, and Principal Component Linear Discriminant Analysis (PCLDA). In the preprocessing stage, an “Integral Normalized Gradient Image”, (INGI) is obtained by transform a face image into an illumination-insensitive image. The effect of illumination gets reduced in the INGI by normalizing and integrating the smoothed gradients of a facial image. The hybrid Fourier features are extracted from three different Fourier domains in different frequency bandwidths by using a frequency band model selection, and further by adding PCLDA the robustness of the system gets improved. In face recognition, it is not possible to process with the entire extracted features, hence the dimension of the feature vectors has to be reduced. In this paper, this is done by using the linear method called PCLDA. The proposed system using the Yale B data set which is having a 2-D face images under various environmental variations such as illumination changes and expression changes.
{"title":"A novel preprocessing method and PCLDA algorithm for face recognition under difficult lighting conditions","authors":"Vinothkumar B, Kumar, T. Tntroductton","doi":"10.1109/ICEVENT.2013.6496557","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496557","url":null,"abstract":"One of the most important challenges for practical face recognition systems is to make recognition more reliable under uncontrolled lighting conditions. We tackle this by using novel illumination-insensitive preprocessing method. The proposed face recognition system consists of a preprocessing stage, a hybrid Fourier-based facial feature extraction, and Principal Component Linear Discriminant Analysis (PCLDA). In the preprocessing stage, an “Integral Normalized Gradient Image”, (INGI) is obtained by transform a face image into an illumination-insensitive image. The effect of illumination gets reduced in the INGI by normalizing and integrating the smoothed gradients of a facial image. The hybrid Fourier features are extracted from three different Fourier domains in different frequency bandwidths by using a frequency band model selection, and further by adding PCLDA the robustness of the system gets improved. In face recognition, it is not possible to process with the entire extracted features, hence the dimension of the feature vectors has to be reduced. In this paper, this is done by using the linear method called PCLDA. The proposed system using the Yale B data set which is having a 2-D face images under various environmental variations such as illumination changes and expression changes.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"44 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86339694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496541
G. Ramadoss, G. Prakash
The multi-band orthogonal frequency division multiplexing modem needs to process large amount of computations in short time for support of high data rates from 53 to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi way parallel architecture has been proposed. In this paper introduced several novel optimization techniques for resource efficient implementation of the baseband modem which has 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization techniques could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of entire baseband modem were about 474 kgates and 248 mW at 66 MHz.
{"title":"Implementation of low power MB-OFDM PHY baseband modem with parallel architecture","authors":"G. Ramadoss, G. Prakash","doi":"10.1109/ICEVENT.2013.6496541","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496541","url":null,"abstract":"The multi-band orthogonal frequency division multiplexing modem needs to process large amount of computations in short time for support of high data rates from 53 to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi way parallel architecture has been proposed. In this paper introduced several novel optimization techniques for resource efficient implementation of the baseband modem which has 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization techniques could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of entire baseband modem were about 474 kgates and 248 mW at 66 MHz.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"2 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90831528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496538
S. Gnanavel, S. Ramakrishan, N. M. Kumar
A Multimedia transmission such as video streaming over wireless networks has grown dramatically in recent years. The downlink transmission of multiple video sequences to multiple users over a shared resource-limited wireless channel, however, is a tough task. We face many challenges in this area like time-varying channel conditions, limited available resources, such as bandwidth and power, and the different transmission requirements of different video content. This work takes into account the time-varying nature of the wireless channels, as well as the importance of individual video packets, to develop a cross-layer resource allocation and packet scheduling scheme for multiuser video streaming over wireless networks. Assuming that accurate channel feedback is not available at the scheduler, random channel losses combined with complex error concealment at the receiver make it impossible for the scheduler to determine the actual distortion of the sequence at the receiver. Therefore, the objective of the optimization is to minimize the expected distortion of the received sequence, where the expectation is calculated at the scheduler with respect to the packet loss probability in the channel. The expected distortion is used to order the packets in the transmission queue of each user, and then gradients of the expected distortion are used to efficiently allocate resources across users.
{"title":"A cross layer resource allocation for multiuser video transmission over wireless networks","authors":"S. Gnanavel, S. Ramakrishan, N. M. Kumar","doi":"10.1109/ICEVENT.2013.6496538","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496538","url":null,"abstract":"A Multimedia transmission such as video streaming over wireless networks has grown dramatically in recent years. The downlink transmission of multiple video sequences to multiple users over a shared resource-limited wireless channel, however, is a tough task. We face many challenges in this area like time-varying channel conditions, limited available resources, such as bandwidth and power, and the different transmission requirements of different video content. This work takes into account the time-varying nature of the wireless channels, as well as the importance of individual video packets, to develop a cross-layer resource allocation and packet scheduling scheme for multiuser video streaming over wireless networks. Assuming that accurate channel feedback is not available at the scheduler, random channel losses combined with complex error concealment at the receiver make it impossible for the scheduler to determine the actual distortion of the sequence at the receiver. Therefore, the objective of the optimization is to minimize the expected distortion of the received sequence, where the expectation is calculated at the scheduler with respect to the packet loss probability in the channel. The expected distortion is used to order the packets in the transmission queue of each user, and then gradients of the expected distortion are used to efficiently allocate resources across users.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"20 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90908784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496579
V. Vijayalakshmi, R. Seshadri, S. Ramakrishnan
This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31% by the CSLA based multiplier to complete the multiplication operation. These multipliers are implemented using Altera Quartus II and timing diagrams are viewed through avan waves.
{"title":"Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA","authors":"V. Vijayalakshmi, R. Seshadri, S. Ramakrishnan","doi":"10.1109/ICEVENT.2013.6496579","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496579","url":null,"abstract":"This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31% by the CSLA based multiplier to complete the multiplication operation. These multipliers are implemented using Altera Quartus II and timing diagrams are viewed through avan waves.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"104 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87711887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496560
B. Pushparaj, C. Paramasivam
This paper present a high-performance and low-complexity modified radix-25 512-point Fast Fourier transform (FFT) architecture using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix-25 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twiddle factor memory. It also uses a complex constant multiplier instead of a complex Booth multiplier. The results demonstrate that the total gate count of the proposed FFT architecture is 11, 894. Furthermore the highest throughput rate is up to 2.4 GS/s at 310 MHz while requiring much less hardware complexity.
{"title":"High performance and low power modified radix-25 FFT architecture for high rate WPAN application","authors":"B. Pushparaj, C. Paramasivam","doi":"10.1109/ICEVENT.2013.6496560","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496560","url":null,"abstract":"This paper present a high-performance and low-complexity modified radix-25 512-point Fast Fourier transform (FFT) architecture using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix-25 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twiddle factor memory. It also uses a complex constant multiplier instead of a complex Booth multiplier. The results demonstrate that the total gate count of the proposed FFT architecture is 11, 894. Furthermore the highest throughput rate is up to 2.4 GS/s at 310 MHz while requiring much less hardware complexity.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81789022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496593
M. S. Suraj, D. Muralidharan, K. Seshu Kumar
In this work, we present the NOC router architecture with five port support which utilizes dual crossbar arrangement, the latency which arises due to the dual cross bar architecture is reduced by using predominant routing algorithm. This arrangement is more efficient and reduces about 10 % of device utilization.
{"title":"A HDL based reduced area NOC router architecture","authors":"M. S. Suraj, D. Muralidharan, K. Seshu Kumar","doi":"10.1109/ICEVENT.2013.6496593","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496593","url":null,"abstract":"In this work, we present the NOC router architecture with five port support which utilizes dual crossbar arrangement, the latency which arises due to the dual cross bar architecture is reduced by using predominant routing algorithm. This arrangement is more efficient and reduces about 10 % of device utilization.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77019254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：