Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496553
A. Amsavalli, K. R. Kashwan
Authors, in this paper, present a bit error rate analysis and FPGA implementation of multiple access interference cancellation in Code Division Multiple Access (CDMA) communication systems. The main objective of paper is focused on designing and then testing the performance of CDMA circuits implemented on FPGA. Main performance parameter of BER was chosen for simulation. The test performances are analyzed by simulating a CDMA communication system with QPSK modulation and demodulation. The latest technology advancement in cellular mobile communication systems has become more demanding for better quality of service. It requires broad bandwidth for huge quanta of data transfer. CDMA communication system easily meets these requirements of cellular communications. The design of the relevant circuits is based on CDMA approach of direct sequence spread spectrum technology. The functional performance of designed circuits is tested by carrying out simulations using Field Programmable Gate Arrays (FPGA) and Very High Speed Integrated Circuits Hardware Description Language (VHDL) on XILINX ISE® and MATLAB® platforms. The simulated results subsequently have shown quite improved and optimized circuit performance.
{"title":"BER analysis and MAI cancellation in CDMA communication system","authors":"A. Amsavalli, K. R. Kashwan","doi":"10.1109/ICEVENT.2013.6496553","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496553","url":null,"abstract":"Authors, in this paper, present a bit error rate analysis and FPGA implementation of multiple access interference cancellation in Code Division Multiple Access (CDMA) communication systems. The main objective of paper is focused on designing and then testing the performance of CDMA circuits implemented on FPGA. Main performance parameter of BER was chosen for simulation. The test performances are analyzed by simulating a CDMA communication system with QPSK modulation and demodulation. The latest technology advancement in cellular mobile communication systems has become more demanding for better quality of service. It requires broad bandwidth for huge quanta of data transfer. CDMA communication system easily meets these requirements of cellular communications. The design of the relevant circuits is based on CDMA approach of direct sequence spread spectrum technology. The functional performance of designed circuits is tested by carrying out simulations using Field Programmable Gate Arrays (FPGA) and Very High Speed Integrated Circuits Hardware Description Language (VHDL) on XILINX ISE® and MATLAB® platforms. The simulated results subsequently have shown quite improved and optimized circuit performance.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"21 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89625505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496591
G. Sudhagar, S. Senthil Kumar, G. Ramesh, G. Sathish Kumar
Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (Soc.) and have not been fully resolved, even if a scan-based technique is employed. A novel architecture, referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuit-under-test (CUT) and increases the clock frequency of the scanning process. An auxiliary chain is utilized in this architecture to avoid the large number of transitions to the CUT during the scan-in process, as well as enabling retention of the currently applied test vectors and applying only necessary changes to them. It also permits delay fault testing. Using ISCAS 85 and 89 benchmark circuits, the effectiveness of this architecture for improving Soc. test measures (such as, time, and data volume) is experimentally evaluated and confirmed.
{"title":"Implementation of a novel architecture for VLSI testing","authors":"G. Sudhagar, S. Senthil Kumar, G. Ramesh, G. Sathish Kumar","doi":"10.1109/ICEVENT.2013.6496591","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496591","url":null,"abstract":"Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (Soc.) and have not been fully resolved, even if a scan-based technique is employed. A novel architecture, referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuit-under-test (CUT) and increases the clock frequency of the scanning process. An auxiliary chain is utilized in this architecture to avoid the large number of transitions to the CUT during the scan-in process, as well as enabling retention of the currently applied test vectors and applying only necessary changes to them. It also permits delay fault testing. Using ISCAS 85 and 89 benchmark circuits, the effectiveness of this architecture for improving Soc. test measures (such as, time, and data volume) is experimentally evaluated and confirmed.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82925076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496536
V. Anupama, P. Salil
Electromagnetic Interference and Compatibility (EMI/EMC) and Signal Integrity (SI) issues are becoming more and more significant in today's product design with product dimensions going down and complexity ever increasing. One of the contributors to this is the PCB via commonly used in the multilayer PCB. In this paper the issues rising out of the via structure as well as how the via can be used to mitigate the issues is discussed. The vias provide a convenient way for routing electrical connections on different layers of the PCB. The discontinuities introduced by these vias on the PCB trace bring in new Signal Integrity (SI) and Electromagnetic Interference (EMI) related issues. These discontinuities lead to increased coupling and cross talk. This effect is prominent in differential traces containing vias placed nearby. In this paper, studies are carried out to estimate the effect of the via coupling alone separating it from the effect of the coupling from the traces. Different techniques for reducing these effects were tried out using commercially available tools based on numerical computational electromagnetics. The structures were analysed in the 1GHz to 10GHz frequency range. The results were validated using practical measurements.
{"title":"Analysis of different techniques for reduction of SI and emission from PCB trace","authors":"V. Anupama, P. Salil","doi":"10.1109/ICEVENT.2013.6496536","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496536","url":null,"abstract":"Electromagnetic Interference and Compatibility (EMI/EMC) and Signal Integrity (SI) issues are becoming more and more significant in today's product design with product dimensions going down and complexity ever increasing. One of the contributors to this is the PCB via commonly used in the multilayer PCB. In this paper the issues rising out of the via structure as well as how the via can be used to mitigate the issues is discussed. The vias provide a convenient way for routing electrical connections on different layers of the PCB. The discontinuities introduced by these vias on the PCB trace bring in new Signal Integrity (SI) and Electromagnetic Interference (EMI) related issues. These discontinuities lead to increased coupling and cross talk. This effect is prominent in differential traces containing vias placed nearby. In this paper, studies are carried out to estimate the effect of the via coupling alone separating it from the effect of the coupling from the traces. Different techniques for reducing these effects were tried out using commercially available tools based on numerical computational electromagnetics. The structures were analysed in the 1GHz to 10GHz frequency range. The results were validated using practical measurements.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"77 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83861475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496582
T. Senthilkumar, G. Prakash
This paper proposes a novel modified reverse converter for the unrestricted moduli set. This uses to investigate the Residue Number System (RNS) to decimal equivalent binary conversion for the utilization of RNS numbers in Digital Signal Processing (DSP) applications. First, we simplify the Chinese Remainder Theorem in order to obtain a reverse converter that uses mod-(2n-1) operations. Next, we further analyze the theorem for the low complexity implementation that does not require the explicit use of modulo operation in the conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. The proposed converter is implemented on Xilinx Spartan 3 field-programmable gate array. The results indicate that the proposal shows the better performance in conversion time, area cost and power consumption.
{"title":"A novel FPGA design of modified residue to binary converter for three moduli set","authors":"T. Senthilkumar, G. Prakash","doi":"10.1109/ICEVENT.2013.6496582","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496582","url":null,"abstract":"This paper proposes a novel modified reverse converter for the unrestricted moduli set. This uses to investigate the Residue Number System (RNS) to decimal equivalent binary conversion for the utilization of RNS numbers in Digital Signal Processing (DSP) applications. First, we simplify the Chinese Remainder Theorem in order to obtain a reverse converter that uses mod-(2n-1) operations. Next, we further analyze the theorem for the low complexity implementation that does not require the explicit use of modulo operation in the conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. The proposed converter is implemented on Xilinx Spartan 3 field-programmable gate array. The results indicate that the proposal shows the better performance in conversion time, area cost and power consumption.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76237530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496589
Dhruva Kumari, Monisha SaW, Aminul Islam
Spintronic devices are based on the up and down spin of an electron rather than on the charge of electrons as in traditional electronic devices. In principle, they primarily have higher speed, low power consumption, non-volatile storage and high integration density as compared to transistor based devices. A Magnetic Tunnel Junction (MTJ) is one such spintronic device which is not only used for memory storage but also for computation of logic functions. A multiplexer is an integral part of various digital logic circuits such as a FPGA. In the present paper, a novel architecture of a 2:1 multiplexer using only two MTJ elements, interconnected by a nano-magnetic channel has been designed. The corresponding demultiplexer has also been presented. HSPICE simulation is shown to verify the functionalities of the proposed circuits.
{"title":"Design of 2∶1 multiplexer and 1∶2 demultiplexer using magnetic tunnel junction elements","authors":"Dhruva Kumari, Monisha SaW, Aminul Islam","doi":"10.1109/ICEVENT.2013.6496589","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496589","url":null,"abstract":"Spintronic devices are based on the up and down spin of an electron rather than on the charge of electrons as in traditional electronic devices. In principle, they primarily have higher speed, low power consumption, non-volatile storage and high integration density as compared to transistor based devices. A Magnetic Tunnel Junction (MTJ) is one such spintronic device which is not only used for memory storage but also for computation of logic functions. A multiplexer is an integral part of various digital logic circuits such as a FPGA. In the present paper, a novel architecture of a 2:1 multiplexer using only two MTJ elements, interconnected by a nano-magnetic channel has been designed. The corresponding demultiplexer has also been presented. HSPICE simulation is shown to verify the functionalities of the proposed circuits.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"174 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73921035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496580
T. S. Arun Samuel, N. Balamurugan
In this paper, a new two dimensional (2D) analytical model of the single gate (SG) silicon-on-insulator (SOI) tunnel field effect transistors (TFETs) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. Analytical expressions for surface potential and electric field are derived. The validity of the proposed model is tested for device scaled to 18-nm length and the analytical results are compared with TCAD simulations.
{"title":"Potential and electric field model for 18 nm SG tunnel field effect transistor","authors":"T. S. Arun Samuel, N. Balamurugan","doi":"10.1109/ICEVENT.2013.6496580","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496580","url":null,"abstract":"In this paper, a new two dimensional (2D) analytical model of the single gate (SG) silicon-on-insulator (SOI) tunnel field effect transistors (TFETs) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. Analytical expressions for surface potential and electric field are derived. The validity of the proposed model is tested for device scaled to 18-nm length and the analytical results are compared with TCAD simulations.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74090145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496585
M. Sagana Gandi, M. Karthigai Pandian, N. Balamurugan
This paper deals with the study of modelling double gate silicon nanowire transistors. The scaling of nanowire transistors to 10nm and below is discussed for acceptable short-channel effects and the quantum mechanical effects caused by ultrathin silicon devices considered in modelling the threshold voltage is studied. Similarly, the variation of threshold voltage with different doping density, channel length, channel thickness and oxide thickness of DG MOSFET are analysed. The inversion charge and electrical potential along the channel of double gate MOSFET are also discussed in this paper. These approaches analysed are based upon the analytical solutions of Schrödinger and Poisson equations solved in the silicon channel. The simulation results obtained from various methodologies are compared to analyze the performance of the DG MOSFETs.
{"title":"High performance double gate silicon nanowire transistors","authors":"M. Sagana Gandi, M. Karthigai Pandian, N. Balamurugan","doi":"10.1109/ICEVENT.2013.6496585","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496585","url":null,"abstract":"This paper deals with the study of modelling double gate silicon nanowire transistors. The scaling of nanowire transistors to 10nm and below is discussed for acceptable short-channel effects and the quantum mechanical effects caused by ultrathin silicon devices considered in modelling the threshold voltage is studied. Similarly, the variation of threshold voltage with different doping density, channel length, channel thickness and oxide thickness of DG MOSFET are analysed. The inversion charge and electrical potential along the channel of double gate MOSFET are also discussed in this paper. These approaches analysed are based upon the analytical solutions of Schrödinger and Poisson equations solved in the silicon channel. The simulation results obtained from various methodologies are compared to analyze the performance of the DG MOSFETs.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"23 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80777666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496594
R. Krishnamurthy, B. S. Samuel, R. Rajasekaran
Potassium Dihydrogen Phosphate (KDP) doped with L-glutamic acid has been grown by solvent slow evaporation technique from a mixture of aqueous solution of KDP and 1.0 mol% of L-Glutamic acid at room temperature. The grown crystals were characterized by powder X-ray diffraction and UV-visible. The The Nonlinear optical property (SHG) of L-glutamic acid doped KDP has been confirmed. Microhardness studies were carried out on the grown crystal.
{"title":"Growth and characterization of KDP crystals doped with L-Glutamic acid","authors":"R. Krishnamurthy, B. S. Samuel, R. Rajasekaran","doi":"10.1109/ICEVENT.2013.6496594","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496594","url":null,"abstract":"Potassium Dihydrogen Phosphate (KDP) doped with L-glutamic acid has been grown by solvent slow evaporation technique from a mixture of aqueous solution of KDP and 1.0 mol% of L-Glutamic acid at room temperature. The grown crystals were characterized by powder X-ray diffraction and UV-visible. The The Nonlinear optical property (SHG) of L-glutamic acid doped KDP has been confirmed. Microhardness studies were carried out on the grown crystal.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88756356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496564
D. Samidha, D. Agrawal
Steganography is an art of hiding information in some media. This paper describes various image steganography techniques, based on spatial domain and by considering pixel values in binary format. Spatial domain is based on physical location of pixels in an image. Generally 8 bit gray level or colour images can be used as a cover to hide data. Again binary representations of these pixels are considered to hide secret information. Random bits from these bytes are used to replace the bits of secret. In this paper, many steganography techniques can be used like Least Significant Bit (LSB), layout management schemes, replacing only 1's or only zero's from lower nibble from the byte are considered for hiding secret message in an image. Along with these techniques, some more methods are proposed, based on selection of random pixels from an image and again secret data is hidden in random bits of these randomly selected pixels. For this purpose, many parameters of an image are considered like physical location of pixels, intensity value of pixel, etc.
{"title":"Random image steganography in spatial domain","authors":"D. Samidha, D. Agrawal","doi":"10.1109/ICEVENT.2013.6496564","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496564","url":null,"abstract":"Steganography is an art of hiding information in some media. This paper describes various image steganography techniques, based on spatial domain and by considering pixel values in binary format. Spatial domain is based on physical location of pixels in an image. Generally 8 bit gray level or colour images can be used as a cover to hide data. Again binary representations of these pixels are considered to hide secret information. Random bits from these bytes are used to replace the bits of secret. In this paper, many steganography techniques can be used like Least Significant Bit (LSB), layout management schemes, replacing only 1's or only zero's from lower nibble from the byte are considered for hiding secret message in an image. Along with these techniques, some more methods are proposed, based on selection of random pixels from an image and again secret data is hidden in random bits of these randomly selected pixels. For this purpose, many parameters of an image are considered like physical location of pixels, intensity value of pixel, etc.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87392144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496540
S. Parija, R. Ranjan, P. K. Sahu
This work describes the neural network technique to solve location management problem. A multilayer neural model is designed to predict the future prediction of the subscriber based on the past predicted information of the subscriber. In this paper a prediction based location management scheme is proposed for locating a mobile terminal in a communication without losing quality maintain a good response. There are various methods of location management schemes for prediction of the mobile user. Based on individual characteristic of the user, prediction based location management can be implemented. This work is purely analytical which need the past movement of the subscriber. The movement of the mobile target is considered as regular and uniform. An artificial neural network model is used for mobility management to reducing the total cost. Single or multiple mobile targets can be predicted. Among all the neural techniques multilayer perceptron is used for this work. The records is collected from the past movement and is used to train the network for the future prediction. The analytical result of the prediction method is found to be satisfactory.
{"title":"Location prediction of mobility management using neural network techniques in cellular network","authors":"S. Parija, R. Ranjan, P. K. Sahu","doi":"10.1109/ICEVENT.2013.6496540","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496540","url":null,"abstract":"This work describes the neural network technique to solve location management problem. A multilayer neural model is designed to predict the future prediction of the subscriber based on the past predicted information of the subscriber. In this paper a prediction based location management scheme is proposed for locating a mobile terminal in a communication without losing quality maintain a good response. There are various methods of location management schemes for prediction of the mobile user. Based on individual characteristic of the user, prediction based location management can be implemented. This work is purely analytical which need the past movement of the subscriber. The movement of the mobile target is considered as regular and uniform. An artificial neural network model is used for mobility management to reducing the total cost. Single or multiple mobile targets can be predicted. Among all the neural techniques multilayer perceptron is used for this work. The records is collected from the past movement and is used to train the network for the future prediction. The analytical result of the prediction method is found to be satisfactory.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84744046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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