Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496571
G. Shiva, N. R. Raajan, G. N. Jayabhavani
We are on the verge of universally adopting Augmented Reality (AR) technologies to augment our perception and help us see, feel, and hear our environments in enriched and new ways as Augmented Reality (AR). Simply we can say that it's a combination of a virtual object or 3D objects which are overlaid on live camera feed information. It is not only smart phones looking at some pictures we will have videos sounds vocals and even several other kind of technologies we couldn't imagine. We are incorporating a new efficient solution for integrating a virtual thing (3D video) on to the real world which can be very much handful for tourism and advertisement for showcasing objects or things. The ultimate goal of this paper is to augmenting the 3D video onto a real world on which it will increase the person's conceptual understanding of the subject. For performing this, various methods have been used like model based and feature based methods for making a connection between the 3D object coordinates and the 2D coordinates which are obtained on processing the live camera feed information.
{"title":"Augmented Reality based 3D commercial advertisements","authors":"G. Shiva, N. R. Raajan, G. N. Jayabhavani","doi":"10.1109/ICEVENT.2013.6496571","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496571","url":null,"abstract":"We are on the verge of universally adopting Augmented Reality (AR) technologies to augment our perception and help us see, feel, and hear our environments in enriched and new ways as Augmented Reality (AR). Simply we can say that it's a combination of a virtual object or 3D objects which are overlaid on live camera feed information. It is not only smart phones looking at some pictures we will have videos sounds vocals and even several other kind of technologies we couldn't imagine. We are incorporating a new efficient solution for integrating a virtual thing (3D video) on to the real world which can be very much handful for tourism and advertisement for showcasing objects or things. The ultimate goal of this paper is to augmenting the 3D video onto a real world on which it will increase the person's conceptual understanding of the subject. For performing this, various methods have been used like model based and feature based methods for making a connection between the 3D object coordinates and the 2D coordinates which are obtained on processing the live camera feed information.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72729817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496578
Y. Lavania, G. Varghese, K. Mahapatra
This investigation suggests a low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital converter. One of the demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this paper converts the thermometer code into binary code without any intermediate stage. To decrease the power consumption of the encoder, the implementation is done using dynamic CMOS logic. The proposed encoder is designed using 90 nm technology at 1.2 V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 4GHz and the average power dissipation of the encoder is 1.833 μW.
{"title":"An ultra low power encoder for 5 bit flash ADC","authors":"Y. Lavania, G. Varghese, K. Mahapatra","doi":"10.1109/ICEVENT.2013.6496578","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496578","url":null,"abstract":"This investigation suggests a low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital converter. One of the demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this paper converts the thermometer code into binary code without any intermediate stage. To decrease the power consumption of the encoder, the implementation is done using dynamic CMOS logic. The proposed encoder is designed using 90 nm technology at 1.2 V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 4GHz and the average power dissipation of the encoder is 1.833 μW.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85233352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496558
Dinakardas En, Perumal Sankar, Nisha George
In this paper, we present a multimodal face recognition system that fuses results from both Principal Component Analysis, Fisherface projections, minutia extraction and LBP feature extraction on different biometric traits. The proposed identification system uses the face, fingerprint and iris of a person for recognizing a person. We use two different methods for comparing the performance. The first model used principal component analysis to extract the features of the fingerprint and iris image and fisherfaces for the face image. The second method used fisherface for face, minutiae extraction for fingerprint and LBP feature for iris image. The developed multimodal biometric system possesses a number of unique qualities, starting from utilizing principal component analysis and Fisher's linear discriminant methods for individual matchers identity authentication and utilizes the novel feature fusion method to consolidate the results obtained from different biometric matchers. Two fusion strategies are experimentally compared. The proposed approaches is tested on a real database consisting of 500 images and shows promising results compared to other techniques. The Receiver Operating Characteristics also shows that the proposed methods are superior compared to other techniques under study.
{"title":"A multimodal performance evaluation on two different models based on face, fingerprint and iris templates","authors":"Dinakardas En, Perumal Sankar, Nisha George","doi":"10.1109/ICEVENT.2013.6496558","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496558","url":null,"abstract":"In this paper, we present a multimodal face recognition system that fuses results from both Principal Component Analysis, Fisherface projections, minutia extraction and LBP feature extraction on different biometric traits. The proposed identification system uses the face, fingerprint and iris of a person for recognizing a person. We use two different methods for comparing the performance. The first model used principal component analysis to extract the features of the fingerprint and iris image and fisherfaces for the face image. The second method used fisherface for face, minutiae extraction for fingerprint and LBP feature for iris image. The developed multimodal biometric system possesses a number of unique qualities, starting from utilizing principal component analysis and Fisher's linear discriminant methods for individual matchers identity authentication and utilizes the novel feature fusion method to consolidate the results obtained from different biometric matchers. Two fusion strategies are experimentally compared. The proposed approaches is tested on a real database consisting of 500 images and shows promising results compared to other techniques. The Receiver Operating Characteristics also shows that the proposed methods are superior compared to other techniques under study.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85881151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496575
A. Ramesh, A. Tilak, A. M. Prasad
Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
{"title":"An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog","authors":"A. Ramesh, A. Tilak, A. M. Prasad","doi":"10.1109/ICEVENT.2013.6496575","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496575","url":null,"abstract":"Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87137541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496555
R. Pushpavalli, G. Sivarajde
An intelligent filtering technique for image enhancement is proposed in this paper. The proposed intelligent filter is carried out in two stages. In first stage the corrupted image is filtered by applying a special class of switching median filter. Filtered output image is suitably combined with a feed forward neural network in the second stage. The internal parameters of the feed forward neural network are adaptively optimized by training for three well known images. This is quite effective in eliminating impulse noise. Simulation results show that the proposed filter is superior in terms of eliminating impulse noise as well as preserving edges and fine details of digital images. The results are compared with other existing filters for performance evaluation.
{"title":"An intelligent post processing technique for image enhancement","authors":"R. Pushpavalli, G. Sivarajde","doi":"10.1109/ICEVENT.2013.6496555","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496555","url":null,"abstract":"An intelligent filtering technique for image enhancement is proposed in this paper. The proposed intelligent filter is carried out in two stages. In first stage the corrupted image is filtered by applying a special class of switching median filter. Filtered output image is suitably combined with a feed forward neural network in the second stage. The internal parameters of the feed forward neural network are adaptively optimized by training for three well known images. This is quite effective in eliminating impulse noise. Simulation results show that the proposed filter is superior in terms of eliminating impulse noise as well as preserving edges and fine details of digital images. The results are compared with other existing filters for performance evaluation.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79057805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496576
R. Anjana, Ajay Kumar Somkuwar
Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap for Semiconductors (IRTS). This directly affects the battery operated devices as it has long idle times. Thus by scaling down the threshold voltage has tremendously increased the sub threshold leakage current thereby making the static power dissipation very high. To overcome this problem several techniques has been proposed to overcome this high leakage power dissipation. A comprehensive survey and analysis of various leakage power minimization techniques is presented in this paper. Of the available techniques, eight techniques are considered for the analysis namely, Multi Threshold CMOS (MTCMOS), Super Cut-off CMOS (SCCMOS), Forced Transistor Stacking (FTS) and Sleepy Stack (SS), Sleepy keeper (SK), Dual Stack (DS), Input Vector Control (IVC) and LECTOR. From the results, it is observed that MTCMOS and SCCMOS techniques produces lower power dissipation than the other techniques due to the ability of power gating.
{"title":"Analysis of sub threshold leakage reduction techniques in deep sub micron regime for CMOS VLSI circuits","authors":"R. Anjana, Ajay Kumar Somkuwar","doi":"10.1109/ICEVENT.2013.6496576","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496576","url":null,"abstract":"Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap for Semiconductors (IRTS). This directly affects the battery operated devices as it has long idle times. Thus by scaling down the threshold voltage has tremendously increased the sub threshold leakage current thereby making the static power dissipation very high. To overcome this problem several techniques has been proposed to overcome this high leakage power dissipation. A comprehensive survey and analysis of various leakage power minimization techniques is presented in this paper. Of the available techniques, eight techniques are considered for the analysis namely, Multi Threshold CMOS (MTCMOS), Super Cut-off CMOS (SCCMOS), Forced Transistor Stacking (FTS) and Sleepy Stack (SS), Sleepy keeper (SK), Dual Stack (DS), Input Vector Control (IVC) and LECTOR. From the results, it is observed that MTCMOS and SCCMOS techniques produces lower power dissipation than the other techniques due to the ability of power gating.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79501611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-11DOI: 10.1109/ICEVENT.2013.6496583
M. Regila Manohari, M. Karthigai Pandian, N. Balamurugan
In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.
{"title":"Performance analysis and threshold voltage modeling of Surrounding Gate Silicon Nanowire Transistors","authors":"M. Regila Manohari, M. Karthigai Pandian, N. Balamurugan","doi":"10.1109/ICEVENT.2013.6496583","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496583","url":null,"abstract":"In this paper the threshold voltage models proposed for the modeling of Surrounding Gate Silicon Nanowire Transistors are reviewed. The control of short channel effects as a challenging aspect and performance limits are also presented in this review paper. A number of threshold voltage models based on various device parameters and their results are summarized and comparative study has been done. Here mainly the impact of the gate length, the surface potential, and the damaged zone length on the threshold voltage are analyzed. Parabolic potential approximation and perimeter weighted summation method are the two known methods for the threshold voltage analysis of surrounding gate MOSFETs. Simulation results are compared with the values obtained from standard numerical simulators.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89576715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-01-01DOI: 10.1109/ICEVENT.2013.6496574
S. Ananthi, K. Padmanabhan, K. R. Balaji
Digital data communication uses various modes of encoding the data bits into a frequency signal. Phase shift keying (PSK) of various forms such as Binary PSK, Quaternary PSK etc., are in vogue in several current communication schemes such as GSM. In this paper, a different scheme of encoding digital data using wavelet functions instead of sinusoidal waves is explained. Errors in bits at the received end through a radio channel are common in such data communication. These errors are mainly caused by improper phase changes in the detected audio signal. Since the method presented here with the use of Wavelet functions provides several clues for identification of the data symbol instead of just by one criterion viz., the phase of the carrier as in the PSK schemes, this method is found to be better in performance. Simulation of the scheme was made with Matlab and some preliminary results are presented.
{"title":"A different scheme of encoding data bits in digital communication using wavelets","authors":"S. Ananthi, K. Padmanabhan, K. R. Balaji","doi":"10.1109/ICEVENT.2013.6496574","DOIUrl":"https://doi.org/10.1109/ICEVENT.2013.6496574","url":null,"abstract":"Digital data communication uses various modes of encoding the data bits into a frequency signal. Phase shift keying (PSK) of various forms such as Binary PSK, Quaternary PSK etc., are in vogue in several current communication schemes such as GSM. In this paper, a different scheme of encoding digital data using wavelet functions instead of sinusoidal waves is explained. Errors in bits at the received end through a radio channel are common in such data communication. These errors are mainly caused by improper phase changes in the detected audio signal. Since the method presented here with the use of Wavelet functions provides several clues for identification of the data symbol instead of just by one criterion viz., the phase of the carrier as in the PSK schemes, this method is found to be better in performance. Simulation of the scheme was made with Matlab and some preliminary results are presented.","PeriodicalId":6426,"journal":{"name":"2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75122894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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