Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356465
Zin Mar Kyu, T. Nyunt
XML is playing an increasingly important role in the exchange of a wide variety of data on the Web. The volume of XML data exchange is explosively increasing, and the need for efficient mechanisms of XML data management is vital. One of the most popular used of XML is as a data storage facility. Many XML storage models have been proposed for storing XML data in relational database systems. In this paper, we present how to create dynamic relational schema and store XML data only depend on input XML document. For this process, we propose DTD-independent schema mapping algorithm and data mapping algorithm. Our DTD-independent schema mapping algorithm uses data extraction approach that extracts table names and attributes of the input XML document to create a document schema, and data mapping algorithm stores all extracted XML information into relational tables by mapping outputs of DTD-independent schema mapping algorithm. Our proposed system reduce the step of creating relational schema depend on DTD information. So we do not need DTD information , can solve the problem of missing elements and attributes of inputs DTD and XML document, and will get similar result of DTD-dependent approach.
{"title":"Storing DTD-independent XML data in relational database","authors":"Zin Mar Kyu, T. Nyunt","doi":"10.1109/ISIEA.2009.5356465","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356465","url":null,"abstract":"XML is playing an increasingly important role in the exchange of a wide variety of data on the Web. The volume of XML data exchange is explosively increasing, and the need for efficient mechanisms of XML data management is vital. One of the most popular used of XML is as a data storage facility. Many XML storage models have been proposed for storing XML data in relational database systems. In this paper, we present how to create dynamic relational schema and store XML data only depend on input XML document. For this process, we propose DTD-independent schema mapping algorithm and data mapping algorithm. Our DTD-independent schema mapping algorithm uses data extraction approach that extracts table names and attributes of the input XML document to create a document schema, and data mapping algorithm stores all extracted XML information into relational tables by mapping outputs of DTD-independent schema mapping algorithm. Our proposed system reduce the step of creating relational schema depend on DTD information. So we do not need DTD information , can solve the problem of missing elements and attributes of inputs DTD and XML document, and will get similar result of DTD-dependent approach.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"16 1","pages":"197-202"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81674592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356325
Mahanijah Md. Kamal, N. Mamat
The objective of this paper is to design a controller for servo motor in discrete-time systems. The effect of sampling time on the proposed design will further discussed. Real-time data gained from the experimental is used to obtain the transfer function to design the PID controller. In order to get the optimal value of PID controller, ARX model structure was implemented. The effectiveness of the design is validated using MATLAB/Simulink. From the results obtained, it shows that the output for PID controller will gives the best performance of 87.79% at 55 ms sampling time.
{"title":"Controller design for servo motor","authors":"Mahanijah Md. Kamal, N. Mamat","doi":"10.1109/ISIEA.2009.5356325","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356325","url":null,"abstract":"The objective of this paper is to design a controller for servo motor in discrete-time systems. The effect of sampling time on the proposed design will further discussed. Real-time data gained from the experimental is used to obtain the transfer function to design the PID controller. In order to get the optimal value of PID controller, ARX model structure was implemented. The effectiveness of the design is validated using MATLAB/Simulink. From the results obtained, it shows that the output for PID controller will gives the best performance of 87.79% at 55 ms sampling time.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"41 1","pages":"926-929"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74658513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356339
M. Murugappan, R. Nagarajan, S. Yaacob
In recent years, estimation of human emotions from Electroencephalogram (EEG) signals plays a vital role on developing intellectual Brain Computer Interface (BCI) devices. In this work, we have collected the EEG signals using 64 channels from 20 subjects in the age group of 21~39 years for determining discrete emotions (happy, surprise, fear, disgust, and neutral) under audio-visual induction (video/film clips) stimuli. Surface Laplacian filtering is used to preprocess the EEG signals and decomposed into five different EEG frequency bands (delta, theta, alpha, beta, and gamma) using Wavelet Transform (WT). The statistical features are derived from all these five frequency bands are considered for classifying the emotions using two linear classifiers (K Nearest Neighbor (KNN) & Linear Discriminant Analysis (LDA)). The main objective of this work is to consider a selected number of 24 channels for assessing emotions from the original EEG channels. There are three different wavelet functions (“db8”, “sym8”, and “coif5”) are used to derive the linear and non linear features for emotion classification. The validation of statistical features is performed using 5 fold cross validation. In this work, KNN outperforms LDA by offering a maximum average classification rate of 79.174 %. Finally we present the average and individual classification rate of emotions over various statistical features on three different wavelet functions for justifying the performance of our emotion recognition system.
{"title":"Comparison of different wavelet features from EEG signals for classifying human emotions","authors":"M. Murugappan, R. Nagarajan, S. Yaacob","doi":"10.1109/ISIEA.2009.5356339","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356339","url":null,"abstract":"In recent years, estimation of human emotions from Electroencephalogram (EEG) signals plays a vital role on developing intellectual Brain Computer Interface (BCI) devices. In this work, we have collected the EEG signals using 64 channels from 20 subjects in the age group of 21~39 years for determining discrete emotions (happy, surprise, fear, disgust, and neutral) under audio-visual induction (video/film clips) stimuli. Surface Laplacian filtering is used to preprocess the EEG signals and decomposed into five different EEG frequency bands (delta, theta, alpha, beta, and gamma) using Wavelet Transform (WT). The statistical features are derived from all these five frequency bands are considered for classifying the emotions using two linear classifiers (K Nearest Neighbor (KNN) & Linear Discriminant Analysis (LDA)). The main objective of this work is to consider a selected number of 24 channels for assessing emotions from the original EEG channels. There are three different wavelet functions (“db8”, “sym8”, and “coif5”) are used to derive the linear and non linear features for emotion classification. The validation of statistical features is performed using 5 fold cross validation. In this work, KNN outperforms LDA by offering a maximum average classification rate of 79.174 %. Finally we present the average and individual classification rate of emotions over various statistical features on three different wavelet functions for justifying the performance of our emotion recognition system.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"65 1","pages":"836-841"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80705846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356425
A. Besari, Ruzaidi Zamri, Ahmad Yusaeri, Md.Dan Md.Palil, A. S. Prabuwono
Water is something that is so cheap yet we take it for granted, but we need to conserve this life-sustaining resource. Based on research, a Muslim will use six to nine liters of water during ablution, adding that only two liters of water was used for the whole ritual. Because of that we need a machine that would enable Muslims to save water every time they perform the pre-prayer cleansing ritual. This machine allowed a Muslim to perform the cleansing ritual without water spillage and is environment-friendly as it encouraged water conservation. This machine use camera as sensor and servo motor as an actuator that is embedded on crane to turn and open it based on and object under the crane. It means that if there is an object under the crane, it will be opened, and when there is no object under the crane, it will be closed. Not just open and close the crane, we also use an adaptive method that detect how much water that Muslim need in ablution, example the amount of water that is needed for rinse the mouth of course is more than wash the nose. Not only for ablution, this machine can be implemented in every field, hand wash, kitchen, bathroom, wherever place whether there is crane there in order to protect water and environments.
{"title":"Automatic ablution machine using vision sensor","authors":"A. Besari, Ruzaidi Zamri, Ahmad Yusaeri, Md.Dan Md.Palil, A. S. Prabuwono","doi":"10.1109/ISIEA.2009.5356425","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356425","url":null,"abstract":"Water is something that is so cheap yet we take it for granted, but we need to conserve this life-sustaining resource. Based on research, a Muslim will use six to nine liters of water during ablution, adding that only two liters of water was used for the whole ritual. Because of that we need a machine that would enable Muslims to save water every time they perform the pre-prayer cleansing ritual. This machine allowed a Muslim to perform the cleansing ritual without water spillage and is environment-friendly as it encouraged water conservation. This machine use camera as sensor and servo motor as an actuator that is embedded on crane to turn and open it based on and object under the crane. It means that if there is an object under the crane, it will be opened, and when there is no object under the crane, it will be closed. Not just open and close the crane, we also use an adaptive method that detect how much water that Muslim need in ablution, example the amount of water that is needed for rinse the mouth of course is more than wash the nose. Not only for ablution, this machine can be implemented in every field, hand wash, kitchen, bathroom, wherever place whether there is crane there in order to protect water and environments.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"62 1","pages":"506-509"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80884414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356476
Bi Xin, Jinsong Du, Fan Wei
Data Acquisition System (DAS) is a fundamental functional part in every radar application, especially when used for high range resolution radar system. This paper presents a high speed and reliable DAS of a High range Resolution Radar used for Acquiring Traffic flow Information (HRRATI). The system uses high performance Field Programmable Gate Array (FPGA) to cope with the data transformed by the high speed 8-bits Analog-to-Digital Converter (ADC08D500), which performs digitization of the dual channels radar echo signals with sampling rate at 500MHz. The signal bandwidth up to 180MHz in each channel, then the system preprocesses all the data onboard in real time. In view of the broad bandwidth of the signal and high sampling rate, clock jitter, signal integrity and EMI/EMC issues assume great importance and pose a great challenge to the Printed Circuit Board (PCB) design. This paper gives a thorough investigation of such problems. Finally, clock jitter and ENOB test experiment results show that the DAS is capable of sampling the radar signal effectively.
{"title":"Design and implementation of an ultra-high speed data acquisition system for HRRATI","authors":"Bi Xin, Jinsong Du, Fan Wei","doi":"10.1109/ISIEA.2009.5356476","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356476","url":null,"abstract":"Data Acquisition System (DAS) is a fundamental functional part in every radar application, especially when used for high range resolution radar system. This paper presents a high speed and reliable DAS of a High range Resolution Radar used for Acquiring Traffic flow Information (HRRATI). The system uses high performance Field Programmable Gate Array (FPGA) to cope with the data transformed by the high speed 8-bits Analog-to-Digital Converter (ADC08D500), which performs digitization of the dual channels radar echo signals with sampling rate at 500MHz. The signal bandwidth up to 180MHz in each channel, then the system preprocesses all the data onboard in real time. In view of the broad bandwidth of the signal and high sampling rate, clock jitter, signal integrity and EMI/EMC issues assume great importance and pose a great challenge to the Printed Circuit Board (PCB) design. This paper gives a thorough investigation of such problems. Finally, clock jitter and ENOB test experiment results show that the DAS is capable of sampling the radar signal effectively.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"247 1","pages":"89-93"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77592633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356405
N. Yahaya, K. M. Begam, M. Awan
This paper discusses about the effects of switching frequency where reduction in losses is significant to the converter's performance. The proposed zero-voltage-switching synchronous buck converter circuit is compared with the conventional synchronous buck converter by applying different frequency ranging from 250 kHz to 1.25 MHz. PSpice simulation is carried out using fixed delay control scheme. It is found that the proposed circuit improves the switching speed by at least 50 % in both turn-off and turn-on transitions. In addition, more than 57 % in switching losses have been reduced. Having a low body diode conduction time, the proposed converter can maintain low loss with minimized dead time delay, indicating suitability in operating at high switching frequency.
{"title":"Investigation of high frequency effects on soft-switched synchronous rectifier buck converter","authors":"N. Yahaya, K. M. Begam, M. Awan","doi":"10.1109/ISIEA.2009.5356405","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356405","url":null,"abstract":"This paper discusses about the effects of switching frequency where reduction in losses is significant to the converter's performance. The proposed zero-voltage-switching synchronous buck converter circuit is compared with the conventional synchronous buck converter by applying different frequency ranging from 250 kHz to 1.25 MHz. PSpice simulation is carried out using fixed delay control scheme. It is found that the proposed circuit improves the switching speed by at least 50 % in both turn-off and turn-on transitions. In addition, more than 57 % in switching losses have been reduced. Having a low body diode conduction time, the proposed converter can maintain low loss with minimized dead time delay, indicating suitability in operating at high switching frequency.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"12 1","pages":"525-529"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87792685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356462
R. Murugesan, S. Ramadass, R. Budiarto
IPv6 has extended features with a host of advantages when compared to IPv4 which could be capitalized to leverage on today's communication needs. Apart from its advantages, IPv6 header size has increased to twice the size of a typical IPv4 header resulting in increased overhead. IPv6 includes IPSec which adds further overhead and reduces network performance. The increased header size and IPSec in IPv6 would increase bandwidth utilization, increase latency and reduce throughput for IPv6 traffic. Devising appropriate methods to offset this increased overhead will significantly improve the performance of IPv6 packet transmission depending on the traffic being transferred. Based on our ongoing research, we present a customized IPv6 header for packet transmission over a LAN. The customized IPv6 header reduces the size of the IPv6 packet header. The reduction in header size will significantly improve the performance of small sized IPv6 packets that are dominantly present over a LAN in terms of bandwidth savings, better response time and increased throughput.
{"title":"Improving the performance of IPv6 packet transmission over LAN","authors":"R. Murugesan, S. Ramadass, R. Budiarto","doi":"10.1109/ISIEA.2009.5356462","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356462","url":null,"abstract":"IPv6 has extended features with a host of advantages when compared to IPv4 which could be capitalized to leverage on today's communication needs. Apart from its advantages, IPv6 header size has increased to twice the size of a typical IPv4 header resulting in increased overhead. IPv6 includes IPSec which adds further overhead and reduces network performance. The increased header size and IPSec in IPv6 would increase bandwidth utilization, increase latency and reduce throughput for IPv6 traffic. Devising appropriate methods to offset this increased overhead will significantly improve the performance of IPv6 packet transmission depending on the traffic being transferred. Based on our ongoing research, we present a customized IPv6 header for packet transmission over a LAN. The customized IPv6 header reduces the size of the IPv6 packet header. The reduction in header size will significantly improve the performance of small sized IPv6 packets that are dominantly present over a LAN in terms of bandwidth savings, better response time and increased throughput.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"C-17 1","pages":"182-187"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85036497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356319
C. Moo, Chun K. Huang, Kuo-Hsing Lee, Dai J. Huang
A novel electronic ballast with a repeatedly resonating ignition circuit is proposed for metal halide lamp (MHL). The proposed electronic ballast features a two-stage structure that comprises a power factor corrector and a full-bridge inverter used for current control, filtering and ignition. The full-bridge inverter consists of a low-frequency leg with unilateral switches and a high- frequency leg with bidirectional switches. During starting, the low-frequency side performs repetitive resonance on a resonant energy tank to accumulate a high ignition voltage. At the steady state, the resonant energy tank serves as a filter to drive the lamp with a low-frequency square-wave current. A prototype is designed for 150-W metal halide lamps. Experimental results demonstrate that the proposed electronic ballast is capable of tackling the demanding staring transient and steady state operation.
{"title":"Two-stage electronic ballast for metal halide lamps with embedded buck-conversion and ignition circuit","authors":"C. Moo, Chun K. Huang, Kuo-Hsing Lee, Dai J. Huang","doi":"10.1109/ISIEA.2009.5356319","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356319","url":null,"abstract":"A novel electronic ballast with a repeatedly resonating ignition circuit is proposed for metal halide lamp (MHL). The proposed electronic ballast features a two-stage structure that comprises a power factor corrector and a full-bridge inverter used for current control, filtering and ignition. The full-bridge inverter consists of a low-frequency leg with unilateral switches and a high- frequency leg with bidirectional switches. During starting, the low-frequency side performs repetitive resonance on a resonant energy tank to accumulate a high ignition voltage. At the steady state, the resonant energy tank serves as a filter to drive the lamp with a low-frequency square-wave current. A prototype is designed for 150-W metal halide lamps. Experimental results demonstrate that the proposed electronic ballast is capable of tackling the demanding staring transient and steady state operation.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"27 1","pages":"895-899"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91179673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356468
Wael Abdulal, Omar Al Jadaan, Ahmad Jabas, S. Ramachandram
In most cases, the number of resources and tasks in Grid Computing environment is large. Accordingly, the complexity of task scheduling is significantly increased. This results very complex optimization problem.
{"title":"An improved rank-based genetic algorithm with limited iterations for grid scheduling","authors":"Wael Abdulal, Omar Al Jadaan, Ahmad Jabas, S. Ramachandram","doi":"10.1109/ISIEA.2009.5356468","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356468","url":null,"abstract":"In most cases, the number of resources and tasks in Grid Computing environment is large. Accordingly, the complexity of task scheduling is significantly increased. This results very complex optimization problem.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"109 1","pages":"215-220"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79253450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/ISIEA.2009.5356440
H. M. Hanafi, M. K. Hamzah, N. R. Hamzah
This paper investigates single-phase electronic transformer design using two stages of Single-Phase Matrix Converter (SPMC) coupled through a high frequency transformer each at the primary and secondary winding in an effort to reduce the size in the future applications of power transformer. Loads are presented in the form of passive device. The proposed system is simulated using MLS with SimPowerSystems environment. An output frequency of 1000Hz is synthesized on the input stage of the transformer using Pulse Width Modulation (PWM) technique with the output converted by another SPMC that produces 50Hz output. Commutation strategies are implemented to mitigate associated problems arising from the use of inductive load.
{"title":"Electronic transformer design using Single-phase Matrix Converter","authors":"H. M. Hanafi, M. K. Hamzah, N. R. Hamzah","doi":"10.1109/ISIEA.2009.5356440","DOIUrl":"https://doi.org/10.1109/ISIEA.2009.5356440","url":null,"abstract":"This paper investigates single-phase electronic transformer design using two stages of Single-Phase Matrix Converter (SPMC) coupled through a high frequency transformer each at the primary and secondary winding in an effort to reduce the size in the future applications of power transformer. Loads are presented in the form of passive device. The proposed system is simulated using MLS with SimPowerSystems environment. An output frequency of 1000Hz is synthesized on the input stage of the transformer using Pulse Width Modulation (PWM) technique with the output converted by another SPMC that produces 50Hz output. Commutation strategies are implemented to mitigate associated problems arising from the use of inductive load.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"8 1","pages":"413-418"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80097006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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