Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527323
Takumi Noda, T. Nagashima, Xiuqin Wei, M. Kazimierczuk, H. Sekiya
This paper presents a design procedure for wireless power transfer (WPT) systems based on the class-E2 dc-dc converter, taking into account inductive coupling-coil optimizations. The WPT system model is formulated as an equivalent circuit model by expressing the inductive coupled part as a transformer with low-coupling coefficient and equivalent resistances of primary and secondary coils. By using the circuit model, the dc-to-dc efficiency can be obtained analytically. The dc-to-dc efficiency, which is a cost function for optimization, is expressed as functions of physical parameters, such as coil size, wire type, and number of turns. The particle swarm optimization (PSO) is applied for reduction of the computational complexity compared with previous design method [1] and maximization of the cost function in this paper. Experimental results showed the validity and the usefulness of the proposed design procedure.
{"title":"Design procedure for wireless power transfer system with inductive coupling-coil optimizations using PSO","authors":"Takumi Noda, T. Nagashima, Xiuqin Wei, M. Kazimierczuk, H. Sekiya","doi":"10.1109/ISCAS.2016.7527323","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527323","url":null,"abstract":"This paper presents a design procedure for wireless power transfer (WPT) systems based on the class-E2 dc-dc converter, taking into account inductive coupling-coil optimizations. The WPT system model is formulated as an equivalent circuit model by expressing the inductive coupled part as a transformer with low-coupling coefficient and equivalent resistances of primary and secondary coils. By using the circuit model, the dc-to-dc efficiency can be obtained analytically. The dc-to-dc efficiency, which is a cost function for optimization, is expressed as functions of physical parameters, such as coil size, wire type, and number of turns. The particle swarm optimization (PSO) is applied for reduction of the computational complexity compared with previous design method [1] and maximization of the cost function in this paper. Experimental results showed the validity and the usefulness of the proposed design procedure.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"52 1","pages":"646-649"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75408597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527432
Kwantae Kim, Minseo Kim, Hyunwoo Cho, Kwonjoon Lee, S. Ryu, H. Yoo
A dedicated ultra-low power arterial pulse wave (APW) sensor for wrist watch type system is implemented in 0.18-μm CMOS technology with 1.8-V supply. A duty cycle controlled (DCC) current source (CS) enables low-power consuming current injection with 98% power reduction. A DC balanced amplifier reduces settling time by 72%, enabling fast APW signal acquisition when motion artifact is occurred. The simulated 2.125-mm2 single chip APW sensor consumes only 54-μW.
{"title":"A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system","authors":"Kwantae Kim, Minseo Kim, Hyunwoo Cho, Kwonjoon Lee, S. Ryu, H. Yoo","doi":"10.1109/ISCAS.2016.7527432","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527432","url":null,"abstract":"A dedicated ultra-low power arterial pulse wave (APW) sensor for wrist watch type system is implemented in 0.18-μm CMOS technology with 1.8-V supply. A duty cycle controlled (DCC) current source (CS) enables low-power consuming current injection with 98% power reduction. A DC balanced amplifier reduces settling time by 72%, enabling fast APW signal acquisition when motion artifact is occurred. The simulated 2.125-mm2 single chip APW sensor consumes only 54-μW.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"46 1","pages":"1082-1085"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77888152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SIMD divergence is one of the critical factors that decrease the hardware utilization in contemporary GPGPUs (General Purpose Graphic Processor Unit). Both the reconvergence scheme and control flow detection have to be well considered. In the emerging HSA (Heterogeneous System Architecture) platform, we develop an effective dynamic stack-based re-convergence scheme that can be implemented without the insertion of re-convergence instructions generated by the finalizer. The stack keeps track of the minimal necessary information of the taken and non-taken paths; the additional end-of-branch instruction insertion is no longer required under our design. Using the scheme we propose, the divergent warp dynamically re-converges at opportunistic re-convergence points. The activity factor improves for 13.36% on average from opportunistic early re-convergence in the unstructured control flow. Our design has eased the development of a finalizer that no longer needs to reason about the reconvergence point after a branch divergence, especially for unstructured control flow.
{"title":"Dynamic SIMD re-convergence with paired-path comparison","authors":"Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, C. Chen","doi":"10.1109/ISCAS.2016.7527213","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527213","url":null,"abstract":"SIMD divergence is one of the critical factors that decrease the hardware utilization in contemporary GPGPUs (General Purpose Graphic Processor Unit). Both the reconvergence scheme and control flow detection have to be well considered. In the emerging HSA (Heterogeneous System Architecture) platform, we develop an effective dynamic stack-based re-convergence scheme that can be implemented without the insertion of re-convergence instructions generated by the finalizer. The stack keeps track of the minimal necessary information of the taken and non-taken paths; the additional end-of-branch instruction insertion is no longer required under our design. Using the scheme we propose, the divergent warp dynamically re-converges at opportunistic re-convergence points. The activity factor improves for 13.36% on average from opportunistic early re-convergence in the unstructured control flow. Our design has eased the development of a finalizer that no longer needs to reason about the reconvergence point after a branch divergence, especially for unstructured control flow.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"78 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78109651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527532
Neelakantan Narasimman, T. T. Kim
This paper introduces an ultra-low voltage open loop VCO-based ADC with background calibration for ultra-low power applications. A novel calibration scheme is proposed to calibrate the nonlinear voltage-to-frequency tuning curve of the VCO. A replica VCO is used to compute the correction coefficients and the corrected values are stored in a lookup table. The proposed calibration method is at least 64 times faster than other state-of-the-art ones. A test chip was implemented in commercial 65nm CMOS technology. Measurement results confirm the effectiveness of the calibration scheme at 0.4 V. The proposed VCO-based ADC achieves a resolution of 8.8 bits at 10 KHz bandwidth with the power consumption of 1.15 μW in the open loop architecture.
{"title":"An ultra-low voltage, VCO-based ADC with digital background calibration","authors":"Neelakantan Narasimman, T. T. Kim","doi":"10.1109/ISCAS.2016.7527532","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527532","url":null,"abstract":"This paper introduces an ultra-low voltage open loop VCO-based ADC with background calibration for ultra-low power applications. A novel calibration scheme is proposed to calibrate the nonlinear voltage-to-frequency tuning curve of the VCO. A replica VCO is used to compute the correction coefficients and the corrected values are stored in a lookup table. The proposed calibration method is at least 64 times faster than other state-of-the-art ones. A test chip was implemented in commercial 65nm CMOS technology. Measurement results confirm the effectiveness of the calibration scheme at 0.4 V. The proposed VCO-based ADC achieves a resolution of 8.8 bits at 10 KHz bandwidth with the power consumption of 1.15 μW in the open loop architecture.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"16 1","pages":"1458-1461"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74883376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527437
Bathiya Senevirathna, Lauren Berman, Nicola Bertoni, Fabio Pareschi, Mauro Mangia, R. Rovatti, G. Setti, J. Simon, P. Abshire
We report a low cost mobile EEG system for characterizing cortical auditory responses. The system is built using commercial off-the-shelf components and each unit costs less than $200. It measures seven EEG channels plus one audio channel (envelope only), and communicates the data to external devices via Bluetooth. A novel implementation was pursued in order to support local signal compression using compressed sensing. At the same time, it provides a low cost solution that is useful for recording cortical auditory responses and extracting clinically relevant features of the waveform. This system has been designed with the eventual goal of long term monitoring of the brain activity of schizophrenic patients outside a clinical setting, in order to better understand auditory hallucinations and manage their ongoing treatment. In this preliminary study we obtained simultaneous audio and cortical recordings of evoked auditory responses from normal healthy subjects wearing the EEG for several hours in duration. We report evoked auditory responses for 2 Hz and 40 Hz click trains. We also report alpha wave responses, demonstrating stable and high quality recordings over a five hour period.
{"title":"Low cost mobile EEG for characterization of cortical auditory responses","authors":"Bathiya Senevirathna, Lauren Berman, Nicola Bertoni, Fabio Pareschi, Mauro Mangia, R. Rovatti, G. Setti, J. Simon, P. Abshire","doi":"10.1109/ISCAS.2016.7527437","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527437","url":null,"abstract":"We report a low cost mobile EEG system for characterizing cortical auditory responses. The system is built using commercial off-the-shelf components and each unit costs less than $200. It measures seven EEG channels plus one audio channel (envelope only), and communicates the data to external devices via Bluetooth. A novel implementation was pursued in order to support local signal compression using compressed sensing. At the same time, it provides a low cost solution that is useful for recording cortical auditory responses and extracting clinically relevant features of the waveform. This system has been designed with the eventual goal of long term monitoring of the brain activity of schizophrenic patients outside a clinical setting, in order to better understand auditory hallucinations and manage their ongoing treatment. In this preliminary study we obtained simultaneous audio and cortical recordings of evoked auditory responses from normal healthy subjects wearing the EEG for several hours in duration. We report evoked auditory responses for 2 Hz and 40 Hz click trains. We also report alpha wave responses, demonstrating stable and high quality recordings over a five hour period.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"1102-1105"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74904597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527488
Yaoxing Hu, Sanjiv Sharma, J. Weatherwax, A. Cass, P. Georgiou
This paper presents a compact and scalable architecture design of a multi-channel potentiostat. Utilizing a hybrid-multiplexed technique, the system is capable of driving multi-electrode array structures of large sizes with few readout channels. A 5-channel potentiostat with 80-electrode capability was fabricated into a portable 8.382×9.906 cm2 PCB prototype using discrete components. It features a dynamic current range of 126dB and 3.3V single-supply operation. Controlled by a MATLAB graphical user interface, the system demonstrates realtime data acquisition and achieves similar performance to a commercial potentiostat based on electrochemical validation.
{"title":"A portable multi-channel potentiostat for real-time amperometric measurement of multi-electrode sensor arrays","authors":"Yaoxing Hu, Sanjiv Sharma, J. Weatherwax, A. Cass, P. Georgiou","doi":"10.1109/ISCAS.2016.7527488","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527488","url":null,"abstract":"This paper presents a compact and scalable architecture design of a multi-channel potentiostat. Utilizing a hybrid-multiplexed technique, the system is capable of driving multi-electrode array structures of large sizes with few readout channels. A 5-channel potentiostat with 80-electrode capability was fabricated into a portable 8.382×9.906 cm2 PCB prototype using discrete components. It features a dynamic current range of 126dB and 3.3V single-supply operation. Controlled by a MATLAB graphical user interface, the system demonstrates realtime data acquisition and achieves similar performance to a commercial potentiostat based on electrochemical validation.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"165 1","pages":"1306-1309"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74906230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527412
R. Damseh, M. Ahmad
In synthetic aperture radar (SAR) images, speckle noise reduction is a crucial pre-processing step for their successful interpretation and thus has drawn a great deal of attention of researchers in the image processing community. The Bayesian estimation is a powerful signal estimation technique and has been widely used for speckle noise removal in images. In this work, a low complexity wavelet-based Bayesian estimation technique for despeckling of images is developed. The main idea of the proposed technique is in establishing suitable statistical models for the wavelet coefficients and then in using these models to develop a shrinkage function with a low-complexity realization for the estimation of the wavelet coefficients of the noise-free images. The experimental results demonstrate the effectiveness of the proposed despeckling scheme in providing a significant reduction in the speckle noise at a very low computational cost and simultaneously preserving the image details.
{"title":"A low-complexity MMSE Bayesian estimator for suppression of speckle in SAR images","authors":"R. Damseh, M. Ahmad","doi":"10.1109/ISCAS.2016.7527412","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527412","url":null,"abstract":"In synthetic aperture radar (SAR) images, speckle noise reduction is a crucial pre-processing step for their successful interpretation and thus has drawn a great deal of attention of researchers in the image processing community. The Bayesian estimation is a powerful signal estimation technique and has been widely used for speckle noise removal in images. In this work, a low complexity wavelet-based Bayesian estimation technique for despeckling of images is developed. The main idea of the proposed technique is in establishing suitable statistical models for the wavelet coefficients and then in using these models to develop a shrinkage function with a low-complexity realization for the estimation of the wavelet coefficients of the noise-free images. The experimental results demonstrate the effectiveness of the proposed despeckling scheme in providing a significant reduction in the speckle noise at a very low computational cost and simultaneously preserving the image details.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1002-1005"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75199094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539021
Ulian Shahnovich, Alain Horé, O. Yadid-Pecht
This paper presents a hardware implementation of a mantissa/exponent-based tone mapping algorithm for wide dynamic range (WDR) images. The algorithm performs tone mapping by using a global compression model for the pixel intensities combined with a local contrast enhancement model. The pixel intensities of the WDR images used in this paper are represented in a mantissa/exponent format produced by an innovative WDR imager which takes advantage of a multi-reset technique during the capture process. The algorithm has been implemented on FPGA and designed to be very small, fast, power-efficient and has the potential to be directly integrated into the same chip as the imager. Experimental results performed by using different images show that our implementation is reliable and efficient.
{"title":"Hardware implementation of a real-time tone mapping algorithm based on a mantissa-exponent representation","authors":"Ulian Shahnovich, Alain Horé, O. Yadid-Pecht","doi":"10.1109/ISCAS.2016.7539021","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539021","url":null,"abstract":"This paper presents a hardware implementation of a mantissa/exponent-based tone mapping algorithm for wide dynamic range (WDR) images. The algorithm performs tone mapping by using a global compression model for the pixel intensities combined with a local contrast enhancement model. The pixel intensities of the WDR images used in this paper are represented in a mantissa/exponent format produced by an innovative WDR imager which takes advantage of a multi-reset technique during the capture process. The algorithm has been implemented on FPGA and designed to be very small, fast, power-efficient and has the potential to be directly integrated into the same chip as the imager. Experimental results performed by using different images show that our implementation is reliable and efficient.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"35 1","pages":"2210-2213"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75974812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527497
William E. Murphy, Megan Renz, Qing Wu
This paper examines the performance of two power efficient hardware implementations using deep neural networks to perform a simple image classification task. We provide the first ever examination of the accuracy-energy trade-offs of deep neural networks running on both an embedded GPU, and a neuromorphic processor. IBM's TrueNorth is a brain-inspired event-driven neuromorphic processor. It was designed to be scalable and to consume extremely low amounts of power. NVIDIA's Tegra K1 SoC is a mobile processor also designed with low power and a small footprint in mind. While these two chips were designed with similar constraints, the resulting architectures and performance trade-offs achieved are significantly different. On our simple image classification task Convolutional Neural Networks utilizing the Tegra K1 SoC achieve up to 89 % accuracy with a normalized accuracy per active energy, ||Acc||/EA, score of up to 24.22 on our test dataset, while Tea Networks running on the TrueNorth processor achieve less accuracy at 82%, but a better accuracy-energy trade-off with a ||Acc||/EA score of up to 158.49.
{"title":"Binary image classification using a neurosynaptic processor: A trade-off analysis","authors":"William E. Murphy, Megan Renz, Qing Wu","doi":"10.1109/ISCAS.2016.7527497","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527497","url":null,"abstract":"This paper examines the performance of two power efficient hardware implementations using deep neural networks to perform a simple image classification task. We provide the first ever examination of the accuracy-energy trade-offs of deep neural networks running on both an embedded GPU, and a neuromorphic processor. IBM's TrueNorth is a brain-inspired event-driven neuromorphic processor. It was designed to be scalable and to consume extremely low amounts of power. NVIDIA's Tegra K1 SoC is a mobile processor also designed with low power and a small footprint in mind. While these two chips were designed with similar constraints, the resulting architectures and performance trade-offs achieved are significantly different. On our simple image classification task Convolutional Neural Networks utilizing the Tegra K1 SoC achieve up to 89 % accuracy with a normalized accuracy per active energy, ||Acc||/EA, score of up to 24.22 on our test dataset, while Tea Networks running on the TrueNorth processor achieve less accuracy at 82%, but a better accuracy-energy trade-off with a ||Acc||/EA score of up to 158.49.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"36 1","pages":"1342-1345"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76299105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527206
Saad Bin Nasir, A. Raychowdhury
This paper explores microarchitecture controlled proactive gain boosting as a means of lowering the effects of supply voltage droop in digital circuits powered by embedded, all-digital linear regulators. A behavioral power supply rejection model for all-digital linear regulator is presented. The presented regulator shows enhanced power supply rejection under increased operating frequency. Test-chip measurements in a 130nm CMOS process reveal more than 2X (4X) reduction in voltage droop (settling time) over purely reactive gain boosting.
{"title":"All-digital linear regulators with proactive and reactive gain-boosting for supply droop mitigation in digital load circuits","authors":"Saad Bin Nasir, A. Raychowdhury","doi":"10.1109/ISCAS.2016.7527206","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527206","url":null,"abstract":"This paper explores microarchitecture controlled proactive gain boosting as a means of lowering the effects of supply voltage droop in digital circuits powered by embedded, all-digital linear regulators. A behavioral power supply rejection model for all-digital linear regulator is presented. The presented regulator shows enhanced power supply rejection under increased operating frequency. Test-chip measurements in a 130nm CMOS process reveal more than 2X (4X) reduction in voltage droop (settling time) over purely reactive gain boosting.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"81 1","pages":"205-208"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74545906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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