Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527504
V. Annese, Christopher Martin, D. Cumming, D. Venuto
In this paper an improved design of an RFID powered swallowable barometric endoradiosonde (ERS) is presented. The ERS consists of a micro fabricated capacitive sensor printed in gold on Polycaprolactone (PCL) on which a transponder chip design in 0.35μm AMS technology is in-plane bounded to the PCL substrate. The implantable or inside the body, transponder (tag) is powered by the external reader at 900MHz through inductively coupled antennas. The tag performs the capacitance to frequency conversion and transmits data back to the reader using load-shift keying (LSK) modulation. The ERS can measure the sensor output frequency with an INL error of 0.4%, sensitivity (Δf/ΔP) of -6.12MHz/kPa, occupies a volume of 1mm3 (transponder only), consumes, 400μW and 360μW for, respectively, dynamic and static power. The sensor has an accuracy of ± 0.1kPa, works in the pressure range of 0-1.99kPa (0-15mmHg). The readout circuit has a ±1.84kHz resolution.
{"title":"Wireless capsule technology: Remotely powered improved high-sensitive barometric endoradiosonde","authors":"V. Annese, Christopher Martin, D. Cumming, D. Venuto","doi":"10.1109/ISCAS.2016.7527504","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527504","url":null,"abstract":"In this paper an improved design of an RFID powered swallowable barometric endoradiosonde (ERS) is presented. The ERS consists of a micro fabricated capacitive sensor printed in gold on Polycaprolactone (PCL) on which a transponder chip design in 0.35μm AMS technology is in-plane bounded to the PCL substrate. The implantable or inside the body, transponder (tag) is powered by the external reader at 900MHz through inductively coupled antennas. The tag performs the capacitance to frequency conversion and transmits data back to the reader using load-shift keying (LSK) modulation. The ERS can measure the sensor output frequency with an INL error of 0.4%, sensitivity (Δf/ΔP) of -6.12MHz/kPa, occupies a volume of 1mm3 (transponder only), consumes, 400μW and 360μW for, respectively, dynamic and static power. The sensor has an accuracy of ± 0.1kPa, works in the pressure range of 0-1.99kPa (0-15mmHg). The readout circuit has a ±1.84kHz resolution.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"311 5 1","pages":"1370-1373"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72969704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539214
A. Andreou, Andrew A. Dykman, Kate D. Fischl, Guillaume Garreau, Daniel R. Mendat, G. Orchard, A. Cassidy, P. Merolla, J. Arthur, Rodrigo Alvarez-Icaza, Bryan L. Jackson, D. Modha
Summary form only given. The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units - neurons-that operate on a unary number representation and compute by counting up to a maximum of 19 bits. The cores are event-driven using custom asynchronous and synchronous logic, and they are globally connected through an asynchronous packet switched mesh network on chip (NOC). The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).
只提供摘要形式。IBM TrueNorth (TN)神经突触系统是一种芯片多处理器，具有紧密耦合的处理器/内存架构，可实现节能的神经计算，是30多年来神经形态工程的重要里程碑!它由4096个核心组成，每个核心都有65K的本地内存(6T SRAM)——突触——和256个算术逻辑单元——神经元——它们以一个数表示操作，并通过最多19位的计数进行计算。这些核心是使用自定义异步和同步逻辑的事件驱动的，它们通过异步分组交换的片上网状网络(NOC)进行全局连接。芯片开发板包括zynxilinx FPGA，它通过以太网UDP接口提供标准通信支持。NOC中的异步寻址事件表示(AER)也公开给用户，以便通过带有捆绑数据全双工接口的数据包连接到基于AER的外设。在系统总线上表示的一元数据值可以采用各种各样的空间和时间编码方案。脉冲密度编码(事件数Ne表示数字N)、温度计编码、时隙编码和随机编码都是例子。额外的低电平接口可用于直接与TrueNorth芯片通信，以帮助编程和参数设置。一种分层的组合编程语言Corelet可用于帮助TN应用程序的开发。IBM提供了支持和一个开发系统，以及一个可扩展的模拟器“Compass”。软件环境在标准Linux安装(Red Hat, CentOS和Ubuntu)下运行，并具有与Matlab和用于训练深度神经网络模型的Caffe的标准接口。TN架构可以使用原生AER与许多经过多年神经形态工程(硅视网膜和硅耳蜗)开发的仿生感官设备进行接口。此外，该体系结构非常适合在计算机视觉、语音识别和语言处理等领域实现深度神经网络。在感官信息处理系统架构中，既需要空间和时间上的模式处理来提取符号子空间中的特征，又需要自然语言处理来以先验的形式提供上下文和语义信息。在本文中，我们讨论了使用TN架构在三个不同领域进行的实时感官信息处理实验工作的结果(i)空间模式处理-计算机视觉(ii)时间模式处理-语音处理和识别(iii)自然语言处理-词相似度-。在ISCAS 2016上，将使用TN系统和基于听觉(硅耳蜗)和视觉(硅视网膜)的神经形态事件传感器进行实时演示。
{"title":"Real-time sensory information processing using the TrueNorth Neurosynaptic System","authors":"A. Andreou, Andrew A. Dykman, Kate D. Fischl, Guillaume Garreau, Daniel R. Mendat, G. Orchard, A. Cassidy, P. Merolla, J. Arthur, Rodrigo Alvarez-Icaza, Bryan L. Jackson, D. Modha","doi":"10.1109/ISCAS.2016.7539214","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539214","url":null,"abstract":"Summary form only given. The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units - neurons-that operate on a unary number representation and compute by counting up to a maximum of 19 bits. The cores are event-driven using custom asynchronous and synchronous logic, and they are globally connected through an asynchronous packet switched mesh network on chip (NOC). The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"26 1","pages":"2911-2911"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74227128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539071
M. Wahib, A. Freundorfer
This paper presents a miniaturized coupled line directional coupler carefully designed in a lumped element configuration. Due to the fact that all the parasitics (i.e. ohmic losses, inductances and capacitances) were taken into consideration at different stages of the design process, this resulted in a measured response which is in very close agreement with the simulated one. The measurements showed an input return loss and isolation of 22.43 dB and 15.76 dB respectively at 1 GHz with a 10-dB fractional bandwidth of almost 10.85%. The measured coupling and thru coefficients are 3.48 dB and 4.01 dB respectively at the same operating frequency. These values agreed quite well with the ones from the electromagnetic simulations. The reduction in the measured thru coefficient is mainly due to the added losses of solders and co-axial connectors. A phase error of about 2.4° with respect to the expected 90° phase difference was noticed.
{"title":"A miniaturized lumped element directional coupler with parasitics compensation","authors":"M. Wahib, A. Freundorfer","doi":"10.1109/ISCAS.2016.7539071","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539071","url":null,"abstract":"This paper presents a miniaturized coupled line directional coupler carefully designed in a lumped element configuration. Due to the fact that all the parasitics (i.e. ohmic losses, inductances and capacitances) were taken into consideration at different stages of the design process, this resulted in a measured response which is in very close agreement with the simulated one. The measurements showed an input return loss and isolation of 22.43 dB and 15.76 dB respectively at 1 GHz with a 10-dB fractional bandwidth of almost 10.85%. The measured coupling and thru coefficients are 3.48 dB and 4.01 dB respectively at the same operating frequency. These values agreed quite well with the ones from the electromagnetic simulations. The reduction in the measured thru coefficient is mainly due to the added losses of solders and co-axial connectors. A phase error of about 2.4° with respect to the expected 90° phase difference was noticed.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"46 1","pages":"2383-2386"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74412165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539066
Hong-Son Vu, Kuan-Hung Chen
We have designed, fabricated, and tested a low-power broad-bandwidth noise cancellation VLSI circuit for in-ear headphones. The proposed design can attenuate 15 dB for broadband pink noise between 50-1500 Hz when operated at 20 MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.59 mW only. Compared with the existing designs, the proposed work achieves higher noise cancellation performance in terms of 3 dB further and saves 97% power consumption.
{"title":"Live demonstration: A low-power broad-bandwidth noise cancellation VLSI circuit design for in-ear headphones","authors":"Hong-Son Vu, Kuan-Hung Chen","doi":"10.1109/ISCAS.2016.7539066","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539066","url":null,"abstract":"We have designed, fabricated, and tested a low-power broad-bandwidth noise cancellation VLSI circuit for in-ear headphones. The proposed design can attenuate 15 dB for broadband pink noise between 50-1500 Hz when operated at 20 MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.59 mW only. Compared with the existing designs, the proposed work achieves higher noise cancellation performance in terms of 3 dB further and saves 97% power consumption.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"2375-2375"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74858564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539131
Baihong Jin, Guojie Luo, Wentai Zhang
The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest [1].
{"title":"A fast and accurate approach for common path pessimism removal in static timing analysis","authors":"Baihong Jin, Guojie Luo, Wentai Zhang","doi":"10.1109/ISCAS.2016.7539131","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539131","url":null,"abstract":"The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest [1].","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"2623-2626"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74875525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527264
Junrui Liang
It has been shown in the previous study that the class-E power amplifier (PA) circuit can be efficiently simulated and optimized in the frequency domain by modeling the whole circuit with the extended impedance method (EIM). This paper reports a breakthrough in the EIM based class-E PA design by taking the nonlinear components into consideration. In analysis, the effect of the two state-dependent nonlinear components in a practical MOSFET switch, i.e., the parasitic drain-to-source junction capacitance and the body diode, is turned into the time-dependent characteristics by carrying out the states-to-time mapping. Iterative computation is necessary for obtaining the steady-state waveforms in view of the nonlinear components. Yet, given the high efficiency of EIM, it is proved that the EIM based optimization runs much faster than the state-of-the-art numerical class-E PA optimization.
{"title":"Design of class-E power amplifier with nonlinear components by using extended impedance method","authors":"Junrui Liang","doi":"10.1109/ISCAS.2016.7527264","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527264","url":null,"abstract":"It has been shown in the previous study that the class-E power amplifier (PA) circuit can be efficiently simulated and optimized in the frequency domain by modeling the whole circuit with the extended impedance method (EIM). This paper reports a breakthrough in the EIM based class-E PA design by taking the nonlinear components into consideration. In analysis, the effect of the two state-dependent nonlinear components in a practical MOSFET switch, i.e., the parasitic drain-to-source junction capacitance and the body diode, is turned into the time-dependent characteristics by carrying out the states-to-time mapping. Iterative computation is necessary for obtaining the steady-state waveforms in view of the nonlinear components. Yet, given the high efficiency of EIM, it is proved that the EIM based optimization runs much faster than the state-of-the-art numerical class-E PA optimization.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"90 1","pages":"437-440"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73326375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527500
B. Minch
In this paper, I present a simple CMOS bump circuit whose transfer characteristic width is electronically adjustable via a single back-gate bias voltage. The proposed circuit comprises two asymmetric differential pairs whose transfer characteristics can be shifted left and right about the origin by adjusting this back-gate bias. One output current from each diff pair is fed into a current correlator circuit, which produces the bump current. The circuit can simultaneously produce a complementary antibump current by summing the other two diff pair currents. I describe the proposed circuit's operation, present a large-signal analysis for weak-inversion bias currents, and show measurements from a proof-of-principle prototype made from commercially available MOS transistor arrays.
{"title":"A simple variable-width CMOS bump circuit","authors":"B. Minch","doi":"10.1109/ISCAS.2016.7527500","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527500","url":null,"abstract":"In this paper, I present a simple CMOS bump circuit whose transfer characteristic width is electronically adjustable via a single back-gate bias voltage. The proposed circuit comprises two asymmetric differential pairs whose transfer characteristics can be shifted left and right about the origin by adjusting this back-gate bias. One output current from each diff pair is fed into a current correlator circuit, which produces the bump current. The circuit can simultaneously produce a complementary antibump current by summing the other two diff pair currents. I describe the proposed circuit's operation, present a large-signal analysis for weak-inversion bias currents, and show measurements from a proof-of-principle prototype made from commercially available MOS transistor arrays.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"244 1","pages":"1354-1357"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84215710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527363
Shuyuan Zhu, Liaoyuan Zeng, B. Zeng, Jiantao Zhou
The image down-conversion may be used in the block-based image compression because it can help save lots of bit-counts for each individual block. A straightforward way to implement the transform domain down-conversion is to truncate some high-frequency components to get a down-sized coefficient block. However, directly using this down-sized coefficient block to reconstruct a completed image block will lead to a serious quality degradation. In this paper, we propose a constrained quantization based transform domain down-conversion (CQTDD) to help compress each 16×16 macro-block and it makes the coding quality of 1/4 selected pixels (according to a regular pattern) in each macro-block much higher than that can be achieved by using the traditional truncation based approach. Meanwhile, the other 3/4 pixels will be interpolated by using those 1/4 well-reconstructed pixels. Furthermore, these 1/4 pixels are optimized before the compression to help get a more efficient interpolation. Finally, the proposed CQTDD works with the JPEG baseline coding together as two candidate coding modes in our proposed compression scheme. Experimental results demonstrate that our proposed method may offer a remarkable quality gain, both objectively and subjectively, compared with some existing methods.
{"title":"Constrained quantization based transform domain down-conversion for image compression","authors":"Shuyuan Zhu, Liaoyuan Zeng, B. Zeng, Jiantao Zhou","doi":"10.1109/ISCAS.2016.7527363","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527363","url":null,"abstract":"The image down-conversion may be used in the block-based image compression because it can help save lots of bit-counts for each individual block. A straightforward way to implement the transform domain down-conversion is to truncate some high-frequency components to get a down-sized coefficient block. However, directly using this down-sized coefficient block to reconstruct a completed image block will lead to a serious quality degradation. In this paper, we propose a constrained quantization based transform domain down-conversion (CQTDD) to help compress each 16×16 macro-block and it makes the coding quality of 1/4 selected pixels (according to a regular pattern) in each macro-block much higher than that can be achieved by using the traditional truncation based approach. Meanwhile, the other 3/4 pixels will be interpolated by using those 1/4 well-reconstructed pixels. Furthermore, these 1/4 pixels are optimized before the compression to help get a more efficient interpolation. Finally, the proposed CQTDD works with the JPEG baseline coding together as two candidate coding modes in our proposed compression scheme. Experimental results demonstrate that our proposed method may offer a remarkable quality gain, both objectively and subjectively, compared with some existing methods.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"57 1","pages":"806-809"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84416005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539190
Bathiya Senevirathna, Alexander Castro, M. Dandin, E. Smela, P. Abshire
Capacitance sensing is an emerging technology for monitoring cell viability. This work extends a previously developed sensor that measured capacitive loading by cells on the oscillation frequency of a current-starved ring oscillator and converted the frequency to a digital value by counting oscillation cycles. The new sensor array has been developed into a one-chip lab-on-CMOS system with integrated temperature sensors, serial readout to an external microcontroller using an Inter-Integrated Circuit (I2C) bus, and automatic scanning to allow for autonomous data collection. To allow sensing at the required aF levels, the system was realized on single chip to reduce the baseline capacitance, and long counting times were employed. The I2C module was moved to the edge of the chip prevent exposing cells to unacceptably high temperatures during viability studies.
{"title":"Lab-on-CMOS capacitance sensor array for real-time cell viability measurements with I2C readout","authors":"Bathiya Senevirathna, Alexander Castro, M. Dandin, E. Smela, P. Abshire","doi":"10.1109/ISCAS.2016.7539190","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539190","url":null,"abstract":"Capacitance sensing is an emerging technology for monitoring cell viability. This work extends a previously developed sensor that measured capacitive loading by cells on the oscillation frequency of a current-starved ring oscillator and converted the frequency to a digital value by counting oscillation cycles. The new sensor array has been developed into a one-chip lab-on-CMOS system with integrated temperature sensors, serial readout to an external microcontroller using an Inter-Integrated Circuit (I2C) bus, and automatic scanning to allow for autonomous data collection. To allow sensing at the required aF levels, the system was realized on single chip to reduce the baseline capacitance, and long counting times were employed. The I2C module was moved to the edge of the chip prevent exposing cells to unacceptably high temperatures during viability studies.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"16 1","pages":"2863-2866"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84425128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527229
Scott M. Newton, P. Kinget
An inverter-transconductor-based continuous-time analog 4th-order low-pass Butterworth filter was described entirely in Verilog hardware description language (HDL) using only standard cells. The physical design was synthesized with automated digital logic place-and-route (APR) CAD tools. APR was achieved in less than a minute making for an enormous improvement compared to traditional manual analog chip layout. A test chip was fabricated in a 0.18um CMOS technology and its performance was experimentally verified. The experimental results document excellent measured performance and a huge physical design timesaving thereby validating the proposed automated design methodology.
{"title":"A 4th-order analog continuous-time filter designed using standard cells and automatic digital logic design tools","authors":"Scott M. Newton, P. Kinget","doi":"10.1109/ISCAS.2016.7527229","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527229","url":null,"abstract":"An inverter-transconductor-based continuous-time analog 4th-order low-pass Butterworth filter was described entirely in Verilog hardware description language (HDL) using only standard cells. The physical design was synthesized with automated digital logic place-and-route (APR) CAD tools. APR was achieved in less than a minute making for an enormous improvement compared to traditional manual analog chip layout. A test chip was fabricated in a 0.18um CMOS technology and its performance was experimentally verified. The experimental results document excellent measured performance and a huge physical design timesaving thereby validating the proposed automated design methodology.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"27 1","pages":"297-300"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84599774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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