Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059434
P. Lall, Nakul Kothari, Kartik Goyal, Benjamin J. Leever, Scott Miller
Traditionally, a combination of imaging and plating based subtractive processes have been used for fabrication of printed circuit assemblies to form the needed circuitry on rigid and flexible laminates. In addition to circuits, additive electronics is finding applications for fabrication of sensors for wearable applications and asset situational awareness. Aerosol-Jet printing has shown the capability for printing lines and spaces below $10 mu mathrm{m}$ in width with a wide variety of materials, including nanoparticle inks, conductive polymers, insulators, adhesives, and even biological matter. The adoption of additive manufacturing for high-volume commercial fabrication requires an understanding of the print consistency, electrical and mechanical properties. In this study, the effect of process parameters on the resultant line-consistency, mechanical and electrical properties has been studied for single-layer and multi-layer substrates. Print process parameters studied include the sheath rate, mass flow rate, nozzle size, substrate temperature and chiller temperature. Properties include resistance and shear load to failure of the printed electrical line as a function of varying sintering time and varying sintering temperature. Printed samples have been exposed to different sintering times and temperatures. The resistance and shear load to failure of the printed lines has been measured. The underlying physics of the resultant trend was then investigated using elemental analysis and SEM. The effect of line-consistency drift over prolonged runtimes has been measured for up to 10-hours of runtime. Printing process efficiency has been gauged a function of process capability index (Cpk) and process capability ratio (Cp). Printed samples were studied offline using optical Profilometry to analyze the consistency within the line width, line height, line resistance and shear load to study the variance in the electrical and mechanical properties over time.
{"title":"Extended-Time Process Consistency and Process-Property Relationships for Flexible Additive-Printed Electronics","authors":"P. Lall, Nakul Kothari, Kartik Goyal, Benjamin J. Leever, Scott Miller","doi":"10.23919/PanPacific48324.2020.9059434","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059434","url":null,"abstract":"Traditionally, a combination of imaging and plating based subtractive processes have been used for fabrication of printed circuit assemblies to form the needed circuitry on rigid and flexible laminates. In addition to circuits, additive electronics is finding applications for fabrication of sensors for wearable applications and asset situational awareness. Aerosol-Jet printing has shown the capability for printing lines and spaces below $10 mu mathrm{m}$ in width with a wide variety of materials, including nanoparticle inks, conductive polymers, insulators, adhesives, and even biological matter. The adoption of additive manufacturing for high-volume commercial fabrication requires an understanding of the print consistency, electrical and mechanical properties. In this study, the effect of process parameters on the resultant line-consistency, mechanical and electrical properties has been studied for single-layer and multi-layer substrates. Print process parameters studied include the sheath rate, mass flow rate, nozzle size, substrate temperature and chiller temperature. Properties include resistance and shear load to failure of the printed electrical line as a function of varying sintering time and varying sintering temperature. Printed samples have been exposed to different sintering times and temperatures. The resistance and shear load to failure of the printed lines has been measured. The underlying physics of the resultant trend was then investigated using elemental analysis and SEM. The effect of line-consistency drift over prolonged runtimes has been measured for up to 10-hours of runtime. Printing process efficiency has been gauged a function of process capability index (Cpk) and process capability ratio (Cp). Printed samples were studied offline using optical Profilometry to analyze the consistency within the line width, line height, line resistance and shear load to study the variance in the electrical and mechanical properties over time.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"46 1","pages":"1-16"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78669140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059460
Matthew K. Hudes
Healthcare currently contains major gaps in the areas of chronic and acute disease, the role of genetics and the environment, lack of access based on location and income, the process of aging and the role of fitness and wellness, among others. Some of these gaps may be filled by technologies, and some of these gaps may only be filled by technologies. Digital Health is comprised of applications of wearable and implantable technology, web and email, mobile technology, software and social networking, and data management and analytics. Some of the prominent emerging areas of technology that will be relied upon include: •Artificial Intelligence •Big Data •Wearables •Fitness and consumer-related products •Medical technology and devices The growing worldwide aging population is stretching healthcare capabilities and resources, leading to another set of gaps. Many of the initial Digital Health offerings were developed by technology and healthcare companies and offered to patients and consumers with limited adoption. Consumers' preference and desire for wearable technology has led to more patient-owned technology solutions that are more readily adopted. The concept of “Connected Care” presents a comprehensive environment in which technology can transform healthcare. However, several frameworks will be required for the technology infrastructure and applications to fall into place. As they come together, fundamental types of innovation can occur in healthcare, creating unprecedented and sizable opportunities for Technology, Biotechnology, and Medical Technology (Tech+Biotech+Medtech).
{"title":"Healthcare Gaps that Only Technology Can Fill","authors":"Matthew K. Hudes","doi":"10.23919/PanPacific48324.2020.9059460","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059460","url":null,"abstract":"Healthcare currently contains major gaps in the areas of chronic and acute disease, the role of genetics and the environment, lack of access based on location and income, the process of aging and the role of fitness and wellness, among others. Some of these gaps may be filled by technologies, and some of these gaps may only be filled by technologies. Digital Health is comprised of applications of wearable and implantable technology, web and email, mobile technology, software and social networking, and data management and analytics. Some of the prominent emerging areas of technology that will be relied upon include: •Artificial Intelligence •Big Data •Wearables •Fitness and consumer-related products •Medical technology and devices The growing worldwide aging population is stretching healthcare capabilities and resources, leading to another set of gaps. Many of the initial Digital Health offerings were developed by technology and healthcare companies and offered to patients and consumers with limited adoption. Consumers' preference and desire for wearable technology has led to more patient-owned technology solutions that are more readily adopted. The concept of “Connected Care” presents a comprehensive environment in which technology can transform healthcare. However, several frameworks will be required for the technology infrastructure and applications to fall into place. As they come together, fundamental types of innovation can occur in healthcare, creating unprecedented and sizable opportunities for Technology, Biotechnology, and Medical Technology (Tech+Biotech+Medtech).","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"216 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74896217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059539
K. Hollstein, K. Weide-Zaage
A review about latest advances in packaging and drivers for the development of novel packaging technologies will be given in this paper. Starting with a description about the trends in miniaturization of IC packaging and the demand for heterogeneous integration in the following a focus on commonly applied processes like System-on-Chip, Flip-Chip packaging, Fan-out packaging and 3D-Integration will be presented. A brief explanation about process characteristics, followed by an explanation of the main process steps is described. The latest version of the heterogeneous integration roadmap is short introduced. The link to corresponding fields of application like high performance computing and AI processing, mobile electronics and 5G, and automotive is given. Here, main requirements for each technological sectors are worked out followed by a description of commonly applied package types. Each sector is round up by mentioning key challenges for future developments.
{"title":"Advances in Packaging for Emerging Technologies","authors":"K. Hollstein, K. Weide-Zaage","doi":"10.23919/PanPacific48324.2020.9059539","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059539","url":null,"abstract":"A review about latest advances in packaging and drivers for the development of novel packaging technologies will be given in this paper. Starting with a description about the trends in miniaturization of IC packaging and the demand for heterogeneous integration in the following a focus on commonly applied processes like System-on-Chip, Flip-Chip packaging, Fan-out packaging and 3D-Integration will be presented. A brief explanation about process characteristics, followed by an explanation of the main process steps is described. The latest version of the heterogeneous integration roadmap is short introduced. The link to corresponding fields of application like high performance computing and AI processing, mobile electronics and 5G, and automotive is given. Here, main requirements for each technological sectors are worked out followed by a description of commonly applied package types. Each sector is round up by mentioning key challenges for future developments.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"29 1","pages":"1-11"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85013849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/panpacific48324.2020.9059409
Yeong-Kook Kim, Seohyun Jang, Dosoon Hwnag
Large size commercially available plastic ball grid array chip packaging was tested and analyzed under random vibration to assess its application feasibility on satellite electronics. Two types of the PBGA were chosen, and the chips were surface mounted without underfill on a daisy chained polyimide printed circuit boards. Two strong levels of the random vibrations were applied sequentially to investigate the sustainability of the PBGA chips mounted on the polyimide PCB with aluminum frame. It was found that the test results did not show any solder failure under the test conditions, indicating the robust structural integrity and providing the evidences justifying the PBGA packaging application to the aerospace applications. Numerical analyses were also performed for the solder stress development mechanism. The results demonstrated that the first natural mode was not necessarily the dominant source for the maximum solder stress, and higher stress could be induced at higher natural modes depending on the chip size and its location.
{"title":"PBGA Solder Stress Development Mechanism Analyses Under Random Vibration","authors":"Yeong-Kook Kim, Seohyun Jang, Dosoon Hwnag","doi":"10.23919/panpacific48324.2020.9059409","DOIUrl":"https://doi.org/10.23919/panpacific48324.2020.9059409","url":null,"abstract":"Large size commercially available plastic ball grid array chip packaging was tested and analyzed under random vibration to assess its application feasibility on satellite electronics. Two types of the PBGA were chosen, and the chips were surface mounted without underfill on a daisy chained polyimide printed circuit boards. Two strong levels of the random vibrations were applied sequentially to investigate the sustainability of the PBGA chips mounted on the polyimide PCB with aluminum frame. It was found that the test results did not show any solder failure under the test conditions, indicating the robust structural integrity and providing the evidences justifying the PBGA packaging application to the aerospace applications. Numerical analyses were also performed for the solder stress development mechanism. The results demonstrated that the first natural mode was not necessarily the dominant source for the maximum solder stress, and higher stress could be induced at higher natural modes depending on the chip size and its location.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"27 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86036794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059414
Kyle Pawlowski, Sumit Chkravarty, A. Joginipelly
A major problem in circuit board remanufacturing is the identification of parametric faults from age or stress to the individual passive components. We propose a deep machine learning system for simulating and identifying such faults. A simulated dataset is generated for the most common faults in a circuit. This dataset is used to train deep machine learning classification algorithms to identify and classify the faults. The accuracy of system is measured by comparing with real circuit boards in operation.
{"title":"Simulation and Fault Diagnosis in Post-Manufacturing Mixed Signal Circuits","authors":"Kyle Pawlowski, Sumit Chkravarty, A. Joginipelly","doi":"10.23919/PanPacific48324.2020.9059414","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059414","url":null,"abstract":"A major problem in circuit board remanufacturing is the identification of parametric faults from age or stress to the individual passive components. We propose a deep machine learning system for simulating and identifying such faults. A simulated dataset is generated for the most common faults in a circuit. This dataset is used to train deep machine learning classification algorithms to identify and classify the faults. The accuracy of system is measured by comparing with real circuit boards in operation.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"16 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75649063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059551
Cameron E. Shearon
Historically, Cyber Security has been limited to software. Because of IPC 1782, IPC 2581, and IPC 2591, it is possible to know exactly what hardware is in any electronic device. Therefore, hardware can be part of the Cyber Security solution. In addition, by coupling the hardware and software Cyber Security approaches with the Framework for End to End in Situ Monitoring described in Section 9.5 of ETSI GS NFV-REL 004 V1.1.1 (2016-04), a comprehensive Cyber Security solution can be created. Implementing IPC 1782, IPC 2581, and IPC 2591 with a very innovative labeling system within a factory and across the Supply Chain will increase yields, improve Quality, and Improve Reliability, as well as, make these items much more predictable. In addition to productivity gains, implementing these standards across the Supply Chain will fight counterfeits systematically. Because counterfeiters are opportunistic and operate in the “dark” by surprise attacks, they are like guerilla fighters in a sense. The best way to deal with this type of “attack” is by taking a systematic approach and shining light, by sharing information, where there is currently darkness. Combining these three IPC standards with other technologies such as innovative tagging technologies, Blockchain, The Cloud, and Big Data Tools enable unprecedented productivity gains not seen since interchangeable parts enabled the Industrial Revolution, as well as, the ability to catch counterfeits in situ before the components go through the next process step in a factory. This can be done regardless of the path taken from the original manufacturing site to the next downstream manufacturer. The true beauty of this approach is that no single entity shoulders the cost of this solution. Variability causes yield, quality, reliability (quality over time), and product safety issues. Interchangeable parts enabled the industrial revolution because they addressed variability. What gets measured tends to get managed. This combination of tools enables a tailorable solution that is proportionate to the need and available resources. Therefore, this solution fits very well with Smart Factory/Industry 4.0, materially increases productivity, and can be utilized to create entirely new business models, as well as, a practical way to address the risk of counterfeits and Cyber Security for a very long time.
{"title":"The New Standard for Cyber Security","authors":"Cameron E. Shearon","doi":"10.23919/PanPacific48324.2020.9059551","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059551","url":null,"abstract":"Historically, Cyber Security has been limited to software. Because of IPC 1782, IPC 2581, and IPC 2591, it is possible to know exactly what hardware is in any electronic device. Therefore, hardware can be part of the Cyber Security solution. In addition, by coupling the hardware and software Cyber Security approaches with the Framework for End to End in Situ Monitoring described in Section 9.5 of ETSI GS NFV-REL 004 V1.1.1 (2016-04), a comprehensive Cyber Security solution can be created. Implementing IPC 1782, IPC 2581, and IPC 2591 with a very innovative labeling system within a factory and across the Supply Chain will increase yields, improve Quality, and Improve Reliability, as well as, make these items much more predictable. In addition to productivity gains, implementing these standards across the Supply Chain will fight counterfeits systematically. Because counterfeiters are opportunistic and operate in the “dark” by surprise attacks, they are like guerilla fighters in a sense. The best way to deal with this type of “attack” is by taking a systematic approach and shining light, by sharing information, where there is currently darkness. Combining these three IPC standards with other technologies such as innovative tagging technologies, Blockchain, The Cloud, and Big Data Tools enable unprecedented productivity gains not seen since interchangeable parts enabled the Industrial Revolution, as well as, the ability to catch counterfeits in situ before the components go through the next process step in a factory. This can be done regardless of the path taken from the original manufacturing site to the next downstream manufacturer. The true beauty of this approach is that no single entity shoulders the cost of this solution. Variability causes yield, quality, reliability (quality over time), and product safety issues. Interchangeable parts enabled the industrial revolution because they addressed variability. What gets measured tends to get managed. This combination of tools enables a tailorable solution that is proportionate to the need and available resources. Therefore, this solution fits very well with Smart Factory/Industry 4.0, materially increases productivity, and can be utilized to create entirely new business models, as well as, a practical way to address the risk of counterfeits and Cyber Security for a very long time.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"1 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84431779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059332
Seth Gordon, T. Sanders, A. Raj, Christy Evans, Tom Devall, Gregory Harris, John L. Evans
Electronic products are continuing to improve and evolve with new and innovative packaging technology. With these advancements and the legislation banning SnPb, the reliability of lead-free solder materials has become a high priority. When considering the effects of isothermal aging on the relative reliability of various electronic packages, the data indicates packages will show various decreased levels of reliability as aging is increased. The most commonly used lead-free solder, SAC305, has shown increased levels of reliability compared to SnPb, but as the solder material is aged, the reliability begins to degrade at an exceedingly high rate when compared with other materials. Multiple lead-free solder materials with various combinations of metals have been examined to provide a solution for this high degradation rate. This paper examines the degradation rate as aging time is increased in multiple lead-free solder materials combined with the CABGA208 package when subjected to multiple test conditions. The CABGA208 package is an excellent example of this trend based on the level of failure throughout the various test and the rate of degradation. For each test performed, the CABGA208 package exhibited high failure rates with most test groups having 100% failure. The testing method includes thermal cycling between −40°C to 125°C. A comparison between 0-month (no aging) and 24-month aging was performed to measure the reliability of the solder joints using degradation plots through use of Weibull analysis. Results show a systemic adverse effect of aging time on package level reliability in multiple harsh environments.
{"title":"Degradation of Leadfree Solder Materials Subjected to Isothermal Aging with Use of the CABGA208 Package","authors":"Seth Gordon, T. Sanders, A. Raj, Christy Evans, Tom Devall, Gregory Harris, John L. Evans","doi":"10.23919/PanPacific48324.2020.9059332","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059332","url":null,"abstract":"Electronic products are continuing to improve and evolve with new and innovative packaging technology. With these advancements and the legislation banning SnPb, the reliability of lead-free solder materials has become a high priority. When considering the effects of isothermal aging on the relative reliability of various electronic packages, the data indicates packages will show various decreased levels of reliability as aging is increased. The most commonly used lead-free solder, SAC305, has shown increased levels of reliability compared to SnPb, but as the solder material is aged, the reliability begins to degrade at an exceedingly high rate when compared with other materials. Multiple lead-free solder materials with various combinations of metals have been examined to provide a solution for this high degradation rate. This paper examines the degradation rate as aging time is increased in multiple lead-free solder materials combined with the CABGA208 package when subjected to multiple test conditions. The CABGA208 package is an excellent example of this trend based on the level of failure throughout the various test and the rate of degradation. For each test performed, the CABGA208 package exhibited high failure rates with most test groups having 100% failure. The testing method includes thermal cycling between −40°C to 125°C. A comparison between 0-month (no aging) and 24-month aging was performed to measure the reliability of the solder joints using degradation plots through use of Weibull analysis. Results show a systemic adverse effect of aging time on package level reliability in multiple harsh environments.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"93 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77211491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059521
R. Tummala, Bartlet H. Deprospo, Shreya Dwarakanath, Siddharth Ravichandran, Pratik Nimbalkar, N. Nedumthakady, M. Swaminathan
The semiconductor and systems landscape are changing dramatically. As Moore's law begins to come to an end for many reasons that include minimal increase in transistor performance and in computer performance from node to node but at higher power, the industry has begun to shift to interconnections, referred to as Moore's law for Packaging. This focus addresses both the need for homogeneous and heterogeneous integrations by interconnecting smaller chips and smaller components with higher performance at lower cost and interconnecting them as multichip in 2.5 and 3D architectures. This is also called extending Moore's law, not in a single chip but with multiple chips interconnected horizontally and vertically. This strategy is very consistent with the dramatic and emerging changes in electronic systems such as in HPC, AI and a new era of self-driving and electric cars that potentially think and drive better than humans. This requires device, packaging, and computing architecture paradigms with an entirely different vision and strategy than transistor scaling alone. Packaging, which can be viewed broadly as system scaling, is now viewed as replacing Moore's law for enabling better devices and better systems, unlike in the past. Glass packaging is being developed by Georgia Tech and its industry partners, as the most leading-edge packaging, consistent with the above systems needs in cost, performance, functionality, reliability, and miniaturization. This paper describes the critical glass packaging technologies, their R&D and commercialization status as well as all the current and future applications. It compares and contrasts glass packaging against other leading-edge technologies such as Si and embedded packaging.
{"title":"Glass Panel Packaging, as the Most Leading-Edge Packaging: Technologies and Applications","authors":"R. Tummala, Bartlet H. Deprospo, Shreya Dwarakanath, Siddharth Ravichandran, Pratik Nimbalkar, N. Nedumthakady, M. Swaminathan","doi":"10.23919/PanPacific48324.2020.9059521","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059521","url":null,"abstract":"The semiconductor and systems landscape are changing dramatically. As Moore's law begins to come to an end for many reasons that include minimal increase in transistor performance and in computer performance from node to node but at higher power, the industry has begun to shift to interconnections, referred to as Moore's law for Packaging. This focus addresses both the need for homogeneous and heterogeneous integrations by interconnecting smaller chips and smaller components with higher performance at lower cost and interconnecting them as multichip in 2.5 and 3D architectures. This is also called extending Moore's law, not in a single chip but with multiple chips interconnected horizontally and vertically. This strategy is very consistent with the dramatic and emerging changes in electronic systems such as in HPC, AI and a new era of self-driving and electric cars that potentially think and drive better than humans. This requires device, packaging, and computing architecture paradigms with an entirely different vision and strategy than transistor scaling alone. Packaging, which can be viewed broadly as system scaling, is now viewed as replacing Moore's law for enabling better devices and better systems, unlike in the past. Glass packaging is being developed by Georgia Tech and its industry partners, as the most leading-edge packaging, consistent with the above systems needs in cost, performance, functionality, reliability, and miniaturization. This paper describes the critical glass packaging technologies, their R&D and commercialization status as well as all the current and future applications. It compares and contrasts glass packaging against other leading-edge technologies such as Si and embedded packaging.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"9 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82294864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059483
Thomas A. Okrasinski, M. Benowitz
In this paper we describe a simplified approach for estimating the environmental impact of Information and Communications Technology (ICT) products. The approach provides a means to more quickly and easily evaluate product concepts and optimize design trade-offs. It uses simplified techniques and algorithms for estimating Global Warming Potential in terms of carbon dioxide equivalents. We will also share the development of the environmental impact estimator, including its applicability, validation, along with current and proposed activities to further advance its capabilities for more general use.
{"title":"Quantifying Environmental Life Cycle Impacts for ICT Products - A Simpler Approach","authors":"Thomas A. Okrasinski, M. Benowitz","doi":"10.23919/PanPacific48324.2020.9059483","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059483","url":null,"abstract":"In this paper we describe a simplified approach for estimating the environmental impact of Information and Communications Technology (ICT) products. The approach provides a means to more quickly and easily evaluate product concepts and optimize design trade-offs. It uses simplified techniques and algorithms for estimating Global Warming Potential in terms of carbon dioxide equivalents. We will also share the development of the environmental impact estimator, including its applicability, validation, along with current and proposed activities to further advance its capabilities for more general use.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77787301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-01DOI: 10.23919/PanPacific48324.2020.9059466
O. Suzuki
Various types of advanced packages are available, including Fan-Out Wafer Level Package (FO-WLP), Flip-Chip Chip-Scale Package (FC-CSP) and Flip-Chip Ball Grid Arrays (FC-BGA) packages. These advanced packages are migrating to multi-chip package architectures such as 2.3D, 2.5D technology [1]–[6]. These advanced ball grid arrays (BGAs) incorporate multiple dies on a substrate or an interposer. This paper examines the motivation for the move toward heterogeneous integration of multi-chip architecture by a comparison of die size and die yield. It also reports the results of the 2.5D package trend analysis. By comparing a silicon interposer with a redistribution layer (RDL) interposer, further simulations were performed to investigate the thermomechanical stress behavior of an interposer package against the warpage of the package and tensile stress of underfill and micro-bumps [7]. For a multi-die interposer package, underfill seals below and between the die areas. Between the dies, the underfill was sealed vertically like a wall. The stress distribution of the underfill between the die and the interposer, the underfill between the interposer and the substrate, and the vertical underfill wall is discussed. Low Coefficient-of-Thermal-Expansion (CTE)/high modulus underfill was compared to high CTE/low modulus underfill in the same interposer package.
{"title":"Recent Advances in Underfill for New Package Architectures","authors":"O. Suzuki","doi":"10.23919/PanPacific48324.2020.9059466","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059466","url":null,"abstract":"Various types of advanced packages are available, including Fan-Out Wafer Level Package (FO-WLP), Flip-Chip Chip-Scale Package (FC-CSP) and Flip-Chip Ball Grid Arrays (FC-BGA) packages. These advanced packages are migrating to multi-chip package architectures such as 2.3D, 2.5D technology [1]–[6]. These advanced ball grid arrays (BGAs) incorporate multiple dies on a substrate or an interposer. This paper examines the motivation for the move toward heterogeneous integration of multi-chip architecture by a comparison of die size and die yield. It also reports the results of the 2.5D package trend analysis. By comparing a silicon interposer with a redistribution layer (RDL) interposer, further simulations were performed to investigate the thermomechanical stress behavior of an interposer package against the warpage of the package and tensile stress of underfill and micro-bumps [7]. For a multi-die interposer package, underfill seals below and between the die areas. Between the dies, the underfill was sealed vertically like a wall. The stress distribution of the underfill between the die and the interposer, the underfill between the interposer and the substrate, and the vertical underfill wall is discussed. Low Coefficient-of-Thermal-Expansion (CTE)/high modulus underfill was compared to high CTE/low modulus underfill in the same interposer package.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"312 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79696529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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