Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696439
A. Larsson, Christian Bjørge Thoresen, Thomas Aamli
Off-eutectic Au–Ge, $10 pm 2$ at.% Ge, were formed between Au metallized Si substrates to investigate their high temperature compatibility. High quality joints made with a small bond pressure, 53 kPa, were fabricated. The joints comprised three different types of morphologies; (1) a layered structure of Au / Au–Ge / Au, (2); a layered structure of Au / Au–Ge / Au where some sections of the central Au–Ge band were replaced by a Au section that extended across the joint, and (3); a roughly homogenous Au layer. Joints formed with a higher bond line pressure, 7.6 MPa, were of a reduced quality with voids and cracks at the original bond line. The shear strength of the fabricated joints was found to be at least 50 MPa, and the fracture mode was an adhesive fracture at the adhesion layer. The effective melting point were found to be at least 460°C, or 100°C above the eutectic isotherm of the binary Au–Ge system. Electrical resistivity measurements confirmed a melting process at the eutectic isotherm by an abrupt increase in resistivity.
非共晶Au-Ge， $10 pm 2$ at。在Au金属化Si衬底之间形成了% Ge，研究了它们的高温相容性。制作了高质量的连接，连接压力小，为53 kPa。关节包括三种不同的形态;(1) Au / Au - ge / Au层状结构，(2);Au / Au - ge / Au的层状结构，其中中央Au - ge带的某些部分被延伸到节理上的Au段所取代;一个大致均匀的金层。在较高的结合线压力(7.6 MPa)下形成的接头质量下降，在原结合线上出现空洞和裂纹。结果表明，所制备接头的抗剪强度至少为50 MPa，在粘结层处断裂方式为粘结断裂。有效熔点比二元Au-Ge体系的共晶等温线高至少460℃或100℃。电阻率测量通过电阻率的突然增加证实了共晶等温线上的熔化过程。
{"title":"Partially Liquid Interconnects With The Au–Ge System – Mechanical Strength and Electrical Resistivity","authors":"A. Larsson, Christian Bjørge Thoresen, Thomas Aamli","doi":"10.23919/PANPACIFIC.2019.8696439","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696439","url":null,"abstract":"Off-eutectic Au–Ge, $10 pm 2$ at.% Ge, were formed between Au metallized Si substrates to investigate their high temperature compatibility. High quality joints made with a small bond pressure, 53 kPa, were fabricated. The joints comprised three different types of morphologies; (1) a layered structure of Au / Au–Ge / Au, (2); a layered structure of Au / Au–Ge / Au where some sections of the central Au–Ge band were replaced by a Au section that extended across the joint, and (3); a roughly homogenous Au layer. Joints formed with a higher bond line pressure, 7.6 MPa, were of a reduced quality with voids and cracks at the original bond line. The shear strength of the fabricated joints was found to be at least 50 MPa, and the fracture mode was an adhesive fracture at the adhesion layer. The effective melting point were found to be at least 460°C, or 100°C above the eutectic isotherm of the binary Au–Ge system. Electrical resistivity measurements confirmed a melting process at the eutectic isotherm by an abrupt increase in resistivity.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"21 1","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82112733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696317
Masao Tomikawa, Akira Shimada, Yoichi Shimba
High thermal conductive adhesive sheet whose dielectric constant (Dk) is 5.0 was developed. To obtain low Dk. low Dk matrix polyimide resin whose Dk is 2.6 was designed to decrease Dk as much as possible. To obtain high thermal conductivity, h-BN sphere shaped filler was used as a main heat thermal conductive filler. The h-BN sphere shaped filler shows high thermal conductivity (40W/mK) as bulk filler and low Dk (4.0). High thermal conductive adhesive was obtained by mixing the h-BN cohesive filler into the low Dk polyimide matrix resinIn addition, to make heat path in the high thermal conductive adhesive to z-direction, AlN whisker was oriented to z-direction in the thermal conductive adhesive. We successfully developed novel method to disperse AlN whiskers to z-direction preferably. By utilizing the alignment method, thermal conductivity of the materials increased drastically.As a result, the heat conductive sheet shows the heat conductivity of 15W/mK with low dielectric constant. In addition, the sheet shows excellent break down voltage. The adhesive sheet is suitable for Thermal Interface Material (TIM) for high voltage power modules.
{"title":"High Thermal Conductive Adhesive Sheet with Low Dielectric Constant","authors":"Masao Tomikawa, Akira Shimada, Yoichi Shimba","doi":"10.23919/PANPACIFIC.2019.8696317","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696317","url":null,"abstract":"High thermal conductive adhesive sheet whose dielectric constant (Dk) is 5.0 was developed. To obtain low Dk. low Dk matrix polyimide resin whose Dk is 2.6 was designed to decrease Dk as much as possible. To obtain high thermal conductivity, h-BN sphere shaped filler was used as a main heat thermal conductive filler. The h-BN sphere shaped filler shows high thermal conductivity (40W/mK) as bulk filler and low Dk (4.0). High thermal conductive adhesive was obtained by mixing the h-BN cohesive filler into the low Dk polyimide matrix resinIn addition, to make heat path in the high thermal conductive adhesive to z-direction, AlN whisker was oriented to z-direction in the thermal conductive adhesive. We successfully developed novel method to disperse AlN whiskers to z-direction preferably. By utilizing the alignment method, thermal conductivity of the materials increased drastically.As a result, the heat conductive sheet shows the heat conductivity of 15W/mK with low dielectric constant. In addition, the sheet shows excellent break down voltage. The adhesive sheet is suitable for Thermal Interface Material (TIM) for high voltage power modules.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"109 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84501803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696733
Phillip Isaacs, T. Munson
During the last 25 years, major shifts occurred in the electronic assembly industry, such as the transition to contract manufacturing and reduction or elimination of in house manufacturing, the switch from solvent cleaned rosin fluxes to low solids no-clean fluxes and the big shift from leaded solder to Lead-Free solders. The preferred method for cleaning high reliability surface mount assemblies was to employ a suitable solvent batch or inline machine, to clean traditional leaded rosin flux wave solder solvent wash process (Figure 1).1 The fluxes would be reduced from the Printed Circuit Board Assembly (PCBA) with a solvent degreasing process. Visually the board would appear very clean because of the reduction of the amber flux, but when the boards were placed in a water environment the clear flux residue around the leads would turn white. Traditional rosin flux, left a clear film on the board and sealed in the board fabrication and flux activators and visually appeared clean. This is because the solvents used to clean the flux only removed the top 2/3rds off the surface and left a clear film.PCBA cleanliness was monitored using visual inspection and a ROSE (Resistivity OF Solvent Extraction) test system of a process that meet product validation. The ROSE test measured the amount of equivalent m grams of NaCl/sq. cm, by immersing the PCBA in a solution of 75% IPA/25% water.2 This total board average cleanliness reading was a result of the change in the conductivity and the algorithm used to calculate the detectable contamination.3 IPA was selected as weaker solvent that was in the degreasers to soften the rosin and measure the extractable activators and yet safe to labels and ink ID markings.The use of this ROSE monitor for historical rosin-based fluxes with solvent cleaned assemblies appeared to meet the needs of the time, but when the entire chemistry of electronic assembly changed, including fluxes (no solids), laminates, soldermask and not cleaning, this tool was not able to correlate to field performance as a predictor of reliability.Process monitoring of the new no-clean or cleaned processes that passed a ROSE test on the production floor may, or may not, pass during environmental testing, or perform well in the field. As technology has expanded in areas of use, miniaturization and circuit sensitivity, the traditional total board average cleanliness has not correlated to the failure areas that are under a component, between vias, pads, or leads requiring a new definition of cleanliness and how it is assessed.4, , This can be seen in IPC 5702 and 5704 that the IPC recommends that each company determine what level of cleanliness that they require to be included on their print and has not established cleanliness guidelines.6The proliferation of electronics in all aspects of life including medical, wearables, telecom, cell and automobiles is on an exponential growth curve.7, , As electronics complexity increases (Figure 2), the spacing between
{"title":"Cleanliness Requirements: A Moving Target","authors":"Phillip Isaacs, T. Munson","doi":"10.23919/PANPACIFIC.2019.8696733","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696733","url":null,"abstract":"During the last 25 years, major shifts occurred in the electronic assembly industry, such as the transition to contract manufacturing and reduction or elimination of in house manufacturing, the switch from solvent cleaned rosin fluxes to low solids no-clean fluxes and the big shift from leaded solder to Lead-Free solders. The preferred method for cleaning high reliability surface mount assemblies was to employ a suitable solvent batch or inline machine, to clean traditional leaded rosin flux wave solder solvent wash process (Figure 1).1 The fluxes would be reduced from the Printed Circuit Board Assembly (PCBA) with a solvent degreasing process. Visually the board would appear very clean because of the reduction of the amber flux, but when the boards were placed in a water environment the clear flux residue around the leads would turn white. Traditional rosin flux, left a clear film on the board and sealed in the board fabrication and flux activators and visually appeared clean. This is because the solvents used to clean the flux only removed the top 2/3rds off the surface and left a clear film.PCBA cleanliness was monitored using visual inspection and a ROSE (Resistivity OF Solvent Extraction) test system of a process that meet product validation. The ROSE test measured the amount of equivalent m grams of NaCl/sq. cm, by immersing the PCBA in a solution of 75% IPA/25% water.2 This total board average cleanliness reading was a result of the change in the conductivity and the algorithm used to calculate the detectable contamination.3 IPA was selected as weaker solvent that was in the degreasers to soften the rosin and measure the extractable activators and yet safe to labels and ink ID markings.The use of this ROSE monitor for historical rosin-based fluxes with solvent cleaned assemblies appeared to meet the needs of the time, but when the entire chemistry of electronic assembly changed, including fluxes (no solids), laminates, soldermask and not cleaning, this tool was not able to correlate to field performance as a predictor of reliability.Process monitoring of the new no-clean or cleaned processes that passed a ROSE test on the production floor may, or may not, pass during environmental testing, or perform well in the field. As technology has expanded in areas of use, miniaturization and circuit sensitivity, the traditional total board average cleanliness has not correlated to the failure areas that are under a component, between vias, pads, or leads requiring a new definition of cleanliness and how it is assessed.4, , This can be seen in IPC 5702 and 5704 that the IPC recommends that each company determine what level of cleanliness that they require to be included on their print and has not established cleanliness guidelines.6The proliferation of electronics in all aspects of life including medical, wearables, telecom, cell and automobiles is on an exponential growth curve.7, , As electronics complexity increases (Figure 2), the spacing between","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"34 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82613831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696754
Prabjit Singh, L. Palmer, H. Fu, Dem Lee, J. Lee, Karlos Guo, J. Liu, Simon Lee, Geoffrey Tong, Chen Xu
Knowledge of the rates at which an atmosphere will corrode metals has benefits. Corrosion rate is an indirect, though reliable indication of the concentrations of corrosive gases in the air. Today’s data centers require that for computers to work reliably, the corrosion rates of copper and silver foils, in terms of the rates of growth of corrosion products, be less than 300 and 200 Å/month, respectively. One of the industry standard size of metal foils used for reactive monitoring of air corrosivity is 25x50 mm. The thickness of the corrosion products on the foils is measured using coulometric reduction. The other means of measuring corrosion rates is electrical resistance increase of metal serpentine thin films. Serpentine thin films have smaller surface areas, finer grain sizes and higher mechanical stresses compared to metal foils. Both these factors increase corrosion rates. This paper compares the corrosion rates of metal films and foils. The corrosion rates of two different area metal foils were measured using coulometric reduction and compared with the corrosion rates of metal serpentine thin films using resistance increase and coulometric reduction techniques.
{"title":"Recent Advances in Reactive Monitoring of Air Corrosivity","authors":"Prabjit Singh, L. Palmer, H. Fu, Dem Lee, J. Lee, Karlos Guo, J. Liu, Simon Lee, Geoffrey Tong, Chen Xu","doi":"10.23919/PANPACIFIC.2019.8696754","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696754","url":null,"abstract":"Knowledge of the rates at which an atmosphere will corrode metals has benefits. Corrosion rate is an indirect, though reliable indication of the concentrations of corrosive gases in the air. Today’s data centers require that for computers to work reliably, the corrosion rates of copper and silver foils, in terms of the rates of growth of corrosion products, be less than 300 and 200 Å/month, respectively. One of the industry standard size of metal foils used for reactive monitoring of air corrosivity is 25x50 mm. The thickness of the corrosion products on the foils is measured using coulometric reduction. The other means of measuring corrosion rates is electrical resistance increase of metal serpentine thin films. Serpentine thin films have smaller surface areas, finer grain sizes and higher mechanical stresses compared to metal foils. Both these factors increase corrosion rates. This paper compares the corrosion rates of metal films and foils. The corrosion rates of two different area metal foils were measured using coulometric reduction and compared with the corrosion rates of metal serpentine thin films using resistance increase and coulometric reduction techniques.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"19 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80456897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696712
Dwight Howard
Product development is increasingly challenging. Competition demands that ideas be evolved from concept to products shipping into the marketplace in the shortest possible time. Markets are demanding more from technologies. To meet these demands, engineers must utilize the most advanced capabilities that are available. Engineers must minimize time and cost to speed design, development, validation and release to manufacturing. increasing complexities in physical products. Electronics has led the way in feature growth and complexities. Additionally, software magnifies complexities exponentially. Traditional methods of bringing products from concept to production cannot provide the means engineers need to meet the challenges. Computer-based models of physical hardware are critical to meeting current and future challenges. This presentation discusses the promise of the so-called “Digital Twin” and how it may facilitate virtual validation of hardware to facilitate rapid development at least cost in time and manpower while achieving optimized designs by way of “virtual validation”. Discussion regarding digital twins has risen to the forefront as the way of the future. This paper will also identify primary challenges that proponents and visionaries of this concept have cited as the major hurtles that must be overcome.
{"title":"The Digital Twin: Virtual Validation In Electronics Development And Design","authors":"Dwight Howard","doi":"10.23919/PANPACIFIC.2019.8696712","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696712","url":null,"abstract":"Product development is increasingly challenging. Competition demands that ideas be evolved from concept to products shipping into the marketplace in the shortest possible time. Markets are demanding more from technologies. To meet these demands, engineers must utilize the most advanced capabilities that are available. Engineers must minimize time and cost to speed design, development, validation and release to manufacturing. increasing complexities in physical products. Electronics has led the way in feature growth and complexities. Additionally, software magnifies complexities exponentially. Traditional methods of bringing products from concept to production cannot provide the means engineers need to meet the challenges. Computer-based models of physical hardware are critical to meeting current and future challenges. This presentation discusses the promise of the so-called “Digital Twin” and how it may facilitate virtual validation of hardware to facilitate rapid development at least cost in time and manpower while achieving optimized designs by way of “virtual validation”. Discussion regarding digital twins has risen to the forefront as the way of the future. This paper will also identify primary challenges that proponents and visionaries of this concept have cited as the major hurtles that must be overcome.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"26 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87066738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696578
Dwight Howard
Safety-critical applications have long been a significant and formidable challenge for product development and deployment. This challenge is increasing as more complex technologies are introduced. Sophisticated technologies like Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) are pacing the capabilities of automated design and development tools. The tremendous effort involved in meeting functional safety standards like ISO 26262 exceeds most staffing levels. Attempting to address this with largely manual effort appears to be virtually impractical. Automating functional safety in product design, development and production processes is essential. For this to be possible, Engineering Design Automation tools must be able to support functional safety compliant design activities. EDA tools suppliers are stepping up to this challenge. EDA tools targeted for functional safety design and compliance verification are gradually coming into the market. It is not clear that these tools can meet the total needs of product design and development. This paper will provide a high-level, general perspective regarding this question.Functional safety standards have broad scope across many industries. The reader is encouraged to explore any industries where functional safety standards are in place. The scope of this paper is limited to automotive applications and, as stated above, the role EDA tools for the design of automotive electronics must fill to meet the challenges functional safety requirements place upon automotive electronics product development processes.
{"title":"Functional Safety and Engineering Design Automation","authors":"Dwight Howard","doi":"10.23919/PANPACIFIC.2019.8696578","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696578","url":null,"abstract":"Safety-critical applications have long been a significant and formidable challenge for product development and deployment. This challenge is increasing as more complex technologies are introduced. Sophisticated technologies like Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) are pacing the capabilities of automated design and development tools. The tremendous effort involved in meeting functional safety standards like ISO 26262 exceeds most staffing levels. Attempting to address this with largely manual effort appears to be virtually impractical. Automating functional safety in product design, development and production processes is essential. For this to be possible, Engineering Design Automation tools must be able to support functional safety compliant design activities. EDA tools suppliers are stepping up to this challenge. EDA tools targeted for functional safety design and compliance verification are gradually coming into the market. It is not clear that these tools can meet the total needs of product design and development. This paper will provide a high-level, general perspective regarding this question.Functional safety standards have broad scope across many industries. The reader is encouraged to explore any industries where functional safety standards are in place. The scope of this paper is limited to automotive applications and, as stated above, the role EDA tools for the design of automotive electronics must fill to meet the challenges functional safety requirements place upon automotive electronics product development processes.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"1 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83068409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696695
R. Hollman
Electronics packaging technology has been in a period of rapid technology advancement for a number of years, as the package takes on a larger role in improving the cost and performance of systems, such as laptops, tablets and smart phones. This trend will only increase with the introduction of 5G networks, the rising electronics content of automobiles, and the general proliferation of connected systems.The challenges for packaging include handling a greater density of interconnections, connecting multiple chips in the same package and managing greater heat loads by mitigating the stresses they create. The higher frequencies associated with 5G will require new structures and fabrication techniques to minimize signal delays and losses, especially between chips within a package.The smaller interconnect features and tighter specifications blur the boundary between wafer processing and packaging: many of the processes that were historically part of the fab line are finding their way into the packaging process. However, the materials, structures and specifications are very different, and this presents both a challenge and an opportunity. The players who find creative applications for wafer fabrication processes will differentiate themselves from the competition and win market share.We will focus here on a selection of new features for Cu plating in advanced packaging, and which pose special challenges to the process. Some of them, such as embedded conductor for RDL and large via fill plus pad, require a variation of the preferential “bottom up” Cu deposition used in damascene and TSV (Through Silicon Via) processes. We will discuss how the plating chemistry and process is adapted to create these new features in an advanced packaging process flow.
{"title":"From Wafer Processing To Advanced Packaging: Broadening The Applications For Tsv’S Beyond The High End","authors":"R. Hollman","doi":"10.23919/PANPACIFIC.2019.8696695","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696695","url":null,"abstract":"Electronics packaging technology has been in a period of rapid technology advancement for a number of years, as the package takes on a larger role in improving the cost and performance of systems, such as laptops, tablets and smart phones. This trend will only increase with the introduction of 5G networks, the rising electronics content of automobiles, and the general proliferation of connected systems.The challenges for packaging include handling a greater density of interconnections, connecting multiple chips in the same package and managing greater heat loads by mitigating the stresses they create. The higher frequencies associated with 5G will require new structures and fabrication techniques to minimize signal delays and losses, especially between chips within a package.The smaller interconnect features and tighter specifications blur the boundary between wafer processing and packaging: many of the processes that were historically part of the fab line are finding their way into the packaging process. However, the materials, structures and specifications are very different, and this presents both a challenge and an opportunity. The players who find creative applications for wafer fabrication processes will differentiate themselves from the competition and win market share.We will focus here on a selection of new features for Cu plating in advanced packaging, and which pose special challenges to the process. Some of them, such as embedded conductor for RDL and large via fill plus pad, require a variation of the preferential “bottom up” Cu deposition used in damascene and TSV (Through Silicon Via) processes. We will discuss how the plating chemistry and process is adapted to create these new features in an advanced packaging process flow.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"39 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82461307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696308
J. Semmens
Acoustic micro imaging (AMI) uses high frequency ultrasound (5 to 500 MHz) to image the internal features of samples. Ultrasound is sensitive to variations in the elastic properties of materials and is particularly sensitive to locating air gaps. X-Ray uses short wavelength electromagnetic radiation capable of penetrating most materials to look for discontinuities such as voids in solder bonds. One method may be better for the detection of specific defect types. For instance very thin gaps (delaminations) in a plastic encapsulated package are readily detected using AMI. However, they can be overlooked using X-Ray unless the device is viewed at the correct angle. Another method may be better for accessing the area of interest in the sample through certain types of materials. In plastic encapsulated parts, evaluation of wire bonds is limited using AMI as lower frequencies that have lower resolution are required to penetrate the molding compound. X-Ray however readily penetrates the molding material to provide high resolution images of the bond wires. X-Ray also has the advantage of allowing for rotation of the viewing angle. Although there is overlap of applications between AMI and X-Ray imaging, in some cases one technology can provide information that the other cannot. The examples in this paper will demonstrate how both analysis methods, used together, can provide a more comprehensive evaluation of devices or materials.
{"title":"Acoustic Micro Imaging and X-Ray Analysis for More Thorough Evaluation of Microelectronic Devices","authors":"J. Semmens","doi":"10.23919/PANPACIFIC.2019.8696308","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696308","url":null,"abstract":"Acoustic micro imaging (AMI) uses high frequency ultrasound (5 to 500 MHz) to image the internal features of samples. Ultrasound is sensitive to variations in the elastic properties of materials and is particularly sensitive to locating air gaps. X-Ray uses short wavelength electromagnetic radiation capable of penetrating most materials to look for discontinuities such as voids in solder bonds. One method may be better for the detection of specific defect types. For instance very thin gaps (delaminations) in a plastic encapsulated package are readily detected using AMI. However, they can be overlooked using X-Ray unless the device is viewed at the correct angle. Another method may be better for accessing the area of interest in the sample through certain types of materials. In plastic encapsulated parts, evaluation of wire bonds is limited using AMI as lower frequencies that have lower resolution are required to penetrate the molding compound. X-Ray however readily penetrates the molding material to provide high resolution images of the bond wires. X-Ray also has the advantage of allowing for rotation of the viewing angle. Although there is overlap of applications between AMI and X-Ray imaging, in some cases one technology can provide information that the other cannot. The examples in this paper will demonstrate how both analysis methods, used together, can provide a more comprehensive evaluation of devices or materials.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80103707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.23919/PANPACIFIC.2019.8696289
M. Ishikawa
As electronics products are increasing in complexity year by year, electrical engineers and designers are required to consider many more aspects to hand over their design to manufacturing. These include Safety standards, EMI and ESD, protocol specific standards, DFM (Designing for Manufacturing), and design guidelines provided by IC vendors. Tackling these challenges with simulations is a typical strategy. However, it is not always effective as it takes time to prepare the simulation model as well as the computational time, especially when incorporating 3dimensional electrical-magnetic simulations. This paper proposes a new design verification methodology that includes both rule based geometrical checking and the conventional simulations to improve the efficiency of the entire verification process.
{"title":"A Hybrid PCB Verification Methodology with Geometrical Checks and Simulations","authors":"M. Ishikawa","doi":"10.23919/PANPACIFIC.2019.8696289","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696289","url":null,"abstract":"As electronics products are increasing in complexity year by year, electrical engineers and designers are required to consider many more aspects to hand over their design to manufacturing. These include Safety standards, EMI and ESD, protocol specific standards, DFM (Designing for Manufacturing), and design guidelines provided by IC vendors. Tackling these challenges with simulations is a typical strategy. However, it is not always effective as it takes time to prepare the simulation model as well as the computational time, especially when incorporating 3dimensional electrical-magnetic simulations. This paper proposes a new design verification methodology that includes both rule based geometrical checking and the conventional simulations to improve the efficiency of the entire verification process.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"24 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80216636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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