Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760523
A. Neogi, J. Panda
A triple pass band filter is proposed for wireless applications. Four cross coupled Stepped Impedance Resonators are used for the purpose. Three pass bands at 2.4, 3.5 and 5.4 GHz are achieved. Minimum Insertion Loss of the three pass bands are 1.00, -0.52 and -0.92 dB respectively. The Return Loss in the said pass bands are -27,-21 and -22 dB. The overall size of the designed filter is 24.7 mm x 18 mm (0.19 $lambda_{g}$ x 0.14 $lambda_{g}$). The Defective Ground Surface is introduced in the design to reduce the spurious pass bands and hence to improve the pass band selectivity and stop band suppressions.
提出了一种用于无线应用的三通带滤波器。四个交叉耦合阶跃阻抗谐振器用于此目的。实现了2.4、3.5和5.4 GHz三个通带。三个通带的最小插入损耗分别为1.00、-0.52和-0.92 dB。所述通带的回波损耗为-27、-21和-22 dB。所设计滤波器的整体尺寸为24.7 mm × 18 mm (0.19 $lambda_{g}$ x 0.14 $lambda_{g}$)。在设计中引入缺陷地面以减少杂散通带，从而提高通带选择性和阻带抑制。
{"title":"Triple Band Filter with Cross Coupled SIR for Wireless Applications and Harmonic pass band Rejection with DGS","authors":"A. Neogi, J. Panda","doi":"10.1109/AISP53593.2022.9760523","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760523","url":null,"abstract":"A triple pass band filter is proposed for wireless applications. Four cross coupled Stepped Impedance Resonators are used for the purpose. Three pass bands at 2.4, 3.5 and 5.4 GHz are achieved. Minimum Insertion Loss of the three pass bands are 1.00, -0.52 and -0.92 dB respectively. The Return Loss in the said pass bands are -27,-21 and -22 dB. The overall size of the designed filter is 24.7 mm x 18 mm (0.19 $lambda_{g}$ x 0.14 $lambda_{g}$). The Defective Ground Surface is introduced in the design to reduce the spurious pass bands and hence to improve the pass band selectivity and stop band suppressions.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87164788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760666
M. Reddy, Deepakkumar Panda
IOT (Internet of Things) devices such as connected appliances,smart home security systems,wireless inventory trackers,ultra-high speed wireless internet etc. are a gravitating topic of research. In the trending electronic market we do have number of IOT devices flourishing. The IOT application requires such as compactness, lightness, manageability, form-factor, weight, etc. recite the hallmark of such devices. Tiny, slight, movable, and light weight Internet of Things devices use either rechargeable or Non-rechargeable and avoid the utilization of sources such as primary energy one’s. Because the lifespan of batteries and renewal span are condemnatory problems in battery-operated or partly energy-harvested IOT devices, ultralow-power(UL-P) system-on-chips (So-C) are becoming a extensive solution of chipmakers’ option. These kind of UL-P So-C needs logic as well as Static RAM in the processor to perform at low supply voltage’s. The proposed 12MOSFET SRAM(12T) proves itself operating at very low Supply Voltage. The reproving design metrics of introduced 12MOSFET SRAM Bit-Cell are calculated and differentiated with that of (6MOSFET) CON6T, (7MOSFET)CON7T, (8MOSFET)CON8T and (12MOSFET)CON12T SRAM Bit Cell. The RSNM of introduced 12MOSFET Static RAM Bit Cell reaches $1.7 times$ excessive as differentiated to 7MOSFET and 8MOSFET and rests identical as CON12T. The WSNM of introduced 12MOSFET SRAM Bit Cell reaches $1.8 times$ excessive as differentiated to 8MOSFET//7MOSFET and $1.4 times$ excessive differentiated to CON12T.The introduced 12MOSFET SRAM Bit Cell absorb $0.6127 times$ lower accessing power as compared to 8MOSFET and $0.4637 times$ lower accessing power compared to 7MOSFET and $0.253 times$ low accessing power compared to CON12T.The power of introduced 12MOSFET in Hold mode reaches $0.0499/0.055/ 0.0499 times$ lesser as differentiated to 7MOSFET/ 8MOSFET/ CON12T. EQM of 12MOSFET, as it represents the entire performance of SRAM, is greater when compared with remaining conventional methods.
IOT(物联网)设备，如连接电器，智能家居安全系统，无线库存跟踪器，超高速无线互联网等是一个有吸引力的研究主题。在趋势电子市场中，我们确实有许多物联网设备蓬勃发展。物联网应用要求紧凑、轻便、可管理性、外形尺寸、重量等，这些都是此类设备的特点。小巧、轻巧、可移动、重量轻的物联网设备使用可充电或不可充电，避免使用一次能源等资源。在电池供电或部分能量收集的物联网设备中，电池寿命和更新时间是一个严重的问题，因此超低功耗(UL-P)片上系统(So-C)正成为芯片制造商的广泛解决方案。这种类型的UL-P So-C需要逻辑以及处理器中的静态RAM来在低电源电压下执行。所提出的12MOSFET SRAM(12T)证明自己在非常低的电源电压下工作。计算了引入的12MOSFET SRAM位单元的改进设计指标，并与(6MOSFET) CON6T、(7MOSFET)CON7T、(8MOSFET)CON8T和(12MOSFET)CON12T SRAM位单元的改进设计指标进行了区分。引入的12MOSFET静态RAM位单元的RSNM与7MOSFET和8MOSFET的RSNM相差1.7倍，与CON12T相同。引入的12MOSFET SRAM位单元的WSNM在分化为8MOSFET//7MOSFET时达到$1.8 times excess，分化为CON12T时达到$1.4 times excess。与8MOSFET相比，引入的12MOSFET SRAM位单元的存取功率降低了0.6127美元，与7MOSFET相比，存取功率降低了0.4637美元，与CON12T相比，存取功率降低了0.253美元。与7MOSFET/ 8MOSFET/ CON12T相比，在保持模式下引入的12MOSFET功率达到0.0499/0.055/ 0.0499 $。与其他传统方法相比，12MOSFET的EQM更大，因为它代表了SRAM的全部性能。
{"title":"Design of 12T SRAM with improved stability for IOT application","authors":"M. Reddy, Deepakkumar Panda","doi":"10.1109/AISP53593.2022.9760666","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760666","url":null,"abstract":"IOT (Internet of Things) devices such as connected appliances,smart home security systems,wireless inventory trackers,ultra-high speed wireless internet etc. are a gravitating topic of research. In the trending electronic market we do have number of IOT devices flourishing. The IOT application requires such as compactness, lightness, manageability, form-factor, weight, etc. recite the hallmark of such devices. Tiny, slight, movable, and light weight Internet of Things devices use either rechargeable or Non-rechargeable and avoid the utilization of sources such as primary energy one’s. Because the lifespan of batteries and renewal span are condemnatory problems in battery-operated or partly energy-harvested IOT devices, ultralow-power(UL-P) system-on-chips (So-C) are becoming a extensive solution of chipmakers’ option. These kind of UL-P So-C needs logic as well as Static RAM in the processor to perform at low supply voltage’s. The proposed 12MOSFET SRAM(12T) proves itself operating at very low Supply Voltage. The reproving design metrics of introduced 12MOSFET SRAM Bit-Cell are calculated and differentiated with that of (6MOSFET) CON6T, (7MOSFET)CON7T, (8MOSFET)CON8T and (12MOSFET)CON12T SRAM Bit Cell. The RSNM of introduced 12MOSFET Static RAM Bit Cell reaches $1.7 times$ excessive as differentiated to 7MOSFET and 8MOSFET and rests identical as CON12T. The WSNM of introduced 12MOSFET SRAM Bit Cell reaches $1.8 times$ excessive as differentiated to 8MOSFET//7MOSFET and $1.4 times$ excessive differentiated to CON12T.The introduced 12MOSFET SRAM Bit Cell absorb $0.6127 times$ lower accessing power as compared to 8MOSFET and $0.4637 times$ lower accessing power compared to 7MOSFET and $0.253 times$ low accessing power compared to CON12T.The power of introduced 12MOSFET in Hold mode reaches $0.0499/0.055/ 0.0499 times$ lesser as differentiated to 7MOSFET/ 8MOSFET/ CON12T. EQM of 12MOSFET, as it represents the entire performance of SRAM, is greater when compared with remaining conventional methods.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"15 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90058021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760665
Noel Pereira
Sign language essentially allows for communication without the need to explicitly say words. It was developed by the American School for the Deaf in the early 90’s. It is a naturally generated language which incorporates facial movements and hand gestures to convey thoughts and ideas. In modern times, it is used predominantly by people who are deaf and hard of hearing. Unlike most languages, ASL isn’t widely taught which makes it difficult for the general population to communicate effectively with those people who predominantly use ASL as the sole means of communication. Therefore, arises the need for a system which detects and predicts letters from images and which can then be used in real time to overcome this language barrier. This research aims to develop a sign language recognition system atop of YOLOX, which is built on top of YOLOV3, which contains in its architecture, convolutional neural networks. Using the various backbones of YOLOX, this paper introduces and provides six models on every end of the accuracy-testing time spectrum from least accurate/fastest response time to the most accurate/slowest response time. I thereby propose PereiraASLNet, which trains YOLOX with custom classes from the letters A-Z and a Pascal VOC XML American Sign Language dataset developed by Roboflow and variants of YOLOX have been developed, taking into consideration the mean average precision and inference times of all the YOLOX backbone architectures namely the YOLOX-nano, YOLOX-tiny, YOLOX-small, YOLOX-medium, YOLOX-large and YOLOX-xlarge. The testing mean average precision for the models were found to be – 0.9046, 0.9070, 0.9227, 0.9304, 0.9329 and 0.9578 and the testing inference time was found to be 3.50ms, 12.97ms, 34.86ms, 64.56ms, 83.23ms and 97.56ms respectively
{"title":"PereiraASLNet: ASL letter recognition with YOLOX taking Mean Average Precision and Inference Time considerations","authors":"Noel Pereira","doi":"10.1109/AISP53593.2022.9760665","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760665","url":null,"abstract":"Sign language essentially allows for communication without the need to explicitly say words. It was developed by the American School for the Deaf in the early 90’s. It is a naturally generated language which incorporates facial movements and hand gestures to convey thoughts and ideas. In modern times, it is used predominantly by people who are deaf and hard of hearing. Unlike most languages, ASL isn’t widely taught which makes it difficult for the general population to communicate effectively with those people who predominantly use ASL as the sole means of communication. Therefore, arises the need for a system which detects and predicts letters from images and which can then be used in real time to overcome this language barrier. This research aims to develop a sign language recognition system atop of YOLOX, which is built on top of YOLOV3, which contains in its architecture, convolutional neural networks. Using the various backbones of YOLOX, this paper introduces and provides six models on every end of the accuracy-testing time spectrum from least accurate/fastest response time to the most accurate/slowest response time. I thereby propose PereiraASLNet, which trains YOLOX with custom classes from the letters A-Z and a Pascal VOC XML American Sign Language dataset developed by Roboflow and variants of YOLOX have been developed, taking into consideration the mean average precision and inference times of all the YOLOX backbone architectures namely the YOLOX-nano, YOLOX-tiny, YOLOX-small, YOLOX-medium, YOLOX-large and YOLOX-xlarge. The testing mean average precision for the models were found to be – 0.9046, 0.9070, 0.9227, 0.9304, 0.9329 and 0.9578 and the testing inference time was found to be 3.50ms, 12.97ms, 34.86ms, 64.56ms, 83.23ms and 97.56ms respectively","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"20 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86267345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760661
S. Lakhote, Sumit Kumar, Gaurab Banerjee
Frequency modulated continuous wave (FMCW) radars are being widely used for vital signs detection due to their capability of range determination. Compared to continuous wave (CW) radars, this additional feature of FMCW radars helps in distinguishing between multiple people and targets. In this paper, the impact of voltage controlled oscillator (VCO) non-linearity on vital signs detection is evaluated with detailed mathematical analysis and MATLAB simulations using a transistor-level nonlinearity model. We demonstrate that vital signs detection is indeed possible with a non-linear VCO, when it is used in CW and FMCW radars. This also leads to the conclusion that expensive linear waveform generation techniques are not needed in indoor vital signs monitoring applications. This can substantially reduce the cost of radars-on-chip.
{"title":"Effect of VCO Non-Linearity on Non-Contact Vital Signs Detection in CW and FMCW Radars","authors":"S. Lakhote, Sumit Kumar, Gaurab Banerjee","doi":"10.1109/AISP53593.2022.9760661","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760661","url":null,"abstract":"Frequency modulated continuous wave (FMCW) radars are being widely used for vital signs detection due to their capability of range determination. Compared to continuous wave (CW) radars, this additional feature of FMCW radars helps in distinguishing between multiple people and targets. In this paper, the impact of voltage controlled oscillator (VCO) non-linearity on vital signs detection is evaluated with detailed mathematical analysis and MATLAB simulations using a transistor-level nonlinearity model. We demonstrate that vital signs detection is indeed possible with a non-linear VCO, when it is used in CW and FMCW radars. This also leads to the conclusion that expensive linear waveform generation techniques are not needed in indoor vital signs monitoring applications. This can substantially reduce the cost of radars-on-chip.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"7 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76504744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760553
S. J. Basha, G. L. V. Prasad, K. Vivek, Eedupalli Sai Kumar, Tamminina Ammannamma
Rainfall in India is becoming more unpredictable, leaving it harder to forecast. When it comes to predicting Indian summer monsoon rainfall, the Indian Meteorological Department (IMD) now uses Ensemble methods and Statistical methods. As a result of this, strategists are unable to foresee the socioeconomic consequences of floods (too many rains) or droughts (fewer rains). Precisely how much rain falls depends on several variables such as a measure of the warmth or coldness in the air, moisture, breeze, movement, and direction of the wind. This article will use Ensemble time-series forecasting model ARIMA (Autoregressive Integrated Moving Average)+ GARCH (Generalized Auto-Regressive Conditional Heteroskedasticity) to forecast the intensity of rainfall by considering various meteorological factors like sea-level pressure, moisture, dew point, min-max temperature, snowfall, geopotential height, speed and direction of the wind, humidity, and atmospheric pressure. The suggested Ensemble ARIMA+GARCH model has given good results when compared with individual models and state-of-the-art ensemble approaches in terms of RMSE, MAE, and MSE.
{"title":"Leveraging Ensemble Time-series Forecasting Model to Predict the amount of Rainfall in Andhra Pradesh","authors":"S. J. Basha, G. L. V. Prasad, K. Vivek, Eedupalli Sai Kumar, Tamminina Ammannamma","doi":"10.1109/AISP53593.2022.9760553","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760553","url":null,"abstract":"Rainfall in India is becoming more unpredictable, leaving it harder to forecast. When it comes to predicting Indian summer monsoon rainfall, the Indian Meteorological Department (IMD) now uses Ensemble methods and Statistical methods. As a result of this, strategists are unable to foresee the socioeconomic consequences of floods (too many rains) or droughts (fewer rains). Precisely how much rain falls depends on several variables such as a measure of the warmth or coldness in the air, moisture, breeze, movement, and direction of the wind. This article will use Ensemble time-series forecasting model ARIMA (Autoregressive Integrated Moving Average)+ GARCH (Generalized Auto-Regressive Conditional Heteroskedasticity) to forecast the intensity of rainfall by considering various meteorological factors like sea-level pressure, moisture, dew point, min-max temperature, snowfall, geopotential height, speed and direction of the wind, humidity, and atmospheric pressure. The suggested Ensemble ARIMA+GARCH model has given good results when compared with individual models and state-of-the-art ensemble approaches in terms of RMSE, MAE, and MSE.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"24 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82608838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760587
G. V. Ganesh, Chittaluri Sahithi, Mathi Rashmi Sri, Vaddempudi Sony
This article introduces the two cells of static SRAMS to mitigate static power scattering induced by entry and sub-edge leakage flows. To reduce the door spillage current, the main cell structure employs PMOS pass semiconductors. To prevent sub edge spillage while preserving execution awareness, this design uses two fold breaking point voltage generation with forward body biassing. The succeeding cell shape lowers the entrance voltages for the NMOS pass semiconductors, lowering the door spillage current as a result. Contrasted with a customary SRAM cell, the main cell structure complete power scattering by 0.492mW and current by iddmax=1.661mA.while the subsequent cell structure decreases the all out power dispersal by 0.189mW and current by iddmax=0.488mA.
{"title":"Design and Analysis of Two Low Power SRAM Cell Structures","authors":"G. V. Ganesh, Chittaluri Sahithi, Mathi Rashmi Sri, Vaddempudi Sony","doi":"10.1109/AISP53593.2022.9760587","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760587","url":null,"abstract":"This article introduces the two cells of static SRAMS to mitigate static power scattering induced by entry and sub-edge leakage flows. To reduce the door spillage current, the main cell structure employs PMOS pass semiconductors. To prevent sub edge spillage while preserving execution awareness, this design uses two fold breaking point voltage generation with forward body biassing. The succeeding cell shape lowers the entrance voltages for the NMOS pass semiconductors, lowering the door spillage current as a result. Contrasted with a customary SRAM cell, the main cell structure complete power scattering by 0.492mW and current by iddmax=1.661mA.while the subsequent cell structure decreases the all out power dispersal by 0.189mW and current by iddmax=0.488mA.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"4 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73225722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760577
Akshatha Mohan, Athulya B Mohan, B. Indushree, M. Malavikaa, C. Narendra
Circuit diagrams are used to depict electronic or electrical circuits graphically. It is simple for everyone to put their thoughts on paper. However, in order to conduct simulations in the different available tools, the circuit model needs be in digital form. This project presents several image processing and machine learning approaches for the conversion of hand-drawn circuits to netlists. Rather than training the dataset for all components, a technique based on the length ratios of a few of lines was employed to identify elements such as a voltage source, ground, and capacitor. Various image processing techniques are used to eliminate noise and prepare pictures for further processing. HOG feature extraction is utilized throughout the training and segmentation stages to detect resistor, diode, and inductor components. The final stage is to construct a netlist from the detected elements, wires, and their locations, as well as the identified nodes.
{"title":"Generation of Netlist from a Hand drawn Circuit through Image Processing and Machine Learning","authors":"Akshatha Mohan, Athulya B Mohan, B. Indushree, M. Malavikaa, C. Narendra","doi":"10.1109/AISP53593.2022.9760577","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760577","url":null,"abstract":"Circuit diagrams are used to depict electronic or electrical circuits graphically. It is simple for everyone to put their thoughts on paper. However, in order to conduct simulations in the different available tools, the circuit model needs be in digital form. This project presents several image processing and machine learning approaches for the conversion of hand-drawn circuits to netlists. Rather than training the dataset for all components, a technique based on the length ratios of a few of lines was employed to identify elements such as a voltage source, ground, and capacitor. Various image processing techniques are used to eliminate noise and prepare pictures for further processing. HOG feature extraction is utilized throughout the training and segmentation stages to detect resistor, diode, and inductor components. The final stage is to construct a netlist from the detected elements, wires, and their locations, as well as the identified nodes.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"417 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79171841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760542
Modi Divy Bhavesh, Nair Anoopkumar Anilkumar, Manish I. Patel, Ruchi Gajjar, D. Panchal
The demand for Integrated Circuits (ICs) is increasing exponentially, leading to the challenges of a more reliable and effective Electronic Design Tool (EDA) for the circuit design flow. To overcome such limitations Machine Learning (ML) is used, which can learn from the previous design data and can apply it to the unknown design given to it. In this context, the paper proposes the use of the regression technique of ML to estimate the power consumption of the MOSFET-based digital circuits. For this purpose, to train the ML-based regressor model, a dataset is created from the PMOS based Resistive Load Inverter (RLI), NMOS based RLI, and CMOS-based NAND gate layout. For the formation of the dataset, a 90nm MOS technology node is used and it inculcates the features like capacitance, resistance, number of MOSFET, their respective width and length, and the average power consumption of the respective layout. The regressor model used to predict the power consumption in this work is linear regressor, polynomial regressor, random forest regressor, decision tree regressor, and the extra tree regressor. At last, from the experimental results, it is observed that the extra tree regressor performs better for the RLI circuits with the MSE value of $4.02times 10^{-10}$ and $mathrm{R}^{2}$ value of 0.61, and for the NAND gate, the polynomial linear regressor excels with the MSE value of $7.27times 10^{-10}$ and $mathrm{R}^{2}$ value of 0.65.
{"title":"Power Consumption Prediction of Digital Circuits using Machine Learning","authors":"Modi Divy Bhavesh, Nair Anoopkumar Anilkumar, Manish I. Patel, Ruchi Gajjar, D. Panchal","doi":"10.1109/AISP53593.2022.9760542","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760542","url":null,"abstract":"The demand for Integrated Circuits (ICs) is increasing exponentially, leading to the challenges of a more reliable and effective Electronic Design Tool (EDA) for the circuit design flow. To overcome such limitations Machine Learning (ML) is used, which can learn from the previous design data and can apply it to the unknown design given to it. In this context, the paper proposes the use of the regression technique of ML to estimate the power consumption of the MOSFET-based digital circuits. For this purpose, to train the ML-based regressor model, a dataset is created from the PMOS based Resistive Load Inverter (RLI), NMOS based RLI, and CMOS-based NAND gate layout. For the formation of the dataset, a 90nm MOS technology node is used and it inculcates the features like capacitance, resistance, number of MOSFET, their respective width and length, and the average power consumption of the respective layout. The regressor model used to predict the power consumption in this work is linear regressor, polynomial regressor, random forest regressor, decision tree regressor, and the extra tree regressor. At last, from the experimental results, it is observed that the extra tree regressor performs better for the RLI circuits with the MSE value of $4.02times 10^{-10}$ and $mathrm{R}^{2}$ value of 0.61, and for the NAND gate, the polynomial linear regressor excels with the MSE value of $7.27times 10^{-10}$ and $mathrm{R}^{2}$ value of 0.65.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"5 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75045246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760612
Bhargav Ram Rayapati, N. Rangaswamy, A. V. Bhaskar
This work discusses the availability of cache memories for VoD service in Time and Wavelength Division Multiplexed Passive Optical Network (TWDM PON) ring topology. In a unidirectional ring topology with TWDM PON, the wavelength channels are enabled in an anti-cyclic manner through intermediate devices such as Remote Node (RN) and splitter as per traffic requirements. The provision of cache storage at subsystems of ring topology, namely, Optical Line Terminal (OLT), RN, and Optical Network Unit (ONU) enables the users to access the VoD service within reach rather than from a typical video server. Thus, this mechanism reduces the delay as well as power requirements. However, in this paper the analytical emphasis on the ring topology is confined only to power requirements through two situational cases. In the first case, the cache storage at OLT and ONU is only availed. While in the second case, the cache available at RN was also made to use. It is observed that the power consumption in the second case is lesser than in the first case. Due to more decentralization of cache availability in the second case, relatively 70 % more power savings are observed.
{"title":"Energy Efficient VoD with Cache in TWDM PON ring","authors":"Bhargav Ram Rayapati, N. Rangaswamy, A. V. Bhaskar","doi":"10.1109/AISP53593.2022.9760612","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760612","url":null,"abstract":"This work discusses the availability of cache memories for VoD service in Time and Wavelength Division Multiplexed Passive Optical Network (TWDM PON) ring topology. In a unidirectional ring topology with TWDM PON, the wavelength channels are enabled in an anti-cyclic manner through intermediate devices such as Remote Node (RN) and splitter as per traffic requirements. The provision of cache storage at subsystems of ring topology, namely, Optical Line Terminal (OLT), RN, and Optical Network Unit (ONU) enables the users to access the VoD service within reach rather than from a typical video server. Thus, this mechanism reduces the delay as well as power requirements. However, in this paper the analytical emphasis on the ring topology is confined only to power requirements through two situational cases. In the first case, the cache storage at OLT and ONU is only availed. While in the second case, the cache available at RN was also made to use. It is observed that the power consumption in the second case is lesser than in the first case. Due to more decentralization of cache availability in the second case, relatively 70 % more power savings are observed.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"3 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73175757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-12DOI: 10.1109/AISP53593.2022.9760526
Uday A. Patil, A. Kakade, Sajeed S. Mulla
In this paper the microstrip annular slot antenna (MASA) loaded with surrounding metamaterial having permittivity and permeability less than zero is investigated with analytical and numerical methods. A solution to the source surrounded by an infinite inhomogeneous medium is obtained. Then the same technique is used to formulate the field equations of the microstrip annular slot antenna (MASA) surrounded by a homogeneous metamaterial. The power gain of the microstrip annular slot antenna (MASA) surrounded by the metamaterial medium relative to the dielectric medium is analyzed and calculated. The analysis of the reactance ratio and the reactive power of the MASA shows that the surrounding metamaterial acts as a natural impedance matching network for an antenna. The equivalent circuit model for the surrounding inhomogeneous medium with metamaterial has been proposed. It justifies the approval of the metamaterial as a natural impedance matching network. The radiated power of the MASA surrounded by metamaterial (with media constant $varepsilon_{2}=-varepsilon_{0}, mu_{2}=-mu_{0}$) has been increased by 73.66 times the radiated power of the MASA surrounded by a dielectric medium $(varepsilon_{2}=varepsilon_{0}, mu_{2}=mu_{0})$.
{"title":"Metamaterial Loaded Miniaturized Microstrip Annular Slot Antenna with Increased Gain","authors":"Uday A. Patil, A. Kakade, Sajeed S. Mulla","doi":"10.1109/AISP53593.2022.9760526","DOIUrl":"https://doi.org/10.1109/AISP53593.2022.9760526","url":null,"abstract":"In this paper the microstrip annular slot antenna (MASA) loaded with surrounding metamaterial having permittivity and permeability less than zero is investigated with analytical and numerical methods. A solution to the source surrounded by an infinite inhomogeneous medium is obtained. Then the same technique is used to formulate the field equations of the microstrip annular slot antenna (MASA) surrounded by a homogeneous metamaterial. The power gain of the microstrip annular slot antenna (MASA) surrounded by the metamaterial medium relative to the dielectric medium is analyzed and calculated. The analysis of the reactance ratio and the reactive power of the MASA shows that the surrounding metamaterial acts as a natural impedance matching network for an antenna. The equivalent circuit model for the surrounding inhomogeneous medium with metamaterial has been proposed. It justifies the approval of the metamaterial as a natural impedance matching network. The radiated power of the MASA surrounded by metamaterial (with media constant $varepsilon_{2}=-varepsilon_{0}, mu_{2}=-mu_{0}$) has been increased by 73.66 times the radiated power of the MASA surrounded by a dielectric medium $(varepsilon_{2}=varepsilon_{0}, mu_{2}=mu_{0})$.","PeriodicalId":6793,"journal":{"name":"2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP)","volume":"69 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2022-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73601914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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