Pub Date : 2023-04-17DOI: 10.3389/felec.2023.1129675
Yuyi Liu, B. Gao, Peng Yao, Qi Liu, Qingtian Zhang, Dong Wu, Jianshi Tang, H. Qian, Huaqiang Wu
Analog resistive random-access memory (RRAM)-based computation-in-memory (CIM) technology is promising for constructing artificial intelligence (AI) with high energy efficiency and excellent scalability. However, the large overhead of analog-to-digital converters (ADCs) is a key limitation. In this work, we propose a novel LINKAGE architecture that eliminates PE-level ADCs and leverages an analog data transfer module to implement inter-array data processing. A blockwise dataflow is further proposed to accelerate convolutional neural networks (CNNs) to speed up compute-intensive layers and solve the unbalanced pipeline problem. To obtain accurate and reliable benchmark results, key component modules, such as straightforward link (SFL) modules and Tile-level ADCs, are designed in standard 28 nm CMOS technology. The evaluation shows that LINKAGE outperforms the conventional ADC/DAC-based architecture with a 2.07×∼11.22× improvement in throughput, 2.45×∼7.00× in energy efficiency, and 22%–51% reduction in the area overhead while maintaining accuracy. Our LINKAGE architecture can achieve 22.9∼24.4 TOPS/W energy efficiency (4b-IN/4b-W) and 1.82 ∼4.53 TOPS throughput with the blockwise method. This work demonstrates a new method for significantly improving the energy efficiency of CIM chips, which can be applied to general CNNs/FCNNs.
{"title":"Straightforward data transfer in a blockwise dataflow for an analog RRAM-based CIM system","authors":"Yuyi Liu, B. Gao, Peng Yao, Qi Liu, Qingtian Zhang, Dong Wu, Jianshi Tang, H. Qian, Huaqiang Wu","doi":"10.3389/felec.2023.1129675","DOIUrl":"https://doi.org/10.3389/felec.2023.1129675","url":null,"abstract":"Analog resistive random-access memory (RRAM)-based computation-in-memory (CIM) technology is promising for constructing artificial intelligence (AI) with high energy efficiency and excellent scalability. However, the large overhead of analog-to-digital converters (ADCs) is a key limitation. In this work, we propose a novel LINKAGE architecture that eliminates PE-level ADCs and leverages an analog data transfer module to implement inter-array data processing. A blockwise dataflow is further proposed to accelerate convolutional neural networks (CNNs) to speed up compute-intensive layers and solve the unbalanced pipeline problem. To obtain accurate and reliable benchmark results, key component modules, such as straightforward link (SFL) modules and Tile-level ADCs, are designed in standard 28 nm CMOS technology. The evaluation shows that LINKAGE outperforms the conventional ADC/DAC-based architecture with a 2.07×∼11.22× improvement in throughput, 2.45×∼7.00× in energy efficiency, and 22%–51% reduction in the area overhead while maintaining accuracy. Our LINKAGE architecture can achieve 22.9∼24.4 TOPS/W energy efficiency (4b-IN/4b-W) and 1.82 ∼4.53 TOPS throughput with the blockwise method. This work demonstrates a new method for significantly improving the energy efficiency of CIM chips, which can be applied to general CNNs/FCNNs.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49576812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-17DOI: 10.3389/felec.2023.968549
Chenchen Li, Kaiyuan Wang, Y. Mao
This paper presents a general circuit and control design method for wireless power transfer (WPT) systems in DC microgrids to achieve optimal power transfer efficiency, while maintain accurate output voltage regulation. An auxiliary inductor is added at the transmitter resonator to form a current sink to ensure zero voltage switching (ZVS) of the primary-side full-bridge inverter with even extreme-light load conditions. Besides, an adaptive proportional-integral (PI) controller is adopted to track the output voltage references by regulating the phase shift angle of the phase shift control for the full-bridge inverter. The coefficients of the adaptive proportional-integral controller are determined by the inductor of the auxiliary inductor. Both simulation and experimental results have validated the effectiveness of the proposed circuit and control design in achieving optimal efficiency and output voltage regulation for wireless power transfer systems in DC microgrids with source and load variations.
{"title":"Design of a wireless charging system in DC microgrids with accurate output regulation and optimal efficiency","authors":"Chenchen Li, Kaiyuan Wang, Y. Mao","doi":"10.3389/felec.2023.968549","DOIUrl":"https://doi.org/10.3389/felec.2023.968549","url":null,"abstract":"This paper presents a general circuit and control design method for wireless power transfer (WPT) systems in DC microgrids to achieve optimal power transfer efficiency, while maintain accurate output voltage regulation. An auxiliary inductor is added at the transmitter resonator to form a current sink to ensure zero voltage switching (ZVS) of the primary-side full-bridge inverter with even extreme-light load conditions. Besides, an adaptive proportional-integral (PI) controller is adopted to track the output voltage references by regulating the phase shift angle of the phase shift control for the full-bridge inverter. The coefficients of the adaptive proportional-integral controller are determined by the inductor of the auxiliary inductor. Both simulation and experimental results have validated the effectiveness of the proposed circuit and control design in achieving optimal efficiency and output voltage regulation for wireless power transfer systems in DC microgrids with source and load variations.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47750702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-23DOI: 10.3389/felec.2023.1110039
Xianglei Ye, Zhenya Ji, Jinxing Xu, Xiaofeng Liu
The integrated energy system is an effective way to achieve carbon neutrality. To further exploit the carbon reduction potentials of IESs, an optimal dispatch strategy that considers integrated demand response and stepped carbon trading is proposed. First, an integrated demand response (IDR) pricing approach is proposed based on the characteristics of different load types. Classify multi-energy loads into curtailable and substitutable loads, and incentivize both loads through a price elasticity matrix and low-price energy in the same period. Then, to better incentivize IESs to reduce carbon emissions, a stepped pricing mechanism was introduced in the carbon price. Finally, an optimal dispatch model is developed with an objective function that minimizes the sum of energy purchase cost, carbon trading cost, and operation and maintenance (O&M) cost. Considering the high-dimensional and non-linear characteristics of the model, an improved differential evolution (DE) algorithm is introduced in this paper. In addition, this paper also analyzes the effects of the stepped carbon trading parameters on the optimal dispatching results of the system in terms of carbon trading base price, carbon emission interval length, and carbon price growth rate. Compared to the case of adopting a single IDR model or a single stepped carbon trading, carbon emissions from the IESs decreased by 6.28% and 3.24%, respectively, while total operating costs decreased by 1.24% and 0.92%, The results show that the model proposed in this paper has good environmental and economic benefits, and the reasonable setting of stepped carbon trading parameters can effectively promote the low-carbon development of IESs.
{"title":"Optimal dispatch of integrated energy systems considering integrated demand response and stepped carbon trading","authors":"Xianglei Ye, Zhenya Ji, Jinxing Xu, Xiaofeng Liu","doi":"10.3389/felec.2023.1110039","DOIUrl":"https://doi.org/10.3389/felec.2023.1110039","url":null,"abstract":"The integrated energy system is an effective way to achieve carbon neutrality. To further exploit the carbon reduction potentials of IESs, an optimal dispatch strategy that considers integrated demand response and stepped carbon trading is proposed. First, an integrated demand response (IDR) pricing approach is proposed based on the characteristics of different load types. Classify multi-energy loads into curtailable and substitutable loads, and incentivize both loads through a price elasticity matrix and low-price energy in the same period. Then, to better incentivize IESs to reduce carbon emissions, a stepped pricing mechanism was introduced in the carbon price. Finally, an optimal dispatch model is developed with an objective function that minimizes the sum of energy purchase cost, carbon trading cost, and operation and maintenance (O&M) cost. Considering the high-dimensional and non-linear characteristics of the model, an improved differential evolution (DE) algorithm is introduced in this paper. In addition, this paper also analyzes the effects of the stepped carbon trading parameters on the optimal dispatching results of the system in terms of carbon trading base price, carbon emission interval length, and carbon price growth rate. Compared to the case of adopting a single IDR model or a single stepped carbon trading, carbon emissions from the IESs decreased by 6.28% and 3.24%, respectively, while total operating costs decreased by 1.24% and 0.92%, The results show that the model proposed in this paper has good environmental and economic benefits, and the reasonable setting of stepped carbon trading parameters can effectively promote the low-carbon development of IESs.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47715360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-26DOI: 10.3389/felec.2023.1034082
W. Wang, Mingrong Duan, Zhenwei Zeng, Hua Liu, Zhenya Ji
This paper presents the optimized structure of the multi-relay coils insulator of WPT system. With the rapid development of the smart grid, on-line monitoring devices in the transmission tower have been widely used. However, the power supply problem has become an important bottleneck in the development of transmission tower intelligent sensing technology. Hence, the multi-relay coils wireless power transfer technology has been proposed to supply for the tower monitoring equipment in this paper. Compared with traditional multi-relay coils, the effects of the number, arrangement position and turns of relay coils on the performance of WPT system are further explored. The simulation results show that the operation performance of WPT can be significantly improved by optimizing the coil arrangement position and turns. Moreover, there are multiple configuration schemes that the design indexes of the system could be achieved. The experiment results show that in the 110 kV high-voltage transmission with the insulator length of 1.015 m, the transmitting power and efficiency of the WPT system could be increased to 1.81 W and 60.11% respectively by parameters optimization, which ensures the continuous and stable work of the monitoring equipment.
{"title":"Research on optimal coil configuration scheme of insulator relay WPT system","authors":"W. Wang, Mingrong Duan, Zhenwei Zeng, Hua Liu, Zhenya Ji","doi":"10.3389/felec.2023.1034082","DOIUrl":"https://doi.org/10.3389/felec.2023.1034082","url":null,"abstract":"This paper presents the optimized structure of the multi-relay coils insulator of WPT system. With the rapid development of the smart grid, on-line monitoring devices in the transmission tower have been widely used. However, the power supply problem has become an important bottleneck in the development of transmission tower intelligent sensing technology. Hence, the multi-relay coils wireless power transfer technology has been proposed to supply for the tower monitoring equipment in this paper. Compared with traditional multi-relay coils, the effects of the number, arrangement position and turns of relay coils on the performance of WPT system are further explored. The simulation results show that the operation performance of WPT can be significantly improved by optimizing the coil arrangement position and turns. Moreover, there are multiple configuration schemes that the design indexes of the system could be achieved. The experiment results show that in the 110 kV high-voltage transmission with the insulator length of 1.015 m, the transmitting power and efficiency of the WPT system could be increased to 1.81 W and 60.11% respectively by parameters optimization, which ensures the continuous and stable work of the monitoring equipment.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":"4 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45145957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-12DOI: 10.3389/felec.2022.1091369
Mengxin Zheng, Lei Ju, Lei Jiang
Introduction: Privacy concerns arise whenever sensitive data is outsourced to untrusted Machine Learning as a Service (MLaaS) platforms. Fully Homomorphic Encryption (FHE) emerges one of the most promising solutions to implementing privacy-preserving MLaaS. But prior FHE-based MLaaS faces challenges from both software and hardware perspectives. First, FHE can be implemented by various schemes including BGV, BFV, and CKKS, which are good at different FHE operations, e.g., additions, multiplications, and rotations. Different neural network architectures require different numbers of FHE operations, thereby preferring different FHE schemes. However, state-of-the-art MLaaS just naïvely chooses one FHE scheme to build FHE-based neural networks without considering other FHE schemes. Second, state-of-the-art MLaaS uses power-hungry hardware accelerators to process FHE-based inferences. Typically, prior high-performance FHE accelerators consume > 160 Watt, due to their huge capacity (e.g., 512 MB) on-chip SRAM scratchpad memories. Methods: In this paper, we propose a software and hardware co-designed FHE-based MLaaS framework, CoFHE. From the software perspective, we propose an FHE compiler to select the best FHE scheme for a network architecture. We also build a low-power and high-density NAND-SPIN and SRAM hybrid scratchpad memory system for FHE hardware accelerators. Results: On average, under the same security and accuracy constraints, on average, CoFHE accelerates various FHE-based inferences by 18%, and reduces the energy consumption of various FHE-based inferences by 26%. Discussion: CoFHE greatly improves the latency and energy efficiency of FHE-based MLaaS.
{"title":"CoFHE: Software and hardware Co-design for FHE-based machine learning as a service","authors":"Mengxin Zheng, Lei Ju, Lei Jiang","doi":"10.3389/felec.2022.1091369","DOIUrl":"https://doi.org/10.3389/felec.2022.1091369","url":null,"abstract":"Introduction: Privacy concerns arise whenever sensitive data is outsourced to untrusted Machine Learning as a Service (MLaaS) platforms. Fully Homomorphic Encryption (FHE) emerges one of the most promising solutions to implementing privacy-preserving MLaaS. But prior FHE-based MLaaS faces challenges from both software and hardware perspectives. First, FHE can be implemented by various schemes including BGV, BFV, and CKKS, which are good at different FHE operations, e.g., additions, multiplications, and rotations. Different neural network architectures require different numbers of FHE operations, thereby preferring different FHE schemes. However, state-of-the-art MLaaS just naïvely chooses one FHE scheme to build FHE-based neural networks without considering other FHE schemes. Second, state-of-the-art MLaaS uses power-hungry hardware accelerators to process FHE-based inferences. Typically, prior high-performance FHE accelerators consume > 160 Watt, due to their huge capacity (e.g., 512 MB) on-chip SRAM scratchpad memories. Methods: In this paper, we propose a software and hardware co-designed FHE-based MLaaS framework, CoFHE. From the software perspective, we propose an FHE compiler to select the best FHE scheme for a network architecture. We also build a low-power and high-density NAND-SPIN and SRAM hybrid scratchpad memory system for FHE hardware accelerators. Results: On average, under the same security and accuracy constraints, on average, CoFHE accelerates various FHE-based inferences by 18%, and reduces the energy consumption of various FHE-based inferences by 26%. Discussion: CoFHE greatly improves the latency and energy efficiency of FHE-based MLaaS.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":"3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44208279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-06DOI: 10.3389/felec.2022.1060197
G. Maroli, S. Boyeras, H. Giannetta, S. Pazos, J. Gak, A. Oliva, M. Volpe, P. Julián, F. Palumbo
Understanding the sintering process of conductive inks is a fundamental step in the development of sensors. The intrinsic properties (such as thermal conductivity, resistivity, thermal coefficient, among others) of the printed devices do not correspond to those of the bulk materials. In the field of biosensors porosity plays a predominant role, since it defines the difference between the geometric area of the working electrode and its electrochemical surface area. The analysis reported so far in the literature on the sintering of inks are based on their DC characterization. In this work, the shape and distribution of the nanoparticles that make up the silver ink have been studied employing a transmission electron microscopy. Images of the printed traces have been obtained through a scanning electron microscope at different sintering times, allowing to observe how the material decreases its porosity over time. These structural changes were supported through electrical measurements of the change in the trace impedance as a function of drying time. The resistivity and thermal coefficient of the printed tracks were analyzed and compared with the values of bulk silver. Finally, this work proposes an analytical circuit model of the drying behavior of the ink based on AC characterization at different frequencies. The characterization considers an initial time when the spheric nanoparticles are still surrounded by the capping agent until the conductive trace is obtained. This model can estimate the characteristics that the printed devices would have, whether they are used as biosensors (porous material) or as interconnections (compact material) in printed electronics.
{"title":"Analytic circuit model for thermal drying behavior of electronic inks","authors":"G. Maroli, S. Boyeras, H. Giannetta, S. Pazos, J. Gak, A. Oliva, M. Volpe, P. Julián, F. Palumbo","doi":"10.3389/felec.2022.1060197","DOIUrl":"https://doi.org/10.3389/felec.2022.1060197","url":null,"abstract":"Understanding the sintering process of conductive inks is a fundamental step in the development of sensors. The intrinsic properties (such as thermal conductivity, resistivity, thermal coefficient, among others) of the printed devices do not correspond to those of the bulk materials. In the field of biosensors porosity plays a predominant role, since it defines the difference between the geometric area of the working electrode and its electrochemical surface area. The analysis reported so far in the literature on the sintering of inks are based on their DC characterization. In this work, the shape and distribution of the nanoparticles that make up the silver ink have been studied employing a transmission electron microscopy. Images of the printed traces have been obtained through a scanning electron microscope at different sintering times, allowing to observe how the material decreases its porosity over time. These structural changes were supported through electrical measurements of the change in the trace impedance as a function of drying time. The resistivity and thermal coefficient of the printed tracks were analyzed and compared with the values of bulk silver. Finally, this work proposes an analytical circuit model of the drying behavior of the ink based on AC characterization at different frequencies. The characterization considers an initial time when the spheric nanoparticles are still surrounded by the capping agent until the conductive trace is obtained. This model can estimate the characteristics that the printed devices would have, whether they are used as biosensors (porous material) or as interconnections (compact material) in printed electronics.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45452639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-21DOI: 10.3389/felec.2022.1091343
K. Toprasertpong, M. Takenaka, Shinichi Takagi
Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.
{"title":"Breakdown-limited endurance in HZO FeFETs: Mechanism and improvement under bipolar stress","authors":"K. Toprasertpong, M. Takenaka, Shinichi Takagi","doi":"10.3389/felec.2022.1091343","DOIUrl":"https://doi.org/10.3389/felec.2022.1091343","url":null,"abstract":"Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42785374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-20DOI: 10.3389/felec.2022.1032485
Fan Zhang, Li Yang, Jian Meng, J.-s. Seo, Yu Cao, Deliang Fan
Recently, ReRAM crossbar-based deep neural network (DNN) accelerator has been widely investigated. However, most prior works focus on single-task inference due to the high energy consumption of weight reprogramming and ReRAM cells’ low endurance issue. Adapting the ReRAM crossbar-based DNN accelerator for multiple tasks has not been fully explored. In this study, we propose XMA 2, a novel crossbar-aware learning method with a 2-tier masking technique to efficiently adapt a DNN backbone model deployed in the ReRAM crossbar for new task learning. During the XMA2-based multi-task adaption (MTA), the tier-1 ReRAM crossbar-based processing-element- (PE-) wise mask is first learned to identify the most critical PEs to be reprogrammed for essential new features of the new task. Subsequently, the tier-2 crossbar column-wise mask is applied within the rest of the weight-frozen PEs to learn a hardware-friendly and column-wise scaling factor for new task learning without modifying the weight values. With such crossbar-aware design innovations, we could implement the required masking operation in an existing crossbar-based convolution engine with minimal hardware/memory overhead to adapt to a new task. The extensive experimental results show that compared with other state-of-the-art multiple-task adaption methods, XMA2 achieves the highest accuracy on all popular multi-task learning datasets.
{"title":"XMA2: A crossbar-aware multi-task adaption framework via 2-tier masks","authors":"Fan Zhang, Li Yang, Jian Meng, J.-s. Seo, Yu Cao, Deliang Fan","doi":"10.3389/felec.2022.1032485","DOIUrl":"https://doi.org/10.3389/felec.2022.1032485","url":null,"abstract":"Recently, ReRAM crossbar-based deep neural network (DNN) accelerator has been widely investigated. However, most prior works focus on single-task inference due to the high energy consumption of weight reprogramming and ReRAM cells’ low endurance issue. Adapting the ReRAM crossbar-based DNN accelerator for multiple tasks has not been fully explored. In this study, we propose XMA 2, a novel crossbar-aware learning method with a 2-tier masking technique to efficiently adapt a DNN backbone model deployed in the ReRAM crossbar for new task learning. During the XMA2-based multi-task adaption (MTA), the tier-1 ReRAM crossbar-based processing-element- (PE-) wise mask is first learned to identify the most critical PEs to be reprogrammed for essential new features of the new task. Subsequently, the tier-2 crossbar column-wise mask is applied within the rest of the weight-frozen PEs to learn a hardware-friendly and column-wise scaling factor for new task learning without modifying the weight values. With such crossbar-aware design innovations, we could implement the required masking operation in an existing crossbar-based convolution engine with minimal hardware/memory overhead to adapt to a new task. The extensive experimental results show that compared with other state-of-the-art multiple-task adaption methods, XMA2 achieves the highest accuracy on all popular multi-task learning datasets.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42187198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bio-sensors connect the biological world with electronic devices, widely used in biomedical applications. The combination of microelectronic and medical technologies makes biomedical diagnosis more rapid, accurate, and efficient. In this article, the current-mode biosensing front-end integrated circuits (ICs) for nanopore-based DNA sequencing are reviewed and analyzed, aiming to present their operation theories, advantages, limitations, and performances including gain, bandwidth, noise, and power consumption. Because biological information and external interference are contained in extremely weak sensing current, usually at the pA or nA level, it is challenging to accurately detect and restore the desired signals. Based on the requirements of DNA sequencing, this paper shows three circuit topologies of biosensing front-end, namely, discrete-time, continuous-time, and current-to-frequency conversion types. This paper also makes an introduction to the current-mode sensor array for DNA sequencing. To better review and evaluate the research of the state-of-the-art, the most relevant published works are summarized and compared. The review and analysis would help the researchers be familiar with the requirements, constraints, and methods for current-mode biosensing front-end IC designs for nanopore-based DNA sequencing.
{"title":"A review and analysis of current-mode biosensing front-end ICs for nanopore-based DNA sequencing","authors":"Xu Liu, Qiumeng Fan, Zhijie Chen, Peiyuan Wan, Wei Mao, Hao Yu","doi":"10.3389/felec.2022.1071132","DOIUrl":"https://doi.org/10.3389/felec.2022.1071132","url":null,"abstract":"Bio-sensors connect the biological world with electronic devices, widely used in biomedical applications. The combination of microelectronic and medical technologies makes biomedical diagnosis more rapid, accurate, and efficient. In this article, the current-mode biosensing front-end integrated circuits (ICs) for nanopore-based DNA sequencing are reviewed and analyzed, aiming to present their operation theories, advantages, limitations, and performances including gain, bandwidth, noise, and power consumption. Because biological information and external interference are contained in extremely weak sensing current, usually at the pA or nA level, it is challenging to accurately detect and restore the desired signals. Based on the requirements of DNA sequencing, this paper shows three circuit topologies of biosensing front-end, namely, discrete-time, continuous-time, and current-to-frequency conversion types. This paper also makes an introduction to the current-mode sensor array for DNA sequencing. To better review and evaluate the research of the state-of-the-art, the most relevant published works are summarized and compared. The review and analysis would help the researchers be familiar with the requirements, constraints, and methods for current-mode biosensing front-end IC designs for nanopore-based DNA sequencing.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":"3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41325199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-06DOI: 10.3389/felec.2022.1017511
Zijie Chen, F. Gao, Junrui Liang
The rapid advance of the Internet of Things (IoT) has attracted growing interest in academia and industry toward pervasive sensing and everlasting IoT. As the IoT nodes exponentially increase, replacing and recharging their batteries proves an incredible waste of labor and resources. Kinetic energy harvesting (KEH), converting the wasted ambient kinetic energy into usable electrical energy, is an emerging research field where various working mechanisms and designs have been developed for improved performance. Leveraging the KEH technologies, many motion-powered sensors, where changes in the external environment are directly converted into corresponding self-generated electrical signals, are developed and prove promising for multiple self-sensing applications. Furthermore, some recent studies focus on utilizing the generated energy to power a whole IoT sensing system. These systems comprehensively consider the mechanical, electrical, and cyber parts, which lead a further step to truly self-sustaining and maintenance-free IoT systems. Here, this review starts with a brief introduction of KEH from the ambient environment and human motion. Furthermore, the cutting-edge KEH-based sensors are reviewed in detail. Subsequently, divided into two aspects, KEH-based battery-free sensing systems toward IoT are highlighted. Moreover, there are remarks in every chapter for summarizing. The concept of self-powered sensing is clarified, and advanced studies of KEH-based sensing in different fields are introduced. It is expected that this review can provide valuable references for future pervasive sensing and ubiquitous IoT.
{"title":"Kinetic energy harvesting based sensing and IoT systems: A review","authors":"Zijie Chen, F. Gao, Junrui Liang","doi":"10.3389/felec.2022.1017511","DOIUrl":"https://doi.org/10.3389/felec.2022.1017511","url":null,"abstract":"The rapid advance of the Internet of Things (IoT) has attracted growing interest in academia and industry toward pervasive sensing and everlasting IoT. As the IoT nodes exponentially increase, replacing and recharging their batteries proves an incredible waste of labor and resources. Kinetic energy harvesting (KEH), converting the wasted ambient kinetic energy into usable electrical energy, is an emerging research field where various working mechanisms and designs have been developed for improved performance. Leveraging the KEH technologies, many motion-powered sensors, where changes in the external environment are directly converted into corresponding self-generated electrical signals, are developed and prove promising for multiple self-sensing applications. Furthermore, some recent studies focus on utilizing the generated energy to power a whole IoT sensing system. These systems comprehensively consider the mechanical, electrical, and cyber parts, which lead a further step to truly self-sustaining and maintenance-free IoT systems. Here, this review starts with a brief introduction of KEH from the ambient environment and human motion. Furthermore, the cutting-edge KEH-based sensors are reviewed in detail. Subsequently, divided into two aspects, KEH-based battery-free sensing systems toward IoT are highlighted. Moreover, there are remarks in every chapter for summarizing. The concept of self-powered sensing is clarified, and advanced studies of KEH-based sensing in different fields are introduced. It is expected that this review can provide valuable references for future pervasive sensing and ubiquitous IoT.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47661166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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