Pub Date : 2022-09-26DOI: 10.3389/felec.2022.877629
Shengqi Yu, Thanasin Bunnam, S. Triamlumlerd, Manoch Pracha, F. Xia, R. Shafik, A. Yakovlev
Artificial intelligence applications implemented with neural networks require extensive arithmetic capabilities through multiply-accumulate (MAC) units. Traditional designs based on voltage-mode circuits feature complex logic chains for such purposes as carry processing. Additionally, as a separate memory block is used (e.g., in a von Neumann architecture), data movements incur on-chip communication bottlenecks. Furthermore, conventional multipliers have both operands encoded in the same physical quantity, which is either low cost to update or low cost to hold, but not both. This may be significant for low-energy edge operations. In this paper, we propose and present a mixed-signal multiply-accumulate unit design with in-memory computing to improve both latency and energy. This design is based on a single-bit multiplication cell consisting of a number of memristors and a single transistor switch (1TxM), arranged in a crossbar structure implementing the long-multiplication algorithm. The key innovation is that one of the operands is encoded in easy to update voltage and the other is encoded in non-volatile memristor conductance. This targets operations such as machine learning which feature asymmetric requirements for operand updates. Ohm’s Law and KCL take care of the multiplication in analog. When implemented as part of a NN, the MAC unit incorporates a current to digital stage to produce multi-bit voltage-mode output, in the same format as the input. The computation latency consists of memory writing and result encoding operations, with the Ohm’s Law and KCL operations contributing negligible delay. When compared with other memristor-based multipliers, the proposed work shows an order of magnitude of latency improvement in 4-bit implementations partly because of the Ohm’s Law and KCL time savings and partly because of the short writing operations for the frequently updated operand represented by voltages. In addition, the energy consumption per multiplication cycle of the proposed work is shown to improve by 74%–99% in corner cases. To investigate the usefulness of this MAC design in machine learning applications, its input/output relationships is characterized using multi-layer perceptrons to classify the well-known hand-writing digit dataset MNIST. This case study implements a quantization-aware training and includes the non-ideal effect of our MAC unit to allow the NN to learn and preserve its high accuracy. The simulation results show the NN using the proposed MAC unit yields an accuracy of 93%, which is only 1% lower than its baseline.
{"title":"Energy-efficient neural network design using memristive MAC unit","authors":"Shengqi Yu, Thanasin Bunnam, S. Triamlumlerd, Manoch Pracha, F. Xia, R. Shafik, A. Yakovlev","doi":"10.3389/felec.2022.877629","DOIUrl":"https://doi.org/10.3389/felec.2022.877629","url":null,"abstract":"Artificial intelligence applications implemented with neural networks require extensive arithmetic capabilities through multiply-accumulate (MAC) units. Traditional designs based on voltage-mode circuits feature complex logic chains for such purposes as carry processing. Additionally, as a separate memory block is used (e.g., in a von Neumann architecture), data movements incur on-chip communication bottlenecks. Furthermore, conventional multipliers have both operands encoded in the same physical quantity, which is either low cost to update or low cost to hold, but not both. This may be significant for low-energy edge operations. In this paper, we propose and present a mixed-signal multiply-accumulate unit design with in-memory computing to improve both latency and energy. This design is based on a single-bit multiplication cell consisting of a number of memristors and a single transistor switch (1TxM), arranged in a crossbar structure implementing the long-multiplication algorithm. The key innovation is that one of the operands is encoded in easy to update voltage and the other is encoded in non-volatile memristor conductance. This targets operations such as machine learning which feature asymmetric requirements for operand updates. Ohm’s Law and KCL take care of the multiplication in analog. When implemented as part of a NN, the MAC unit incorporates a current to digital stage to produce multi-bit voltage-mode output, in the same format as the input. The computation latency consists of memory writing and result encoding operations, with the Ohm’s Law and KCL operations contributing negligible delay. When compared with other memristor-based multipliers, the proposed work shows an order of magnitude of latency improvement in 4-bit implementations partly because of the Ohm’s Law and KCL time savings and partly because of the short writing operations for the frequently updated operand represented by voltages. In addition, the energy consumption per multiplication cycle of the proposed work is shown to improve by 74%–99% in corner cases. To investigate the usefulness of this MAC design in machine learning applications, its input/output relationships is characterized using multi-layer perceptrons to classify the well-known hand-writing digit dataset MNIST. This case study implements a quantization-aware training and includes the non-ideal effect of our MAC unit to allow the NN to learn and preserve its high accuracy. The simulation results show the NN using the proposed MAC unit yields an accuracy of 93%, which is only 1% lower than its baseline.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46302809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-06DOI: 10.3389/felec.2022.985681
Zhiqiang Zhai, Xiaosong Du, Yin Long, Heng Zheng
Biodegradable electronics have great potential to reduce the environmental footprint of electronic devices and to avoid secondary removal of implantable health monitors and therapeutic electronics. Benefiting from the intensive innovation on biodegradable nanomaterials, current transient electronics can realize full components’ degradability. However, design of materials with tissue-comparable flexibility, desired dielectric properties, suitable biocompatibility and programmable biodegradability will always be a challenge to explore the subtle trade-offs between these parameters. In this review, we firstly discuss the general chemical structure and degradation behavior of polymeric biodegradable materials that have been widely studied for various applications. Then, specific properties of different degradable polymer materials such as biocompatibility, biodegradability, and flexibility were compared and evaluated for real-life applications. Complex biodegradable electronics and related strategies with enhanced functionality aimed for different components including substrates, insulators, conductors and semiconductors in complex biodegradable electronics are further researched and discussed. Finally, typical applications of biodegradable electronics in sensing, therapeutic drug delivery, energy storage and integrated electronic systems are highlighted. This paper critically reviews the significant progress made in the field and highlights the future prospects.
{"title":"Biodegradable polymeric materials for flexible and degradable electronics","authors":"Zhiqiang Zhai, Xiaosong Du, Yin Long, Heng Zheng","doi":"10.3389/felec.2022.985681","DOIUrl":"https://doi.org/10.3389/felec.2022.985681","url":null,"abstract":"Biodegradable electronics have great potential to reduce the environmental footprint of electronic devices and to avoid secondary removal of implantable health monitors and therapeutic electronics. Benefiting from the intensive innovation on biodegradable nanomaterials, current transient electronics can realize full components’ degradability. However, design of materials with tissue-comparable flexibility, desired dielectric properties, suitable biocompatibility and programmable biodegradability will always be a challenge to explore the subtle trade-offs between these parameters. In this review, we firstly discuss the general chemical structure and degradation behavior of polymeric biodegradable materials that have been widely studied for various applications. Then, specific properties of different degradable polymer materials such as biocompatibility, biodegradability, and flexibility were compared and evaluated for real-life applications. Complex biodegradable electronics and related strategies with enhanced functionality aimed for different components including substrates, insulators, conductors and semiconductors in complex biodegradable electronics are further researched and discussed. Finally, typical applications of biodegradable electronics in sensing, therapeutic drug delivery, energy storage and integrated electronic systems are highlighted. This paper critically reviews the significant progress made in the field and highlights the future prospects.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45830416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.3389/felec.2022.904976
Tian‐Hua Liu, Yuxuan Zhuang
Improving the efficiency of home appliances is an important area of research these days, especially for global warming and climate change. To achieve this goal, in this paper, a new method to improve the maximum efficiency control of an interior permanent magnet synchronous motor (IPMSM) drive system, which includes an IPMSM and an inverter, is investigated. By suitably controlling the d-axis current, the IPMSM drive system can quickly reach its maximum efficiency. A steepest ascent method is used to obviously reduce the searching steps of the maximum efficiency tracking control for an IPMSM. According to experimental results, by using the traditional fixed step method, 14 steps are required to reach the maximum efficiency operating point. By using the proposed steepest ascent method, however, only 4 steps are needed to reach the maximum efficiency operating point. In addition, according to the experimental results, during the transient dynamics, the predictive controller obtains faster responses and 2% lower overshoot than the PI controller. Moreover, during adding external load, the predictive controller has only a 10 r/min speed drop and 0.1 s recover time; however, the PI controller has a 40 r/min speed drop and 0.3 s recover time. Experimental results can validate theoretical analysis. Several measured results show when compared to the fix-step searching method with a PI controller, the proposed methods provide quicker searching maximum efficiency ability, quicker and better dynamic transient responses, and lower speed drop when an external load is added.
{"title":"Maximum efficiency control and predictive-speed controller design for interior permanent magnet synchronous motor drive systems","authors":"Tian‐Hua Liu, Yuxuan Zhuang","doi":"10.3389/felec.2022.904976","DOIUrl":"https://doi.org/10.3389/felec.2022.904976","url":null,"abstract":"Improving the efficiency of home appliances is an important area of research these days, especially for global warming and climate change. To achieve this goal, in this paper, a new method to improve the maximum efficiency control of an interior permanent magnet synchronous motor (IPMSM) drive system, which includes an IPMSM and an inverter, is investigated. By suitably controlling the d-axis current, the IPMSM drive system can quickly reach its maximum efficiency. A steepest ascent method is used to obviously reduce the searching steps of the maximum efficiency tracking control for an IPMSM. According to experimental results, by using the traditional fixed step method, 14 steps are required to reach the maximum efficiency operating point. By using the proposed steepest ascent method, however, only 4 steps are needed to reach the maximum efficiency operating point. In addition, according to the experimental results, during the transient dynamics, the predictive controller obtains faster responses and 2% lower overshoot than the PI controller. Moreover, during adding external load, the predictive controller has only a 10 r/min speed drop and 0.1 s recover time; however, the PI controller has a 40 r/min speed drop and 0.3 s recover time. Experimental results can validate theoretical analysis. Several measured results show when compared to the fix-step searching method with a PI controller, the proposed methods provide quicker searching maximum efficiency ability, quicker and better dynamic transient responses, and lower speed drop when an external load is added.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47022211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-12DOI: 10.3389/felec.2022.954661
Han Bao, Yi-Fan Qin, Jia Chen, Ling Yang, Jiancong Li, Houji Zhou, Yi Li, Xiangshui Miao
Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.
{"title":"Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks","authors":"Han Bao, Yi-Fan Qin, Jia Chen, Ling Yang, Jiancong Li, Houji Zhou, Yi Li, Xiangshui Miao","doi":"10.3389/felec.2022.954661","DOIUrl":"https://doi.org/10.3389/felec.2022.954661","url":null,"abstract":"Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43918852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-11DOI: 10.3389/felec.2022.898273
Vaibhav Verma, M. Stan
The recent advances in Artificial Intelligence (AI) achieving “better-than-human” accuracy in a variety of tasks such as image classification and the game of Go have come at the cost of exponential increase in the size of artificial neural networks. This has lead to AI hardware solutions becoming severely memory-bound and scrambling to keep-up with the ever increasing “von Neumann bottleneck”. Processing-in-Memory (PiM) architectures offer an excellent solution to ease the von Neumann bottleneck by embedding compute capabilities inside the memory and reducing the data traffic between the memory and the processor. But PiM accelerators break the standard von Neumann programming model by fusing memory and compute operations together which impedes their integration in the standard computing stack. There is an urgent requirement for system-level solutions to take full advantage of PiM accelerators for end-to-end acceleration of AI applications. This article presents AI-PiM as a solution to bridge this research gap. AI-PiM proposes a hardware, ISA and software co-design methodology which allows integration of PiM accelerators in the RISC-V processor pipeline as functional execution units. AI-PiM also extends the RISC-V ISA with custom instructions which directly target the PiM functional units resulting in their tight integration with the processor. This tight integration is especially important for edge AI devices which need to process both AI and non-AI tasks on the same hardware due to area, power, size and cost constraints. AI-PiM ISA extensions expose the PiM hardware functionality to software programmers allowing efficient mapping of applications to the PiM hardware. AI-PiM adds support for custom ISA extensions to the complete software stack including compiler, assembler, linker, simulator and profiler to ensure programmability and evaluation with popular AI domain-specific languages and frameworks like TensorFlow, PyTorch, MXNet, Keras etc. AI-PiM improves the performance for vector-matrix multiplication (VMM) kernel by 17.63x and provides a mean speed-up of 2.74x for MLPerf Tiny benchmark compared to RV64IMC RISC-V baseline. AI-PiM also speeds-up MLPerf Tiny benchmark inference cycles by 2.45x (average) compared to state-of-the-art Arm Cortex-A72 processor.
{"title":"AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT","authors":"Vaibhav Verma, M. Stan","doi":"10.3389/felec.2022.898273","DOIUrl":"https://doi.org/10.3389/felec.2022.898273","url":null,"abstract":"The recent advances in Artificial Intelligence (AI) achieving “better-than-human” accuracy in a variety of tasks such as image classification and the game of Go have come at the cost of exponential increase in the size of artificial neural networks. This has lead to AI hardware solutions becoming severely memory-bound and scrambling to keep-up with the ever increasing “von Neumann bottleneck”. Processing-in-Memory (PiM) architectures offer an excellent solution to ease the von Neumann bottleneck by embedding compute capabilities inside the memory and reducing the data traffic between the memory and the processor. But PiM accelerators break the standard von Neumann programming model by fusing memory and compute operations together which impedes their integration in the standard computing stack. There is an urgent requirement for system-level solutions to take full advantage of PiM accelerators for end-to-end acceleration of AI applications. This article presents AI-PiM as a solution to bridge this research gap. AI-PiM proposes a hardware, ISA and software co-design methodology which allows integration of PiM accelerators in the RISC-V processor pipeline as functional execution units. AI-PiM also extends the RISC-V ISA with custom instructions which directly target the PiM functional units resulting in their tight integration with the processor. This tight integration is especially important for edge AI devices which need to process both AI and non-AI tasks on the same hardware due to area, power, size and cost constraints. AI-PiM ISA extensions expose the PiM hardware functionality to software programmers allowing efficient mapping of applications to the PiM hardware. AI-PiM adds support for custom ISA extensions to the complete software stack including compiler, assembler, linker, simulator and profiler to ensure programmability and evaluation with popular AI domain-specific languages and frameworks like TensorFlow, PyTorch, MXNet, Keras etc. AI-PiM improves the performance for vector-matrix multiplication (VMM) kernel by 17.63x and provides a mean speed-up of 2.74x for MLPerf Tiny benchmark compared to RV64IMC RISC-V baseline. AI-PiM also speeds-up MLPerf Tiny benchmark inference cycles by 2.45x (average) compared to state-of-the-art Arm Cortex-A72 processor.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42223434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-22DOI: 10.3389/felec.2022.836669
P. Pérez, Juan A. Serrano-Viseas, Santiago Fernández-Scagliusi, Daniel Martín-Fernández, G. Huertas, A. Yúfera
Biological Impedance is a physical property related to the state and inherent evolution of biological samples. Among the existing impedance measurement methods, Oscillation-Based (OB) tests are a simple and smart solution to indirectly measure impedance correlated with the amplitude and frequency of the generated oscillation which are proportional to the sample under test. An OB test requires tuning of the system blocks to specifications derived from every measurement problem. The OB setup must be done to obtain the optimum measurement sensitivity for the specific constraints imposed by the system under test, electronic interfaces, and electrodes employed for test. This work proposes the extension of OB measurement systems to spectroscopy test, enabling a completely new range of applications for this technology without the restrictions imposed by setting a fixed frequency on the electrical oscillator. Some examples will be presented to the measurement of cell cultures samples, considering the corresponding circuit interfaces and electric models for the electrode-cell system. The proposed analysis method allows the selection of the best oscillator elements for optimum sensitivity range in amplitude and frequency oscillation values, when a specific cell culture is monitored for the OB system.
{"title":"Oscillation-Based Spectroscopy for Cell-Culture Monitorization","authors":"P. Pérez, Juan A. Serrano-Viseas, Santiago Fernández-Scagliusi, Daniel Martín-Fernández, G. Huertas, A. Yúfera","doi":"10.3389/felec.2022.836669","DOIUrl":"https://doi.org/10.3389/felec.2022.836669","url":null,"abstract":"Biological Impedance is a physical property related to the state and inherent evolution of biological samples. Among the existing impedance measurement methods, Oscillation-Based (OB) tests are a simple and smart solution to indirectly measure impedance correlated with the amplitude and frequency of the generated oscillation which are proportional to the sample under test. An OB test requires tuning of the system blocks to specifications derived from every measurement problem. The OB setup must be done to obtain the optimum measurement sensitivity for the specific constraints imposed by the system under test, electronic interfaces, and electrodes employed for test. This work proposes the extension of OB measurement systems to spectroscopy test, enabling a completely new range of applications for this technology without the restrictions imposed by setting a fixed frequency on the electrical oscillator. Some examples will be presented to the measurement of cell cultures samples, considering the corresponding circuit interfaces and electric models for the electrode-cell system. The proposed analysis method allows the selection of the best oscillator elements for optimum sensitivity range in amplitude and frequency oscillation values, when a specific cell culture is monitored for the OB system.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47190035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-13DOI: 10.3389/felec.2022.926865
Yajie Jiang, Yun Yang
In this work, the loss (including wire loss and converter loss) of island three-phase AC microgrid is modeled as a quadratic function of the current distribution coefficient, that is, a concave function with equality and inequality constraints. On the basis of the concave optimization principle, the optimal current distribution coefficient of the distributed energy unit (DEU) is calculated online by the double ascent optimization method (DAOM) to minimize the distribution loss. It is proven that the concave function with multi-variables can be optimized by the DAOM. Using the average reactive power distribution scheme, the optimal active power distribution coefficient with the minimum distribution loss of the AC microgrid can be obtained in real time. In addition, given the high R/X ratio in the short-distance AC microgrid, the active power–frequency (P-ω) droop control and reactive power–voltage amplitude (Q-E) droop control are not suitable for power distribution among DEUs. Thus, an advanced strategy comprising active power–voltage amplitude (P-E) droop control and reactive power-frequency (Q-ω) droop control is proposed to dispatch the output active powers and reactive powers of DEUs. Simulation examples are provided to verify the convexity of the proposed model and the effectiveness of the control strategy.
{"title":"Dual Ascent Algorithm-Based Improved Droop Control for Efficient Operation of AC Microgrid","authors":"Yajie Jiang, Yun Yang","doi":"10.3389/felec.2022.926865","DOIUrl":"https://doi.org/10.3389/felec.2022.926865","url":null,"abstract":"In this work, the loss (including wire loss and converter loss) of island three-phase AC microgrid is modeled as a quadratic function of the current distribution coefficient, that is, a concave function with equality and inequality constraints. On the basis of the concave optimization principle, the optimal current distribution coefficient of the distributed energy unit (DEU) is calculated online by the double ascent optimization method (DAOM) to minimize the distribution loss. It is proven that the concave function with multi-variables can be optimized by the DAOM. Using the average reactive power distribution scheme, the optimal active power distribution coefficient with the minimum distribution loss of the AC microgrid can be obtained in real time. In addition, given the high R/X ratio in the short-distance AC microgrid, the active power–frequency (P-ω) droop control and reactive power–voltage amplitude (Q-E) droop control are not suitable for power distribution among DEUs. Thus, an advanced strategy comprising active power–voltage amplitude (P-E) droop control and reactive power-frequency (Q-ω) droop control is proposed to dispatch the output active powers and reactive powers of DEUs. Simulation examples are provided to verify the convexity of the proposed model and the effectiveness of the control strategy.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48495192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-01DOI: 10.3389/felec.2022.906689
Mohamed Abdelazez, S. Rajan, A. Chan
The objective of this paper is to develop an optimized system to detect Atrial Fibrillation (AF) in compressively sensed electrocardiogram (ECG) for long-term remote patient monitoring. A three-stage system was developed to 1) reject ECG of poor signal quality, 2) detect AF in compressively sensed ECG, and 3) detect AF in selectively reconstructed ECG. The Long-Term AF Database (LTAFDB), sampled at 128 Hz using a 12-bit ADC with a range of 20 mV, was used to validate the system. The LTAFDB had 83,315 normal and 82,435 AF rhythm 30 s ECG segments. Clean ECG from the LTAFDB was artificially contaminated with motion artifact to achieve −12 to 12 dB Signal-to-Noise Ratio (SNR) in steps of 3 dB. The contaminated ECG was compressively sensed at 50% and 75% compression ratio (CR). The system was evaluated using average precision (AP), the area under the curve (AUC) of the receiver operator characteristic curve, and the F1 score. The system was optimized to maximize the AP and minimize ECG rejection and reconstruction ratios. The optimized system for 50% CR had 0.72 AP, 0.63 AUC, and 0.58 F1 score, 0.38 rejection ratio, and 0.38 reconstruction ratio. The optimized system for 75% CR had 0.72 AP, 0.63 AUC, and 0.59 F1 score, 0.40 rejection ratio, and 0.35 reconstruction ratio. Challenges for long-term AF monitoring are the short battery life of monitors and the high false alarm rate due to artifacts. The proposed system improves the short battery life through compressive sensing while reducing false alarms (high AP) and ECG reconstruction (low reconstruction ratio).
{"title":"Detection of Atrial Fibrillation in Compressively Sensed Electrocardiogram for Remote Monitoring","authors":"Mohamed Abdelazez, S. Rajan, A. Chan","doi":"10.3389/felec.2022.906689","DOIUrl":"https://doi.org/10.3389/felec.2022.906689","url":null,"abstract":"The objective of this paper is to develop an optimized system to detect Atrial Fibrillation (AF) in compressively sensed electrocardiogram (ECG) for long-term remote patient monitoring. A three-stage system was developed to 1) reject ECG of poor signal quality, 2) detect AF in compressively sensed ECG, and 3) detect AF in selectively reconstructed ECG. The Long-Term AF Database (LTAFDB), sampled at 128 Hz using a 12-bit ADC with a range of 20 mV, was used to validate the system. The LTAFDB had 83,315 normal and 82,435 AF rhythm 30 s ECG segments. Clean ECG from the LTAFDB was artificially contaminated with motion artifact to achieve −12 to 12 dB Signal-to-Noise Ratio (SNR) in steps of 3 dB. The contaminated ECG was compressively sensed at 50% and 75% compression ratio (CR). The system was evaluated using average precision (AP), the area under the curve (AUC) of the receiver operator characteristic curve, and the F1 score. The system was optimized to maximize the AP and minimize ECG rejection and reconstruction ratios. The optimized system for 50% CR had 0.72 AP, 0.63 AUC, and 0.58 F1 score, 0.38 rejection ratio, and 0.38 reconstruction ratio. The optimized system for 75% CR had 0.72 AP, 0.63 AUC, and 0.59 F1 score, 0.40 rejection ratio, and 0.35 reconstruction ratio. Challenges for long-term AF monitoring are the short battery life of monitors and the high false alarm rate due to artifacts. The proposed system improves the short battery life through compressive sensing while reducing false alarms (high AP) and ECG reconstruction (low reconstruction ratio).","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44221682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-27DOI: 10.3389/felec.2022.910968
Jaro De Roose, M. Andraud, M. Verhelst
The constant miniaturization of IoT sensor nodes requires a continuous reduction in battery sizes, leading to more stringent needs in terms of low-power operation. Over the past decades, an extremely large variety of techniques have been introduced to enable such reductions in power consumption. Many involve some form of offline reconfigurability (OfC), i.e., the ability to configure the node before deployment, or online adaptivity (OnA), i.e., the ability to also reconfigure the node during run time. Yet, the inherent design trade-offs usually lead to ad hoc OnA and OfC, which prevent assessing the varying benefits and costs each approach implies before investing in implementation on a specific node. To solve this issue, in this work, we propose a generic predictive assessment methodology that enables us to evaluate OfC and OnA globally, prior to any design. Practically, the methodology is based on optimization mathematics, to quickly and efficiently evaluate the potential benefits and costs from OnA relative to OfC. This generic methodology can, thus, determine which type of solution will consume the least amount of power, given a specific application scenario, before implementation. We applied the methodology to three adaptive IoT system studies, to demonstrate the ability of the introduced methodology, bring insights into the adaptivity mechanics, and quickly optimize the OfC–OnA adaptivity, even under scenarios with many adaptivity variables.
{"title":"A Procedural Method to Predictively Assess Power-Quality Trade-Offs of Circuit-Level Adaptivity in IoT Systems","authors":"Jaro De Roose, M. Andraud, M. Verhelst","doi":"10.3389/felec.2022.910968","DOIUrl":"https://doi.org/10.3389/felec.2022.910968","url":null,"abstract":"The constant miniaturization of IoT sensor nodes requires a continuous reduction in battery sizes, leading to more stringent needs in terms of low-power operation. Over the past decades, an extremely large variety of techniques have been introduced to enable such reductions in power consumption. Many involve some form of offline reconfigurability (OfC), i.e., the ability to configure the node before deployment, or online adaptivity (OnA), i.e., the ability to also reconfigure the node during run time. Yet, the inherent design trade-offs usually lead to ad hoc OnA and OfC, which prevent assessing the varying benefits and costs each approach implies before investing in implementation on a specific node. To solve this issue, in this work, we propose a generic predictive assessment methodology that enables us to evaluate OfC and OnA globally, prior to any design. Practically, the methodology is based on optimization mathematics, to quickly and efficiently evaluate the potential benefits and costs from OnA relative to OfC. This generic methodology can, thus, determine which type of solution will consume the least amount of power, given a specific application scenario, before implementation. We applied the methodology to three adaptive IoT system studies, to demonstrate the ability of the introduced methodology, bring insights into the adaptivity mechanics, and quickly optimize the OfC–OnA adaptivity, even under scenarios with many adaptivity variables.","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47195458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-15DOI: 10.3389/felec.2022.935289
Y. Wu, Shiwei Wang, B. Shen, Hubin Zhao, Haichang Lu, Shuo Gao
Department of Electronic and Electrical Engineering, University College London, London, United Kingdom, School of Engineering, The University of Edinburgh, Edinburgh, United Kingdom, Electrical Engineering Division, Department of Engineering, University of Cambridge, Cambridge, United Kingdom, HUB of Intelligent Neuro-engineering, CREATe, Faculty of Medical Sciences, University College London, London, United Kingdom, School of Integrated Circuit Science and Engineering Beihang University, Beijing, China, School of Instrumentation and Optoelectronic Engineering, Beihang University, Beijing, China
{"title":"Editorial: Wearable and Implantable Electronics for the next Generation of Human-Machine Interactive Devices","authors":"Y. Wu, Shiwei Wang, B. Shen, Hubin Zhao, Haichang Lu, Shuo Gao","doi":"10.3389/felec.2022.935289","DOIUrl":"https://doi.org/10.3389/felec.2022.935289","url":null,"abstract":"Department of Electronic and Electrical Engineering, University College London, London, United Kingdom, School of Engineering, The University of Edinburgh, Edinburgh, United Kingdom, Electrical Engineering Division, Department of Engineering, University of Cambridge, Cambridge, United Kingdom, HUB of Intelligent Neuro-engineering, CREATe, Faculty of Medical Sciences, University College London, London, United Kingdom, School of Integrated Circuit Science and Engineering Beihang University, Beijing, China, School of Instrumentation and Optoelectronic Engineering, Beihang University, Beijing, China","PeriodicalId":73081,"journal":{"name":"Frontiers in electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42434087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：