Pub Date : 2025-02-26DOI: 10.1109/OJCAS.2025.3545904
Konstantinos Metaxas;Vassilis Alimisis;Costas Oustoglou;Yannis Kominis;Paul P. Sotiriadis
A comprehensive nonlinear analysis of autonomous and periodically forced fully-differential, negative-resistor LC oscillators is presented. Through nonlinear transformations in the state space, it is shown that oscillators within this class exhibit qualitatively similar dynamical behavior in terms of their limit cycles and bifurcation curves, at least within an open region containing the origin. The case of autonomous, complementary BJT oscillators is used to validate the qualitative analysis and demonstrate a general approach of how to numerically extend the bifurcation curves away from the equilibrium point and determine the oscillatory conditions. When external periodic force is present, we focus on the special case of periodically multiplicatively-forced fully-differential, negative-resistor, LC oscillators and use Harmonic Balance techniques to derive analytical expressions estimating the locking range in the weak injection regime. The results are used to calculate the locking range of a harmonically forced complementary BJT oscillator yielding explicit expressions closely aligned with experimental measurements, thus verifying the validity of the analysis.
{"title":"Nonlinear Analysis of Differential LC Oscillators and Injection Locked Frequency Dividers","authors":"Konstantinos Metaxas;Vassilis Alimisis;Costas Oustoglou;Yannis Kominis;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2025.3545904","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3545904","url":null,"abstract":"A comprehensive nonlinear analysis of autonomous and periodically forced fully-differential, negative-resistor LC oscillators is presented. Through nonlinear transformations in the state space, it is shown that oscillators within this class exhibit qualitatively similar dynamical behavior in terms of their limit cycles and bifurcation curves, at least within an open region containing the origin. The case of autonomous, complementary BJT oscillators is used to validate the qualitative analysis and demonstrate a general approach of how to numerically extend the bifurcation curves away from the equilibrium point and determine the oscillatory conditions. When external periodic force is present, we focus on the special case of periodically multiplicatively-forced fully-differential, negative-resistor, LC oscillators and use Harmonic Balance techniques to derive analytical expressions estimating the locking range in the weak injection regime. The results are used to calculate the locking range of a harmonically forced complementary BJT oscillator yielding explicit expressions closely aligned with experimental measurements, thus verifying the validity of the analysis.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"100-109"},"PeriodicalIF":2.4,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10904493","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-04DOI: 10.1109/OJCAS.2025.3538707
Yufei Xiao;Kai Cai;Xiaohu Ge;Yong Xiao
Energy consumption evaluation for data processing tasks, such as encoding and decoding, is a critical consideration in designing very large scale integration (VLSI) circuits. Incorporating both information theory and circuit perspectives, a new general energy consumption model is proposed to capture the energy consumption of channel decoder circuits. For the binary erasure channel, lower bounds of energy consumption are derived for two-dimensional (2D) and three-dimensional (3D) decoder circuits under specified error probabilities, along with scaling rules for energy consumption in each case. Based on the proposed model, the lower bounds of energy consumption for staged serial and parallel implementations are derived, and a specific threshold value is identified to determine the parallel or serial decoding in decoder circuits. Staged serial implementations in 3D decoder circuits achieve a higher energy efficiency than fully parallel implementations when the processed data exceed 48 bits. Simulation results further demonstrate that the energy efficiency of 3D decoders improves with increasing data volume. When the number of input bits is 648, 1296 and 1944, the energy consumption of 3D decoders is reduced by 11.58%, 13.07%, and 13.86% compared to 2D decoders, respectively. The energy consumption of 3D decoders surpasses that of 2D decoders when the decoding error probability falls below a specific threshold of 0.035492. These results provide a foundational framework and benchmarks for analyzing and optimizing the energy consumption of 2D and 3D channel decoder circuits, enabling more efficient VLSI circuit designs.
{"title":"Energy Consumption Modeling of 2-D and 3-D Decoder Circuits","authors":"Yufei Xiao;Kai Cai;Xiaohu Ge;Yong Xiao","doi":"10.1109/OJCAS.2025.3538707","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3538707","url":null,"abstract":"Energy consumption evaluation for data processing tasks, such as encoding and decoding, is a critical consideration in designing very large scale integration (VLSI) circuits. Incorporating both information theory and circuit perspectives, a new general energy consumption model is proposed to capture the energy consumption of channel decoder circuits. For the binary erasure channel, lower bounds of energy consumption are derived for two-dimensional (2D) and three-dimensional (3D) decoder circuits under specified error probabilities, along with scaling rules for energy consumption in each case. Based on the proposed model, the lower bounds of energy consumption for staged serial and parallel implementations are derived, and a specific threshold value is identified to determine the parallel or serial decoding in decoder circuits. Staged serial implementations in 3D decoder circuits achieve a higher energy efficiency than fully parallel implementations when the processed data exceed 48 bits. Simulation results further demonstrate that the energy efficiency of 3D decoders improves with increasing data volume. When the number of input bits is 648, 1296 and 1944, the energy consumption of 3D decoders is reduced by 11.58%, 13.07%, and 13.86% compared to 2D decoders, respectively. The energy consumption of 3D decoders surpasses that of 2D decoders when the decoding error probability falls below a specific threshold of 0.035492. These results provide a foundational framework and benchmarks for analyzing and optimizing the energy consumption of 2D and 3D channel decoder circuits, enabling more efficient VLSI circuit designs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"74-84"},"PeriodicalIF":2.4,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10870295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/OJCAS.2025.3533978
{"title":"2024 Index IEEE Open Journal of Circuits and Systems Vol. 5","authors":"","doi":"10.1109/OJCAS.2025.3533978","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3533978","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"408-417"},"PeriodicalIF":2.4,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854515","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1109/OJCAS.2025.3525785
{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2025.3525785","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3525785","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10834607","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-31DOI: 10.1109/OJCAS.2024.3524363
Sayma Nowshin Chowdhury;Matthew Chen;Sahil Shah
Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.
{"title":"Analysis and Verilog-A Modeling of Floating-Gate Transistors","authors":"Sayma Nowshin Chowdhury;Matthew Chen;Sahil Shah","doi":"10.1109/OJCAS.2024.3524363","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3524363","url":null,"abstract":"Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"63-73"},"PeriodicalIF":2.4,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818976","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJCAS.2024.3517215
{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2024.3517215","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517215","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805493","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJCAS.2024.3517219
{"title":"Instruction for Authors","authors":"","doi":"10.1109/OJCAS.2024.3517219","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517219","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"408-408"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805492","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142843066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJCAS.2024.3472124
Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger
An application specific integrated circuit (ASIC) and a custom-made microelectromechanical system (MEMS) sensor are presented, designed to function together as a sensor system for measuring low amplitude low frequency magnetic fields. The MEMS system comprises several free-standing double-wing magnetoelectric resonators with a size of $900~mu $ m x $150~mu $ m to measure alternating magnetic fields in the sub-kilohertz regime. It utilizes piezolelectric (AlN) and magnetostrictive (FeCoSiB) layers to exploit the delta-E effect for magnetic field sensing. On the ASIC a three-channel current-reuse amplifier with lateral bipolar transistors in the input stage is implemented occupying a chip area of 0.0864 mm2. Measurements demonstrate a voltage gain of 40 dB with a 3-dB bandwidth of 75 kHz and an input referred noise floor of 8 nV/ $surd $ Hz while consuming $199~mu $ W per channel. The sensor system is capable of detecting magnetic fields with a limit of detection (LOD) of 16 nT/ $surd $ Hz for single sensor elements. By operating three sensor elements in parallel, one on each amplifier channel, the LOD is further reduced to 10 nT/ $surd $ Hz. Owing to the high reproducibility of the sensor elements, this improvement in the LOD is close to the ideal value of $surd 3$ . The results imply that the system can be scaled to large numbers of sensor elements without principle obstacles.
{"title":"ASIC Current-Reuse Amplifier With MEMS Delta-E Magnetic Field Sensors","authors":"Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger","doi":"10.1109/OJCAS.2024.3472124","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3472124","url":null,"abstract":"An application specific integrated circuit (ASIC) and a custom-made microelectromechanical system (MEMS) sensor are presented, designed to function together as a sensor system for measuring low amplitude low frequency magnetic fields. The MEMS system comprises several free-standing double-wing magnetoelectric resonators with a size of \u0000<inline-formula> <tex-math>$900~mu $ </tex-math></inline-formula>\u0000m x \u0000<inline-formula> <tex-math>$150~mu $ </tex-math></inline-formula>\u0000m to measure alternating magnetic fields in the sub-kilohertz regime. It utilizes piezolelectric (AlN) and magnetostrictive (FeCoSiB) layers to exploit the delta-E effect for magnetic field sensing. On the ASIC a three-channel current-reuse amplifier with lateral bipolar transistors in the input stage is implemented occupying a chip area of 0.0864 mm2. Measurements demonstrate a voltage gain of 40 dB with a 3-dB bandwidth of 75 kHz and an input referred noise floor of 8 nV/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz while consuming \u0000<inline-formula> <tex-math>$199~mu $ </tex-math></inline-formula>\u0000W per channel. The sensor system is capable of detecting magnetic fields with a limit of detection (LOD) of 16 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz for single sensor elements. By operating three sensor elements in parallel, one on each amplifier channel, the LOD is further reduced to 10 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz. Owing to the high reproducibility of the sensor elements, this improvement in the LOD is close to the ideal value of \u0000<inline-formula> <tex-math>$surd 3$ </tex-math></inline-formula>\u0000. The results imply that the system can be scaled to large numbers of sensor elements without principle obstacles.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"398-407"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJCAS.2024.3466395
Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen
This paper presents the design and cryogenic electrical characterization of a voltage reference and a linear voltage regulator at temperatures between 6 K and 300 K. Both circuits are employed as test vehicles for the experimental performance evaluation of the 22 nm FDSOI MOS technology when used as platform for the development of cryogenic analog systems, whose role is relevant in Quantum Computing (QC) applications. Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. In particular, we focus on the cryogenic threshold voltage $(V_{text {th}})$ saturation, the transconductance $(g_{m})$ increase and the low frequency (LF) excess noise. Our experimental results indicate that the cryogenic $V_{text {th}}$ saturation and the $g_{m}$ increase can be used as circuit design tools, while the LF excess noise is a performance handicap for cryogenic analog circuits.
{"title":"Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology","authors":"Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen","doi":"10.1109/OJCAS.2024.3466395","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3466395","url":null,"abstract":"This paper presents the design and cryogenic electrical characterization of a voltage reference and a linear voltage regulator at temperatures between 6 K and 300 K. Both circuits are employed as test vehicles for the experimental performance evaluation of the 22 nm FDSOI MOS technology when used as platform for the development of cryogenic analog systems, whose role is relevant in Quantum Computing (QC) applications. Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. In particular, we focus on the cryogenic threshold voltage \u0000<inline-formula> <tex-math>$(V_{text {th}})$ </tex-math></inline-formula>\u0000 saturation, the transconductance \u0000<inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula>\u0000 increase and the low frequency (LF) excess noise. Our experimental results indicate that the cryogenic \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 saturation and the \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000 increase can be used as circuit design tools, while the LF excess noise is a performance handicap for cryogenic analog circuits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"377-386"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801233","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over $2{times }$ . These strengths underscore its significant impact and applicability in the domain of circuit design.
本文介绍了一种简化的SystemVerilog和Verilog-to-Verilog- a （V2Va +）转换工具，该工具可自动将可合成的SystemVerilog和Verilog代码转换为Verilog- a代码，从而实现模拟和数字电路的并发仿真。通过一套映射规则，V2Va +促进了模拟环境下的混合信号仿真，消除了对单独的混合信号仿真引擎的需求，并克服了多种类型的EDA许可障碍。V2Va +翻译工具包括两个组成部分：解析器功能，负责从SystemVerilog和Verilog文件中提取信息，以及Verilog- a生成器，负责生成相应的Verilog- a代码。V2Va +擅长处理复杂性，确保准确性，提高效率。它有效地管理广泛的设计复杂性，在转换过程中保持功能一致性，并显着减少仿真时间，实现超过2倍的加速。这些优势强调了它在电路设计领域的重要影响和适用性。
{"title":"V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation","authors":"Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li","doi":"10.1109/OJCAS.2024.3451530","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3451530","url":null,"abstract":"This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over \u0000<inline-formula> <tex-math>$2{times }$ </tex-math></inline-formula>\u0000. These strengths underscore its significant impact and applicability in the domain of circuit design.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"387-397"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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