Pub Date : 2024-12-17DOI: 10.1109/OJCAS.2024.3517215
{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2024.3517215","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517215","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805493","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJCAS.2024.3517219
{"title":"Instruction for Authors","authors":"","doi":"10.1109/OJCAS.2024.3517219","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3517219","url":null,"abstract":"","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"408-408"},"PeriodicalIF":2.4,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10805492","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142843066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJCAS.2024.3472124
Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger
An application specific integrated circuit (ASIC) and a custom-made microelectromechanical system (MEMS) sensor are presented, designed to function together as a sensor system for measuring low amplitude low frequency magnetic fields. The MEMS system comprises several free-standing double-wing magnetoelectric resonators with a size of $900~mu $ m x $150~mu $ m to measure alternating magnetic fields in the sub-kilohertz regime. It utilizes piezolelectric (AlN) and magnetostrictive (FeCoSiB) layers to exploit the delta-E effect for magnetic field sensing. On the ASIC a three-channel current-reuse amplifier with lateral bipolar transistors in the input stage is implemented occupying a chip area of 0.0864 mm2. Measurements demonstrate a voltage gain of 40 dB with a 3-dB bandwidth of 75 kHz and an input referred noise floor of 8 nV/ $surd $ Hz while consuming $199~mu $ W per channel. The sensor system is capable of detecting magnetic fields with a limit of detection (LOD) of 16 nT/ $surd $ Hz for single sensor elements. By operating three sensor elements in parallel, one on each amplifier channel, the LOD is further reduced to 10 nT/ $surd $ Hz. Owing to the high reproducibility of the sensor elements, this improvement in the LOD is close to the ideal value of $surd 3$ . The results imply that the system can be scaled to large numbers of sensor elements without principle obstacles.
{"title":"ASIC Current-Reuse Amplifier With MEMS Delta-E Magnetic Field Sensors","authors":"Patrick Wiegand;Sebastian Simmich;Fatih Ilgaz;Franz Faupel;Benjamin Spetzler;Robert Rieger","doi":"10.1109/OJCAS.2024.3472124","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3472124","url":null,"abstract":"An application specific integrated circuit (ASIC) and a custom-made microelectromechanical system (MEMS) sensor are presented, designed to function together as a sensor system for measuring low amplitude low frequency magnetic fields. The MEMS system comprises several free-standing double-wing magnetoelectric resonators with a size of \u0000<inline-formula> <tex-math>$900~mu $ </tex-math></inline-formula>\u0000m x \u0000<inline-formula> <tex-math>$150~mu $ </tex-math></inline-formula>\u0000m to measure alternating magnetic fields in the sub-kilohertz regime. It utilizes piezolelectric (AlN) and magnetostrictive (FeCoSiB) layers to exploit the delta-E effect for magnetic field sensing. On the ASIC a three-channel current-reuse amplifier with lateral bipolar transistors in the input stage is implemented occupying a chip area of 0.0864 mm2. Measurements demonstrate a voltage gain of 40 dB with a 3-dB bandwidth of 75 kHz and an input referred noise floor of 8 nV/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz while consuming \u0000<inline-formula> <tex-math>$199~mu $ </tex-math></inline-formula>\u0000W per channel. The sensor system is capable of detecting magnetic fields with a limit of detection (LOD) of 16 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz for single sensor elements. By operating three sensor elements in parallel, one on each amplifier channel, the LOD is further reduced to 10 nT/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz. Owing to the high reproducibility of the sensor elements, this improvement in the LOD is close to the ideal value of \u0000<inline-formula> <tex-math>$surd 3$ </tex-math></inline-formula>\u0000. The results imply that the system can be scaled to large numbers of sensor elements without principle obstacles.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"398-407"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801234","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1109/OJCAS.2024.3466395
Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen
This paper presents the design and cryogenic electrical characterization of a voltage reference and a linear voltage regulator at temperatures between 6 K and 300 K. Both circuits are employed as test vehicles for the experimental performance evaluation of the 22 nm FDSOI MOS technology when used as platform for the development of cryogenic analog systems, whose role is relevant in Quantum Computing (QC) applications. Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. In particular, we focus on the cryogenic threshold voltage $(V_{text {th}})$ saturation, the transconductance $(g_{m})$ increase and the low frequency (LF) excess noise. Our experimental results indicate that the cryogenic $V_{text {th}}$ saturation and the $g_{m}$ increase can be used as circuit design tools, while the LF excess noise is a performance handicap for cryogenic analog circuits.
{"title":"Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology","authors":"Alfonso R. Cabrera-Galicia;Arun Ashok;Patrick Vliex;Andre Kruth;André Zambanini;Stefan van Waasen","doi":"10.1109/OJCAS.2024.3466395","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3466395","url":null,"abstract":"This paper presents the design and cryogenic electrical characterization of a voltage reference and a linear voltage regulator at temperatures between 6 K and 300 K. Both circuits are employed as test vehicles for the experimental performance evaluation of the 22 nm FDSOI MOS technology when used as platform for the development of cryogenic analog systems, whose role is relevant in Quantum Computing (QC) applications. Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. In particular, we focus on the cryogenic threshold voltage \u0000<inline-formula> <tex-math>$(V_{text {th}})$ </tex-math></inline-formula>\u0000 saturation, the transconductance \u0000<inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula>\u0000 increase and the low frequency (LF) excess noise. Our experimental results indicate that the cryogenic \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 saturation and the \u0000<inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula>\u0000 increase can be used as circuit design tools, while the LF excess noise is a performance handicap for cryogenic analog circuits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"377-386"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801233","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over $2{times }$ . These strengths underscore its significant impact and applicability in the domain of circuit design.
本文介绍了一种简化的SystemVerilog和Verilog-to-Verilog- a （V2Va +）转换工具，该工具可自动将可合成的SystemVerilog和Verilog代码转换为Verilog- a代码，从而实现模拟和数字电路的并发仿真。通过一套映射规则，V2Va +促进了模拟环境下的混合信号仿真，消除了对单独的混合信号仿真引擎的需求，并克服了多种类型的EDA许可障碍。V2Va +翻译工具包括两个组成部分：解析器功能，负责从SystemVerilog和Verilog文件中提取信息，以及Verilog- a生成器，负责生成相应的Verilog- a代码。V2Va +擅长处理复杂性，确保准确性，提高效率。它有效地管理广泛的设计复杂性，在转换过程中保持功能一致性，并显着减少仿真时间，实现超过2倍的加速。这些优势强调了它在电路设计领域的重要影响和适用性。
{"title":"V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation","authors":"Chao Wang;Yicong Shao;Jiajie Huang;Wangzilu Lu;Zhiwen Gu;Longfan Li;Yuhang Zhang;Jian Zhao;Wei Mao;Yongfu Li","doi":"10.1109/OJCAS.2024.3451530","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3451530","url":null,"abstract":"This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from SystemVerilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over \u0000<inline-formula> <tex-math>$2{times }$ </tex-math></inline-formula>\u0000. These strengths underscore its significant impact and applicability in the domain of circuit design.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"387-397"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10801235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.
{"title":"Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability","authors":"Tobias Kaiser;Esther Gottschalk;Kai Biethahn;Friedel Gerfers","doi":"10.1109/OJCAS.2024.3518110","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3518110","url":null,"abstract":"This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"1-13"},"PeriodicalIF":2.4,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10802954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of $1.96times 10^{-4}$ for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of $10^{-12}$ at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.
{"title":"Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model","authors":"Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou","doi":"10.1109/OJCAS.2024.3510921","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3510921","url":null,"abstract":"This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of \u0000<inline-formula> <tex-math>$1.96times 10^{-4}$ </tex-math></inline-formula>\u0000 for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of \u0000<inline-formula> <tex-math>$10^{-12}$ </tex-math></inline-formula>\u0000 at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"14-25"},"PeriodicalIF":2.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777587","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-03DOI: 10.1109/OJCAS.2024.3509746
Bangda Yang;Trevor Caldwell;Anthony Chan Carusone
Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).
近年来，动态放大器（DA）由于其基于集成的高能效解决方案而成为静态电流闭环运算跨导放大器（OTA）的热门替代方案，但其主要限制是其线性性能。我们提出了一种通过模拟技术实现- 52 dB总谐波失真（THD）的DA，通过这种模拟技术，输入晶体管中的扩展和压缩非线性相互抵消。采用GlobalFoundries的22nm完全耗尽绝缘体上硅（FDSOI）工艺，设计并制造了一种在输入缓冲器和第一残留放大器（RA）级均采用线性化DA的管道sar模数转换器（ADC）。测量结果表明，该ADC在920 MS/s下的信噪比（SNDR）为37 dB，消耗的总功率为1.8mW, Walden form （FOMW）为34.9 fJ/conv。使用输入缓冲器，实现的FOMW为68.4 fJ/conv。在最佳偏置下，线性化技术提供了8db的SNDR改进，而功率开销约为5%，可以忽略不计。一般来说，预计8 dB SNDR的改进将需要限制失配设计（Walden FOM）的2.5倍功耗或限制噪声设计（Schreier FOM）的6.3倍功耗。
{"title":"An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI","authors":"Bangda Yang;Trevor Caldwell;Anthony Chan Carusone","doi":"10.1109/OJCAS.2024.3509746","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509746","url":null,"abstract":"Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"50-62"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10774063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-03DOI: 10.1109/OJCAS.2024.3509627
Andrew Maclellan;Louise H. Crockett;Robert W. Stewart
This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.
{"title":"RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training","authors":"Andrew Maclellan;Louise H. Crockett;Robert W. Stewart","doi":"10.1109/OJCAS.2024.3509627","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509627","url":null,"abstract":"This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"38-49"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive analysis of nonlinearities in differential pairs with source degeneration and their impact on wireline communication applications. We assess the suitability of three nonlinearity metrics to quantify the receiver analog front-end performance. This work identifies the primary sources of nonlinearity in differential pair circuits including, broadband Variable Gain Amplifiers (VGAs) and Continuous-Time Linear Equalizers (CTLEs) using circuit simulations. Furthermore, the linearity performance of different front-end configurations is evaluated, providing design insights. The analysis is validated through simulations with a 22-nm FDSOI technology.
{"title":"Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications","authors":"Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone","doi":"10.1109/OJCAS.2024.3507543","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3507543","url":null,"abstract":"This paper presents a comprehensive analysis of nonlinearities in differential pairs with source degeneration and their impact on wireline communication applications. We assess the suitability of three nonlinearity metrics to quantify the receiver analog front-end performance. This work identifies the primary sources of nonlinearity in differential pair circuits including, broadband Variable Gain Amplifiers (VGAs) and Continuous-Time Linear Equalizers (CTLEs) using circuit simulations. Furthermore, the linearity performance of different front-end configurations is evaluated, providing design insights. The analysis is validated through simulations with a 22-nm FDSOI technology.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"26-37"},"PeriodicalIF":2.4,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769573","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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