This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of $1.96times 10^{-4}$ for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of $10^{-12}$ at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.
{"title":"Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model","authors":"Chung-Lun Tu;Chen-Yuan Tseng;Wei-Che Lee;Kang-Lun Chiu;Pei-Yun Tsai;Shyh-Jye Jou","doi":"10.1109/OJCAS.2024.3510921","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3510921","url":null,"abstract":"This article presents an advanced synchronization and channel estimation architecture for multi-stream MIMO systems in sub-terahertz environments. To streamline hardware complexity, we employ Golay cross-correlation across all detection and estimation schemes. Key innovations include a precise timing detection algorithm that utilizes pulse shaping impulse response and quadratic regression, along with multiple window-based approaches to enhance performance against non-ideal effects. At the architectural level, a shared optimized Golay correlator reduces hardware usage by 23%, efficiently handling multiple correlation lengths in a single design. Additionally, we propose an indexing-count method that addresses sorting challenges, achieving notable improvements in processing speed and complexity reduction. The proposed design supports the highest modulation schemes defined in IEEE Std. 802.15.3d, achieving an uncoded bit error rate of \u0000<inline-formula> <tex-math>$1.96times 10^{-4}$ </tex-math></inline-formula>\u0000 for 16-QAM and 64-QAM at SNRs of 18.8 dB and 25 dB, respectively. This meets the IEEE Std. 802.15.3d standard of \u0000<inline-formula> <tex-math>$10^{-12}$ </tex-math></inline-formula>\u0000 at SNRs of 19.6 dB and 25.6 dB for these modulation schemes after error correction. Our hardware operates at a clock rate of 1.76 GHz, enabling dual-stream transmission and achieving a throughput of 21.12 Gb/s with 64-QAM modulation.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"14-25"},"PeriodicalIF":2.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777587","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-03DOI: 10.1109/OJCAS.2024.3509746
Bangda Yang;Trevor Caldwell;Anthony Chan Carusone
Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).
近年来，动态放大器（DA）由于其基于集成的高能效解决方案而成为静态电流闭环运算跨导放大器（OTA）的热门替代方案，但其主要限制是其线性性能。我们提出了一种通过模拟技术实现- 52 dB总谐波失真（THD）的DA，通过这种模拟技术，输入晶体管中的扩展和压缩非线性相互抵消。采用GlobalFoundries的22nm完全耗尽绝缘体上硅（FDSOI）工艺，设计并制造了一种在输入缓冲器和第一残留放大器（RA）级均采用线性化DA的管道sar模数转换器（ADC）。测量结果表明，该ADC在920 MS/s下的信噪比（SNDR）为37 dB，消耗的总功率为1.8mW, Walden form （FOMW）为34.9 fJ/conv。使用输入缓冲器，实现的FOMW为68.4 fJ/conv。在最佳偏置下，线性化技术提供了8db的SNDR改进，而功率开销约为5%，可以忽略不计。一般来说，预计8 dB SNDR的改进将需要限制失配设计（Walden FOM）的2.5倍功耗或限制噪声设计（Schreier FOM）的6.3倍功耗。
{"title":"An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI","authors":"Bangda Yang;Trevor Caldwell;Anthony Chan Carusone","doi":"10.1109/OJCAS.2024.3509746","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509746","url":null,"abstract":"Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"50-62"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10774063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-03DOI: 10.1109/OJCAS.2024.3509627
Andrew Maclellan;Louise H. Crockett;Robert W. Stewart
This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.
{"title":"RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training","authors":"Andrew Maclellan;Louise H. Crockett;Robert W. Stewart","doi":"10.1109/OJCAS.2024.3509627","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3509627","url":null,"abstract":"This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"38-49"},"PeriodicalIF":2.4,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive analysis of nonlinearities in differential pairs with source degeneration and their impact on wireline communication applications. We assess the suitability of three nonlinearity metrics to quantify the receiver analog front-end performance. This work identifies the primary sources of nonlinearity in differential pair circuits including, broadband Variable Gain Amplifiers (VGAs) and Continuous-Time Linear Equalizers (CTLEs) using circuit simulations. Furthermore, the linearity performance of different front-end configurations is evaluated, providing design insights. The analysis is validated through simulations with a 22-nm FDSOI technology.
{"title":"Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications","authors":"Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone","doi":"10.1109/OJCAS.2024.3507543","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3507543","url":null,"abstract":"This paper presents a comprehensive analysis of nonlinearities in differential pairs with source degeneration and their impact on wireline communication applications. We assess the suitability of three nonlinearity metrics to quantify the receiver analog front-end performance. This work identifies the primary sources of nonlinearity in differential pair circuits including, broadband Variable Gain Amplifiers (VGAs) and Continuous-Time Linear Equalizers (CTLEs) using circuit simulations. Furthermore, the linearity performance of different front-end configurations is evaluated, providing design insights. The analysis is validated through simulations with a 22-nm FDSOI technology.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"26-37"},"PeriodicalIF":2.4,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769573","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a generalized control architecture for implementing the active balancing of the flying capacitor voltage in any kind of 3-level switching-mode DC-DC converters, independently from the desired conversion ratio or targeted output power level. The proposed strategy is based on the detection of the flying capacitor voltage through the inductor voltage, sensed at the switching node, and acts on the duty cycle of the PWM (Pulse Width Modulation) control signals in order to make the correction, implementing the voltage balancing. The circuit implementation and its operation are described in detail. Extensive simulations were performed in the SIMPLIS environment, taking as examples the cases of a 3-level buck, 3-level boost and 3-level inverting buck-boost DC-DC converter and considering different combinations of input voltage, output voltage and load current. Moreover, the proposed strategy was implemented in the control architecture of a hybrid switched-capacitor 3-level inverting buck-boost converter, fabricated in a 180-nm BCD process. The effectiveness and the versatility of the proposed active voltage balancing strategy and its circuit implementation were, therefore, verified both through simulations and experimentally.
{"title":"A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC–DC Converters","authors":"Elisabetta Moisello;Samuele Fusetto;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/OJCAS.2024.3492320","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3492320","url":null,"abstract":"This paper presents a generalized control architecture for implementing the active balancing of the flying capacitor voltage in any kind of 3-level switching-mode DC-DC converters, independently from the desired conversion ratio or targeted output power level. The proposed strategy is based on the detection of the flying capacitor voltage through the inductor voltage, sensed at the switching node, and acts on the duty cycle of the PWM (Pulse Width Modulation) control signals in order to make the correction, implementing the voltage balancing. The circuit implementation and its operation are described in detail. Extensive simulations were performed in the SIMPLIS environment, taking as examples the cases of a 3-level buck, 3-level boost and 3-level inverting buck-boost DC-DC converter and considering different combinations of input voltage, output voltage and load current. Moreover, the proposed strategy was implemented in the control architecture of a hybrid switched-capacitor 3-level inverting buck-boost converter, fabricated in a 180-nm BCD process. The effectiveness and the versatility of the proposed active voltage balancing strategy and its circuit implementation were, therefore, verified both through simulations and experimentally.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"365-376"},"PeriodicalIF":2.4,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10745640","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142672080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a $50times $ reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.
本文提出了一种基于相关性的背景线性度校准技术，用于对逐次逼近寄存器（SAR）辅助模数转换器（ADC）中的位权进行数字校正。在典型的基于抖动的校准技术中，信号的动态范围（DR）不可避免地会减小，而在这项工作中，通过简单的切换方案将一个小的抖动信号注入到输入路径中。后端冗余避免了相关的 DR 损失。我们还介绍了一种电容扫描抖动方法，可同时独立识别多个比特权重。此外，我们还提出了一种数字域输入干扰消除（IIC）技术，以加快基于相关性校准的收敛速度。通过理论表述和系统仿真分析了所提出的校准和加速技术。仿真结果是通过一个 12 位 SAR 辅助两级流水线 ADC 模型得出的。由于采用了我们提出的校准方法，无杂散动态范围 (SFDR) 从 60.1 dB 提高到 84.8 dB，信噪比和失真比 (SNDR) 从 55.4 dB 提高到 72.5 dB。通过比较使用和不使用所提出的 IIC 技术的情况，收敛周期可减少 50 倍。所提出的校准技术可用于克服固有的 DAC 失配和残差增益误差，以实现高线性度 ADC，如许多不同应用中的 SAR 辅助 ADC。
{"title":"DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation","authors":"Lizhen Zhang;Bo Gao;Kun-Woo Park;Kent Edrian Lozada;Raymond Mabilangan;Hyeongjin Kim;Jianhui Wu;Seung-Tak Ryu","doi":"10.1109/OJCAS.2024.3486809","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3486809","url":null,"abstract":"In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a \u0000<inline-formula> <tex-math>$50times $ </tex-math></inline-formula>\u0000 reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"349-364"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-28DOI: 10.1109/OJCAS.2024.3487072
Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville
Counterfeit electronic components are known to enter supply chains through recycling, with these already-aged components creating serious reliability risks, particularly for critical infrastructure systems. A number of recycled integrated circuit (IC) risk mitigation approaches have been proposed, but these generally lack pragmatic feasibility. This work proposes a novel real-world deployable on-chip sensor that: 1) is tamper-resistant by exploiting persistent changes caused by hot carrier injection (HCI); 2) generates a DC signal measurable by common low-cost test equipment; and 3) reuses an existing I/O interface, including existing pins; while 4) requiring a very small footprint. Combining this sensor with a random sample-based testing strategy allows for low-cost and time efficient detection of fraudulently recycled batches of ICs. Through simulation-based validation using process-accurate models of a 65 nm technology we show that employing a random sample size as small as 130 is sufficient for identifying such batches with a statistical significance level of 0.01.
{"title":"A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling","authors":"Alexandros Dimopoulos;Mihai Sima;Stephen W. Neville","doi":"10.1109/OJCAS.2024.3487072","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3487072","url":null,"abstract":"Counterfeit electronic components are known to enter supply chains through recycling, with these already-aged components creating serious reliability risks, particularly for critical infrastructure systems. A number of recycled integrated circuit (IC) risk mitigation approaches have been proposed, but these generally lack pragmatic feasibility. This work proposes a novel real-world deployable on-chip sensor that: 1) is tamper-resistant by exploiting persistent changes caused by hot carrier injection (HCI); 2) generates a DC signal measurable by common low-cost test equipment; and 3) reuses an existing I/O interface, including existing pins; while 4) requiring a very small footprint. Combining this sensor with a random sample-based testing strategy allows for low-cost and time efficient detection of fraudulently recycled batches of ICs. Through simulation-based validation using process-accurate models of a 65 nm technology we show that employing a random sample size as small as 130 is sufficient for identifying such batches with a statistical significance level of 0.01.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"341-348"},"PeriodicalIF":2.4,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736936","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142600218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-17DOI: 10.1109/OJCAS.2024.3482469
Hiroto Tagata;Takashi Sato;Hiromitsu Awano
This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two input ports, simultaneously performing two binary multiply-and-accumulate (MAC) operations on left and right bitlines. This approach enables a twofold increase in throughput without significantly increasing area or power consumption, since the area overhead for doubling throughput is only two additional WL wires compared to the conventional 8T-SRAM. In addition, the proposed circuit supports binary and ternary activation input, allowing flexible adjustment of high energy efficiency and high inference accuracy depending on the application. The proposed SRAM macro consists of a $128 times 128$ SRAM array that outputs the MAC operation results of 96 binary/ternary inputs and $96 times 128$ binary weights as 1-5 bit digital values. The proposed circuit performance was evaluated by post-layout simulation with the 22-nm process layout of the overall CIM macro. The proposed circuit is capable of high-speed operation at 1 GHz. It achieves a maximum area efficiency of 3320 TOPS/mm2, which is $3.4 times $ higher compared to existing research with a reasonable energy efficiency of 1471 TOPS/W. The simulated inference accuracies of the proposed circuit are 96.45%/97.67% for MNIST dataset with binary/ternary MLP model, and 86.32%/88.56% for CIFAR-10 dataset with binary/ternary VGG-like CNN model.
{"title":"Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline","authors":"Hiroto Tagata;Takashi Sato;Hiromitsu Awano","doi":"10.1109/OJCAS.2024.3482469","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3482469","url":null,"abstract":"This paper proposes a novel 8T-SRAM based computing-in-memory (CIM) accelerator for the Binary/Ternary neural networks. The proposed split dual-port 8T-SRAM cell has two input ports, simultaneously performing two binary multiply-and-accumulate (MAC) operations on left and right bitlines. This approach enables a twofold increase in throughput without significantly increasing area or power consumption, since the area overhead for doubling throughput is only two additional WL wires compared to the conventional 8T-SRAM. In addition, the proposed circuit supports binary and ternary activation input, allowing flexible adjustment of high energy efficiency and high inference accuracy depending on the application. The proposed SRAM macro consists of a \u0000<inline-formula> <tex-math>$128 times 128$ </tex-math></inline-formula>\u0000 SRAM array that outputs the MAC operation results of 96 binary/ternary inputs and \u0000<inline-formula> <tex-math>$96 times 128$ </tex-math></inline-formula>\u0000 binary weights as 1-5 bit digital values. The proposed circuit performance was evaluated by post-layout simulation with the 22-nm process layout of the overall CIM macro. The proposed circuit is capable of high-speed operation at 1 GHz. It achieves a maximum area efficiency of 3320 TOPS/mm2, which is \u0000<inline-formula> <tex-math>$3.4 times $ </tex-math></inline-formula>\u0000 higher compared to existing research with a reasonable energy efficiency of 1471 TOPS/W. The simulated inference accuracies of the proposed circuit are 96.45%/97.67% for MNIST dataset with binary/ternary MLP model, and 86.32%/88.56% for CIFAR-10 dataset with binary/ternary VGG-like CNN model.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"328-340"},"PeriodicalIF":2.4,"publicationDate":"2024-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10721281","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142579204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-16DOI: 10.1109/OJCAS.2024.3427693
Miad Laghaei;Hossein Shakiba;Ali Sheikholeslami
Multicarrier modulation, while providing a theoretical pathway to data rates approaching the Shannon limit and being extensively utilized in wireless communication, has encountered limited application in high-speed wireline communication. This limitation is primarily due to substantial large amplitude peaks, which necessitates a reduction in the signal’s power levels to circumvent signal clipping. This, in turn, results in a low signal-to-noise ratio (SNR) which puts these modulations at a serious disadvantage compared to conventional modulation schemes. This work proposes a novel companding solution in the design of the Continuous Time Linear Equalizer (CTLE) alongside nonlinear blocks to reduce Peak to Average Power Ratio (PAPR), therefore improving the overall link performance. This paper presents a PAPR reduction technique and its implementation in the receiver, distinguishing it from previous studies that place the compander at the transmitter where it fails to work in the presence of an Inter-Symbol Interference (ISI) channel. A theoretical study as well as an implementation of this method is provided, and the merits and performance improvements are demonstrated.
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Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.
{"title":"Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective","authors":"Shuang Song;Dehong Wang;Mengyu Li;Siyao Cao;Feijun Zheng;Kai Huang;Zhichao Tan;Sijun Du;Menglian Zhao","doi":"10.1109/OJCAS.2024.3423484","DOIUrl":"10.1109/OJCAS.2024.3423484","url":null,"abstract":"Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"267-290"},"PeriodicalIF":2.4,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10585308","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141551872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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