Pub Date : 2024-04-16DOI: 10.1109/OJCAS.2023.3335116
Yi Mao;Gengzhen Qi;Pui-In Mak
This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.
{"title":"Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique","authors":"Yi Mao;Gengzhen Qi;Pui-In Mak","doi":"10.1109/OJCAS.2023.3335116","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3335116","url":null,"abstract":"This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500899","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a supervised speech enhancement (SE) method utilising a noise-aware four-layer deep neural network and training target switching. For optimal speech denoising, the SE system, trained with multiple-target joint learning, switches between mapping-based, masking-based, or complementary processing, depending on the level of noise contamination detected. Optimisation techniques, including ternary quantisation, structural pruning, efficient sparse matrix representation and cost-effective approximations for complex computations, were implemented to reduce area, memory, and power requirements. Up to 19.1x compression was obtained, and all weights could be stored on the on-chip memory. When processing NOISEX-92 noises, the system achieved an average short-time objective intelligibility (STOI) and perceptual evaluation of speech quality (PESQ) scores of 0.81 and 1.62, respectively, outperforming SE algorithms trained with only a single learning target. The proposed SE processor was implemented on a field programmable gate array (FPGA) for proof of concept. Mapping the design on a 65-nm CMOS process led to a chip core area of $3.88~mm^{2}$ and a power consumption of 1.91 mW when operating at a 10 MHz clock frequency.
本文介绍了一种利用噪声感知四层深度神经网络和训练目标切换的有监督语音增强（SE）方法。为了优化语音去噪，通过多目标联合学习训练的 SE 系统会根据检测到的噪声污染程度，在基于映射、基于掩蔽或互补处理之间进行切换。该系统采用了优化技术，包括三元量化、结构剪枝、高效稀疏矩阵表示以及用于复杂计算的经济有效的近似方法，以减少对面积、内存和功率的需求。压缩率高达 19.1 倍，所有权重均可存储在片上存储器中。在处理 NOISEX-92 噪音时，该系统的平均短时客观可懂度（STOI）和语音质量感知评估（PESQ）得分分别为 0.81 和 1.62，优于仅使用单一学习目标训练的 SE 算法。为验证概念，在现场可编程门阵列（FPGA）上实现了所提出的 SE 处理器。将设计映射到 65 纳米 CMOS 工艺上后，芯片内核面积为 3.88~mm^{2}$ ，在 10 MHz 时钟频率下工作时的功耗为 1.91 mW。
{"title":"Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning","authors":"Salinna Abdullah;Majid Zamani;Andreas Demosthenous","doi":"10.1109/OJCAS.2024.3389100","DOIUrl":"10.1109/OJCAS.2024.3389100","url":null,"abstract":"This paper describes a supervised speech enhancement (SE) method utilising a noise-aware four-layer deep neural network and training target switching. For optimal speech denoising, the SE system, trained with multiple-target joint learning, switches between mapping-based, masking-based, or complementary processing, depending on the level of noise contamination detected. Optimisation techniques, including ternary quantisation, structural pruning, efficient sparse matrix representation and cost-effective approximations for complex computations, were implemented to reduce area, memory, and power requirements. Up to 19.1x compression was obtained, and all weights could be stored on the on-chip memory. When processing NOISEX-92 noises, the system achieved an average short-time objective intelligibility (STOI) and perceptual evaluation of speech quality (PESQ) scores of 0.81 and 1.62, respectively, outperforming SE algorithms trained with only a single learning target. The proposed SE processor was implemented on a field programmable gate array (FPGA) for proof of concept. Mapping the design on a 65-nm CMOS process led to a chip core area of \u0000<inline-formula> <tex-math>$3.88~mm^{2}$ </tex-math></inline-formula>\u0000 and a power consumption of 1.91 mW when operating at a 10 MHz clock frequency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500889","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-15DOI: 10.1109/OJCAS.2024.3358106
Yan Liu;Yuan Du;Yang Zhao
This special section of the IEEE Open Journal of Circuits and Systems (OJCAS) aims to highlight a selection of papers from 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Due to COVID-19 and travel restrictions, APCCAS 2022 was organised as a hybrid conference during 11 - 13 November 2022 in Shenzhen China. As the regional flagship conference of IEEE Circuits and Systems Society, APCCAS 2022 was driven by the theme “Building a Fully-connected AIoT World” to emphasize the CAS Society’s potential for finding multidisciplinary solutions to societal and industrial challenges. The papers in this special issue were selected from a comprehensive list of papers presented in the sessions of APCCAS 2022.
IEEE Open Journal of Circuits and Systems（OJCAS）的这一专栏旨在重点介绍 2022 年 IEEE 亚太电路与系统会议（APCCAS）的部分论文。由于 COVID-19 和旅行限制，2022 年亚太电路与系统会议将于 2022 年 11 月 11 - 13 日在中国深圳举行。作为 IEEE 电路与系统学会的地区旗舰会议，APCCAS 2022 的主题是 "构建全连接的人工智能物联网世界"，以强调中国科学院学会在为社会和工业挑战寻找多学科解决方案方面的潜力。本特刊中的论文是从 APCCAS 2022 年会议的论文综合清单中挑选出来的。
{"title":"Special Issue on Selected Papers From APCCAS 2022","authors":"Yan Liu;Yuan Du;Yang Zhao","doi":"10.1109/OJCAS.2024.3358106","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3358106","url":null,"abstract":"This special section of the IEEE Open Journal of Circuits and Systems (OJCAS) aims to highlight a selection of papers from 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Due to COVID-19 and travel restrictions, APCCAS 2022 was organised as a hybrid conference during 11 - 13 November 2022 in Shenzhen China. As the regional flagship conference of IEEE Circuits and Systems Society, APCCAS 2022 was driven by the theme “Building a Fully-connected AIoT World” to emphasize the CAS Society’s potential for finding multidisciplinary solutions to societal and industrial challenges. The papers in this special issue were selected from a comprehensive list of papers presented in the sessions of APCCAS 2022.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140555871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-15DOI: 10.1109/OJCAS.2023.3317944
Chien-Cheng Tseng;Su-Ling Lee
In this paper, the computation of graph Fourier transform centrality (GFTC) of complex network using graph filter is presented. For conventional computation method, it needs to use the non-sparse transform matrix of graph Fourier transform (GFT) to compute GFTC scores. To reduce the computational complexity of GFTC, a linear algebra method based on Frobenius norm of error matrix is applied to convert the spectral-domain GFTC computation task to vertex-domain one such that GFTC can be computed by using polynomial graph filtering method. There are two kinds of designs of graph filters to be studied. One is the graph-aware method; the other is the graph-unaware method. The computational complexity comparison and experimental results show that the proposed graph filter method is more computationally efficient than conventional GFT method because the sparsity of Laplacian matrix is used in the implementation structure. Finally, the centrality computations of social network, metro network and sensor network are used to demonstrate the effectiveness of the proposed GFTC computation method using graph filter.
{"title":"Computation of Graph Fourier Transform Centrality Using Graph Filter","authors":"Chien-Cheng Tseng;Su-Ling Lee","doi":"10.1109/OJCAS.2023.3317944","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3317944","url":null,"abstract":"In this paper, the computation of graph Fourier transform centrality (GFTC) of complex network using graph filter is presented. For conventional computation method, it needs to use the non-sparse transform matrix of graph Fourier transform (GFT) to compute GFTC scores. To reduce the computational complexity of GFTC, a linear algebra method based on Frobenius norm of error matrix is applied to convert the spectral-domain GFTC computation task to vertex-domain one such that GFTC can be computed by using polynomial graph filtering method. There are two kinds of designs of graph filters to be studied. One is the graph-aware method; the other is the graph-unaware method. The computational complexity comparison and experimental results show that the proposed graph filter method is more computationally efficient than conventional GFT method because the sparsity of Laplacian matrix is used in the implementation structure. Finally, the centrality computations of social network, metro network and sensor network are used to demonstrate the effectiveness of the proposed GFTC computation method using graph filter.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10500497","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140555836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-12DOI: 10.1109/OJCAS.2024.3388210
Lennart Bamberg;Ardalan Najafi;Alberto Garcia-Ortiz
Specialized compute blocks have been developed for efficient nn execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. This work addresses this bottleneck by contributing a low-power technique for edge-AI inference engines that combines overhead-free coding with a statistical analysis of the data and parameters of neural networks. Our approach reduces the power consumption of the logic, interconnect, and memory blocks used for data storage and movements by up to 80% for state-of-the-art benchmarks while providing additional power savings for the compute blocks by up to 39 %. These power improvements are achieved with no loss of accuracy and negligible hardware cost.
为了实现高效的 nn 执行，我们开发了专门的计算模块。然而，由于大量数据和参数的移动，互连和片上存储器构成了另一个瓶颈，损害了功耗和性能。本研究针对这一瓶颈，为边缘人工智能推理引擎提供了一种低功耗技术，该技术将无开销编码与神经网络数据和参数的统计分析相结合。对于最先进的基准，我们的方法将用于数据存储和移动的逻辑、互连和内存块的功耗降低了 80%，同时为计算块节省了 39% 的额外功耗。在实现这些功耗改进的同时，不会降低精度，硬件成本也可忽略不计。
{"title":"Exploiting Neural-Network Statistics for Low-Power DNN Inference","authors":"Lennart Bamberg;Ardalan Najafi;Alberto Garcia-Ortiz","doi":"10.1109/OJCAS.2024.3388210","DOIUrl":"10.1109/OJCAS.2024.3388210","url":null,"abstract":"Specialized compute blocks have been developed for efficient nn execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. This work addresses this bottleneck by contributing a low-power technique for edge-AI inference engines that combines overhead-free coding with a statistical analysis of the data and parameters of neural networks. Our approach reduces the power consumption of the logic, interconnect, and memory blocks used for data storage and movements by up to 80% for state-of-the-art benchmarks while providing additional power savings for the compute blocks by up to 39 %. These power improvements are achieved with no loss of accuracy and negligible hardware cost.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10498075","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140587370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-11DOI: 10.1109/OJCAS.2024.3387849
Ci-Hao Wu;Tian-Sheuan Chang
Transformer-based speech enhancement models yield impressive results. However, their heterogeneous and complex structure restricts model compression potential, resulting in greater complexity and reduced hardware efficiency. Additionally, these models are not tailored for streaming and low-power applications. Addressing these challenges, this paper proposes a low-power streaming speech enhancement accelerator through model and hardware optimization. The proposed high performance model is optimized for hardware execution with the co-design of model compression and target application, which reduces 93.9% of model size by the proposed domain-aware and streaming-aware pruning techniques. The required latency is further reduced with batch normalization-based transformers. Additionally, we employed softmax-free attention, complemented by an extra batch normalization, facilitating simpler hardware design. The tailored hardware accommodates these diverse computing patterns by breaking them down into element-wise multiplication and accumulation (MAC). This is achieved through a 1-D processing array, utilizing configurable SRAM addressing, thereby minimizing hardware complexities and simplifying zero skipping. Using the TSMC 40nm CMOS process, the final implementation requires merely 207.8K gates and 53.75KB SRAM. It consumes only 8.08 mW for real-time inference at a 62.5MHz frequency.
{"title":"A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices","authors":"Ci-Hao Wu;Tian-Sheuan Chang","doi":"10.1109/OJCAS.2024.3387849","DOIUrl":"10.1109/OJCAS.2024.3387849","url":null,"abstract":"Transformer-based speech enhancement models yield impressive results. However, their heterogeneous and complex structure restricts model compression potential, resulting in greater complexity and reduced hardware efficiency. Additionally, these models are not tailored for streaming and low-power applications. Addressing these challenges, this paper proposes a low-power streaming speech enhancement accelerator through model and hardware optimization. The proposed high performance model is optimized for hardware execution with the co-design of model compression and target application, which reduces 93.9% of model size by the proposed domain-aware and streaming-aware pruning techniques. The required latency is further reduced with batch normalization-based transformers. Additionally, we employed softmax-free attention, complemented by an extra batch normalization, facilitating simpler hardware design. The tailored hardware accommodates these diverse computing patterns by breaking them down into element-wise multiplication and accumulation (MAC). This is achieved through a 1-D processing array, utilizing configurable SRAM addressing, thereby minimizing hardware complexities and simplifying zero skipping. Using the TSMC 40nm CMOS process, the final implementation requires merely 207.8K gates and 53.75KB SRAM. It consumes only 8.08 mW for real-time inference at a 62.5MHz frequency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496994","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140587361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-30DOI: 10.1109/OJCAS.2024.3407663
Vassilis Alimisis;Dimitrios G. Arnaoutoglou;Emmanouil Anastasios Serlis;Argyro Kamperi;Konstantinos Metaxas;George A. Kyriacou;Paul P. Sotiriadis
A fall-detection system was implemented utilizing a 2.45 GHz continuous wave radar along with power-efficient and fully-analog integrated classifier architectures. The Power Burst Curve and the effective acceleration were derived from the short time Fourier transform, and then processed by the analog classifier. The proposed classifier architectures are based on different approximations of the Decision tree classification model. The architectures consist of three main building blocks: sigmoid function circuit, analog multiplier and an argmax operator circuit. To assess the hardware design, a thorough analysis is performed, comparing it to commonly used analog classifiers while exploiting the extracted data. The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.
利用 2.45 GHz 连续波雷达和高能效全模拟集成分类器架构，实现了跌倒检测系统。功率突发曲线和有效加速度由短时傅立叶变换得出，然后由模拟分类器进行处理。所提出的分类器架构基于决策树分类模型的不同近似值。这些架构由三个主要构件组成：sigmoid 函数电路、模拟乘法器和 argmax 运算器电路。为了评估硬件设计，我们进行了全面分析，将其与常用的模拟分类器进行比较，同时利用提取的数据。使用 Python 对架构进行了训练，并与基于软件的分类器进行了比较。电路设计采用台积电的 90 纳米 CMOS 工艺技术，并使用 Cadence IC Suite 完成设计、原理图实现和布局后仿真等任务。
{"title":"A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model","authors":"Vassilis Alimisis;Dimitrios G. Arnaoutoglou;Emmanouil Anastasios Serlis;Argyro Kamperi;Konstantinos Metaxas;George A. Kyriacou;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2024.3407663","DOIUrl":"10.1109/OJCAS.2024.3407663","url":null,"abstract":"A fall-detection system was implemented utilizing a 2.45 GHz continuous wave radar along with power-efficient and fully-analog integrated classifier architectures. The Power Burst Curve and the effective acceleration were derived from the short time Fourier transform, and then processed by the analog classifier. The proposed classifier architectures are based on different approximations of the Decision tree classification model. The architectures consist of three main building blocks: sigmoid function circuit, analog multiplier and an argmax operator circuit. To assess the hardware design, a thorough analysis is performed, comparing it to commonly used analog classifiers while exploiting the extracted data. The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10542293","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141196560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-28DOI: 10.1109/OJCAS.2024.3382355
Mohammad Javad Karimi;Menghe Jin;Catherine Dehollain;Alexandre Schmid
This paper presents a wireless power conversion system designed for biomedical implants, with integrated automatic resonance tuning. The automatic tuning mechanism improves power transfer efficiency (PTE) by finely tuning the resonant frequency of the power link and maximizing the rectified voltage. This adjustment ensures robust and reliable remote powering, even in the face of environmental changes and process variations, while also minimizing tissue exposure to power. On-chip switched array capacitors are connected in parallel with the resonant capacitor, and the system identifies the optimal switched capacitor combination for the highest rectified voltage by iterating over each of them. The proposed system is implemented and fabricated in standard 180nm CMOS technology, with a total area of 0.339 mm2, and its operation is verified. The measurement results demonstrate that this system provides tolerance up to mismatches equivalent to 75 pF capacitance variation in LC tank, ±15% LC variation in this design. The system offers a PTE enhancement from 9.1% to 30.2% in case of high LC variation, and the tuning control consumes 154.7 $mu text{W}$ of power during resonance tuning. Moreover, the power conversion chain delivers an optimized rectified voltage along with a regulated voltage of 1.8 V.
{"title":"A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants","authors":"Mohammad Javad Karimi;Menghe Jin;Catherine Dehollain;Alexandre Schmid","doi":"10.1109/OJCAS.2024.3382355","DOIUrl":"10.1109/OJCAS.2024.3382355","url":null,"abstract":"This paper presents a wireless power conversion system designed for biomedical implants, with integrated automatic resonance tuning. The automatic tuning mechanism improves power transfer efficiency (PTE) by finely tuning the resonant frequency of the power link and maximizing the rectified voltage. This adjustment ensures robust and reliable remote powering, even in the face of environmental changes and process variations, while also minimizing tissue exposure to power. On-chip switched array capacitors are connected in parallel with the resonant capacitor, and the system identifies the optimal switched capacitor combination for the highest rectified voltage by iterating over each of them. The proposed system is implemented and fabricated in standard 180nm CMOS technology, with a total area of 0.339 mm2, and its operation is verified. The measurement results demonstrate that this system provides tolerance up to mismatches equivalent to 75 pF capacitance variation in LC tank, ±15% LC variation in this design. The system offers a PTE enhancement from 9.1% to 30.2% in case of high LC variation, and the tuning control consumes 154.7\u0000<inline-formula> <tex-math>$mu text{W}$ </tex-math></inline-formula>\u0000 of power during resonance tuning. Moreover, the power conversion chain delivers an optimized rectified voltage along with a regulated voltage of 1.8 V.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10481676","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140324283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-26DOI: 10.1109/OJCAS.2024.3381508
Lulu Ge;Keshab K. Parhi
This paper addresses the clustering of data in the hyperdimensional computing (HDC) domain. In prior work, an HDC-based clustering framework, referred to as HDCluster, has been proposed. However, the performance of the existing HDCluster is not robust. The performance of HDCluster is degraded as the hypervectors for the clusters are chosen at random during the initialization step. To overcome this bottleneck, we assign the initial cluster hypervectors by exploring the similarity of the encoded data, referred to as query hypervectors. Intra-cluster hypervectors have a higher similarity than inter-cluster hypervectors. Harnessing the similarity results among query hypervectors, this paper proposes four HDC-based clustering algorithms: similarity-based k-means, equal bin-width histogram, equal bin-height histogram, and similarity-based affinity propagation. Experimental results illustrate that: (i) Compared to the existing HDCluster, our proposed HDC-based clustering algorithms can achieve better accuracy, more robust performance, fewer iterations, and less execution time. Similarity-based affinity propagation outperforms the other three HDC-based clustering algorithms on eight datasets by 2% ~ 38% in clustering accuracy. (ii) Even for one-pass clustering, i.e., without any iterative update of the cluster hypervectors, our proposed algorithms can provide more robust clustering accuracy than HDCluster. (iii) Over eight datasets, five out of eight can achieve higher or comparable accuracy when projected onto the hyperdimensional space. Traditional clustering is more desirable than HDC when the number of clusters, $k$ , is large.
{"title":"Robust Clustering Using Hyperdimensional Computing","authors":"Lulu Ge;Keshab K. Parhi","doi":"10.1109/OJCAS.2024.3381508","DOIUrl":"10.1109/OJCAS.2024.3381508","url":null,"abstract":"This paper addresses the clustering of data in the hyperdimensional computing (HDC) domain. In prior work, an HDC-based clustering framework, referred to as HDCluster, has been proposed. However, the performance of the existing HDCluster is not robust. The performance of HDCluster is degraded as the hypervectors for the clusters are chosen at random during the initialization step. To overcome this bottleneck, we assign the initial cluster hypervectors by exploring the similarity of the encoded data, referred to as query hypervectors. Intra-cluster hypervectors have a higher similarity than inter-cluster hypervectors. Harnessing the similarity results among query hypervectors, this paper proposes four HDC-based clustering algorithms: similarity-based k-means, equal bin-width histogram, equal bin-height histogram, and similarity-based affinity propagation. Experimental results illustrate that: (i) Compared to the existing HDCluster, our proposed HDC-based clustering algorithms can achieve better accuracy, more robust performance, fewer iterations, and less execution time. Similarity-based affinity propagation outperforms the other three HDC-based clustering algorithms on eight datasets by 2% ~ 38% in clustering accuracy. (ii) Even for one-pass clustering, i.e., without any iterative update of the cluster hypervectors, our proposed algorithms can provide more robust clustering accuracy than HDCluster. (iii) Over eight datasets, five out of eight can achieve higher or comparable accuracy when projected onto the hyperdimensional space. Traditional clustering is more desirable than HDC when the number of clusters, \u0000<inline-formula> <tex-math>$k$ </tex-math></inline-formula>\u0000, is large.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10480378","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140314400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-18DOI: 10.1109/OJCAS.2024.3378653
Manish Srivastava;Alessandro Ferro;Aleksandr Sidun;José M. De La Rosa;Kilian O’Donoghue;Pádraig Cantillon-Murphy;Daniel O’Hare
This work presents a small-area 2nd-order continuous-time $Delta Sigma $ Modulator (CT $Delta Sigma text{M}$ ) with a single low dropout regulator (LDO) serving as both the power supply for the CT $Delta Sigma text{M}$ and reference voltage buffer. The CT $Delta Sigma text{M}$ is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and $text{V}_{ref}$ for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT $Delta Sigma text{M}$ consumes $300 ~mu text{W}$ of power when clocked at 10.24 MHz. The CT $Delta Sigma text{M}$ achieves a state-of-the-art area of 0.07 mm2.
{"title":"A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing","authors":"Manish Srivastava;Alessandro Ferro;Aleksandr Sidun;José M. De La Rosa;Kilian O’Donoghue;Pádraig Cantillon-Murphy;Daniel O’Hare","doi":"10.1109/OJCAS.2024.3378653","DOIUrl":"10.1109/OJCAS.2024.3378653","url":null,"abstract":"This work presents a small-area 2nd-order continuous-time \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 Modulator (CT\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000) with a single low dropout regulator (LDO) serving as both the power supply for the CT\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000 and reference voltage buffer. The CT\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000 is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and \u0000<inline-formula> <tex-math>$text{V}_{ref}$ </tex-math></inline-formula>\u0000 for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000 consumes \u0000<inline-formula> <tex-math>$300 ~mu text{W}$ </tex-math></inline-formula>\u0000 of power when clocked at 10.24 MHz. The CT\u0000<inline-formula> <tex-math>$Delta Sigma text{M}$ </tex-math></inline-formula>\u0000 achieves a state-of-the-art area of 0.07 mm2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10475189","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140170286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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