Pub Date : 2025-11-25DOI: 10.1109/OJCAS.2025.3581188
Rella Mareta;Ardianto Satriawan;Hanho Lee
Homomorphic Encryption (HE) enables secure computations on encrypted data, which is crucial for cloud and edge computing. The BFV scheme, widely used for integer arithmetic, faces performance bottlenecks in polynomial multiplication, especially in tensor operations. The Residue Number System (RNS) helps address this, leading to the BEHZ and HPS BFV variants. The Halevi-Polyakov-Shoup (HPS) variant simplifies implementation but still struggles with the overhead of modular arithmetic. We propose an Arithmetic Computing Unit (ACU) optimized for key BFV operations, including modular addition, multiplication, NTT/INTT, and MAC to improve efficiency. Implemented on a Xilinx Alveo U250 FPGA, our design achieves up to $2.3{times }$ higher throughput, $2.2{times }$ less latency, and $9.4{times }$ better BRAM efficiency than existing solutions, demonstrating FPGA acceleration’s for homomorphic encryption.
{"title":"High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption","authors":"Rella Mareta;Ardianto Satriawan;Hanho Lee","doi":"10.1109/OJCAS.2025.3581188","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3581188","url":null,"abstract":"Homomorphic Encryption (HE) enables secure computations on encrypted data, which is crucial for cloud and edge computing. The BFV scheme, widely used for integer arithmetic, faces performance bottlenecks in polynomial multiplication, especially in tensor operations. The Residue Number System (RNS) helps address this, leading to the BEHZ and HPS BFV variants. The Halevi-Polyakov-Shoup (HPS) variant simplifies implementation but still struggles with the overhead of modular arithmetic. We propose an Arithmetic Computing Unit (ACU) optimized for key BFV operations, including modular addition, multiplication, NTT/INTT, and MAC to improve efficiency. Implemented on a Xilinx Alveo U250 FPGA, our design achieves up to <inline-formula> <tex-math>$2.3{times }$ </tex-math></inline-formula> higher throughput, <inline-formula> <tex-math>$2.2{times }$ </tex-math></inline-formula> less latency, and <inline-formula> <tex-math>$9.4{times }$ </tex-math></inline-formula> better BRAM efficiency than existing solutions, demonstrating FPGA acceleration’s for homomorphic encryption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"457-466"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267476","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/OJCAS.2025.3589132
M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John
Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a $2times $ speedup in inference and upto $2times $ reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.
{"title":"MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI","authors":"M. Ajay Kumar;Cian O’Mahoney;Pedro Kreutz Werle;Shreejith Shanker;Dimitrios S. Nikolopoulos;Bo Ji;Hans Vandierendonck;Deepu John","doi":"10.1109/OJCAS.2025.3589132","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3589132","url":null,"abstract":"Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models. Existing accelerator-generation tools, such as AMD’s FINN, do not adequately address extreme resource limitations faced by IoT endpoints operating in bare-metal environments without an operating system (OS). To overcome these constraints, we propose MARVEL–an automated, end-to-end framework that generates custom RISC-V ISA extensions tailored to specific DNN model classes, with a primary focus on convolutional neural networks (CNNs). The proposed method profiles high-level DNN representations in Python and generates an ISA-extended RISC-V core with associated compiler tools for efficient deployment. The flow leverages (1) Apache TVM for translating high-level Python-based DNN models into optimized C code, (2) Synopsys ASIP Designer for identifying compute-intensive kernels, modeling, and generating a custom RISC-V and (3) Xilinx Vivado for FPGA implementation. Beyond a model-class specific RISC-V, our approach produces an optimized bare-metal C implementation, eliminating the need for an OS or extensive software dependencies. Unlike conventional deployment pipelines relying on TensorFlow/PyTorch runtimes, our solution enables seamless execution in highly resource-constrained environments. We evaluated the flow on popular DNN models such as LeNet-5*, MobileNetV1, ResNet50, VGG16, MobileNetV2 and DenseNet121 using the Synopsys trv32p3 RISC-V core as a baseline. Results show a <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> speedup in inference and upto <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> reduction in energy per inference at a 28.23% area overhead when implemented on an AMD Zynq UltraScale+ ZCU104 FPGA platform.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"445-456"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1109/OJCAS.2025.3625587
Ruoman Yang;Tzu-Chien Hsueh
A low-power time-to-voltage converter (TVC) is composed of a reconfigurable current-mode integrator and a capacitive voltage holder specifically for random sampling-and-averaging (RSA) time-to-digital conversions (TDC) in time-correlated single-photon counting (TCSPC) systems. To accommodate the TVC circuit within each single-photon detection pixel for compact silicon-photonics integration, this paper exploits the Miller-impedance technique to demonstrate the leakage time-constant of the voltage holder being extended up to tens of milliseconds, which represents a more than $100times $ improvement in high-leakage 22-nm digital CMOS process technology, with only a 9-pF (36-$mu $ m $times 36$ -$mu $ m) metal-finger hold capacitor and 120-$mu $ W power consumption.
针对时间相关单光子计数（TCSPC）系统中的随机采样和平均（RSA）时间-数字转换（TDC），设计了一种低功耗时间-电压转换器（TVC），由可重构电流模式积分器和电容电压保持器组成。为了在每个单光子检测像素内容纳TVC电路以实现紧凑的硅光子集成，本文利用米勒阻抗技术证明了电压保持器的泄漏时间常数被扩展到数十毫秒，这代表了高泄漏22纳米数字CMOS工艺技术的100多倍改进。只有一个9-pF （36- $mu $ m $乘以36$ - $mu $ m $）金属手指保持电容器和120- $mu $ W的功耗。
{"title":"A Time-to-Voltage Converter With Miller-Impedance Technique for Single-Photon Arrival Time-to-Digital Conversions","authors":"Ruoman Yang;Tzu-Chien Hsueh","doi":"10.1109/OJCAS.2025.3625587","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3625587","url":null,"abstract":"A low-power time-to-voltage converter (TVC) is composed of a reconfigurable current-mode integrator and a capacitive voltage holder specifically for random sampling-and-averaging (RSA) time-to-digital conversions (TDC) in time-correlated single-photon counting (TCSPC) systems. To accommodate the TVC circuit within each single-photon detection pixel for compact silicon-photonics integration, this paper exploits the Miller-impedance technique to demonstrate the leakage time-constant of the voltage holder being extended up to tens of milliseconds, which represents a more than <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> improvement in high-leakage 22-nm digital CMOS process technology, with only a 9-pF (36-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 36$ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m) metal-finger hold capacitor and 120-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W power consumption.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"467-476"},"PeriodicalIF":2.4,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11218226","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-05DOI: 10.1109/OJCAS.2025.3606618
Paul Kaesser;Maurits Ortmanns
incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are widely utilized in applications requiring high-resolution Nyquist conversion. Accurate performance prediction of these converters is crucial for efficient design and optimization. Existing state of the art (SoA) equations are either lacking sufficient accuracy or simplicity in predicting quantization noise performance under various architectural scenarios. This paper reviews the derivation and limitations of existing performance prediction models. A more general and accurate analysis is derived for predicting the performance of I-DS ADCs, addressing the shortcomings of the conventional approaches. The validity of the proposed performance prediction is rigorously evaluated through extensive simulations across a broad range of architectural choices. The results establish the new model as a robust tool for predicting the performance of I-DS ADCs, advancing the SoA, and facilitating more effective design strategies in the field.
{"title":"Performance Prediction of Incremental ΔΣ ADCs","authors":"Paul Kaesser;Maurits Ortmanns","doi":"10.1109/OJCAS.2025.3606618","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3606618","url":null,"abstract":"incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are widely utilized in applications requiring high-resolution Nyquist conversion. Accurate performance prediction of these converters is crucial for efficient design and optimization. Existing state of the art (SoA) equations are either lacking sufficient accuracy or simplicity in predicting quantization noise performance under various architectural scenarios. This paper reviews the derivation and limitations of existing performance prediction models. A more general and accurate analysis is derived for predicting the performance of I-DS ADCs, addressing the shortcomings of the conventional approaches. The validity of the proposed performance prediction is rigorously evaluated through extensive simulations across a broad range of architectural choices. The results establish the new model as a robust tool for predicting the performance of I-DS ADCs, advancing the SoA, and facilitating more effective design strategies in the field.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"424-431"},"PeriodicalIF":2.4,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11152582","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-03DOI: 10.1109/OJCAS.2025.3604902
Uday Maurya;Mahima Arrawatia;Nagarjuna Nallam
The balanced power amplifier (BPA) topology is commonly used in applications requiring high antenna impedance tolerance. This paper presents a low-loss transmit-receive (T/R) front-end module (FEM) with BPA using four shunt switches. These switches are embedded into the output network of the BPA and the input matching network of the common source low noise amplifier (LNA). A prototype T/R FEM is implemented in bulk CMOS 65 nm technology for the 5G FR2 n260 band. As per simulations, the extra loss due to the T/R interface in transmit mode is 0.75 dB, and the noise figure (NF) degradation in receive mode is 1.5 dB. The prototype chip is characterized by die-probing. The BPA delivers a saturated power output of + 18 dBm with a power-added efficiency (PAE) of 14.5 % at 40 GHz in measurements. The LNA has a gain of 21.3 dB and a noise figure of 5.8 dB in the n260 band.
{"title":"A Low-Loss T/R Module With Balanced Power Amplifier for High Antenna Impedance Tolerance","authors":"Uday Maurya;Mahima Arrawatia;Nagarjuna Nallam","doi":"10.1109/OJCAS.2025.3604902","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3604902","url":null,"abstract":"The balanced power amplifier (BPA) topology is commonly used in applications requiring high antenna impedance tolerance. This paper presents a low-loss transmit-receive (T/R) front-end module (FEM) with BPA using four shunt switches. These switches are embedded into the output network of the BPA and the input matching network of the common source low noise amplifier (LNA). A prototype T/R FEM is implemented in bulk CMOS 65 nm technology for the 5G FR2 n260 band. As per simulations, the extra loss due to the T/R interface in transmit mode is 0.75 dB, and the noise figure (NF) degradation in receive mode is 1.5 dB. The prototype chip is characterized by die-probing. The BPA delivers a saturated power output of + 18 dBm with a power-added efficiency (PAE) of 14.5 % at 40 GHz in measurements. The LNA has a gain of 21.3 dB and a noise figure of 5.8 dB in the n260 band.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"414-423"},"PeriodicalIF":2.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11150516","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-27DOI: 10.1109/OJCAS.2025.3592376
Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano
This paper presents a hardware-software deep learning architecture for prediction-based spectrum sensing in Cognitive Radio (CR) applications. A convolutional neural network-based predictor for spectrum occupancy was trained using the band power from I/Q samples acquired by a softwaredefined radio (SDR). Additionally, a second neural engine was trained for radio frequency (RF) frame detection based on spectrograms. We implemented a transfer-learning solution using a You-Only-LookOnce version 8 nano model with a synthetic dataset comprising thousands of wireless signals, including Wi-Fi, Bluetooth, and collision frames. Once trained, the two neural networks were transferred to a Raspberry Pi 5 – an affordable single-board computer – connected to two (one for Rx, one for Tx) ADALM-PLUTO SDR systems for benchmarking using over-the-air signals in the 2.4 GHz band. Together with our methodology and experimental results, the paper also presents an overview of current spectrum prediction proposals and RF frame detectors. Remarkably, to the best of our knowledge, this proposed framework is the first approach towards an Internet of Things-suitable implementation of prediction-based spectrum sensing for CR applications.
针对认知无线电（CR）应用中基于预测的频谱感知，提出了一种硬件-软件深度学习架构。使用软件定义无线电（SDR）获取的I/Q样本的频带功率训练基于卷积神经网络的频谱占用预测器。此外，还训练了第二个神经引擎，用于基于频谱图的射频帧检测。我们使用You-Only-LookOnce版本8纳米模型实现了一个迁移学习解决方案，该模型具有包含数千个无线信号的合成数据集，包括Wi-Fi、蓝牙和碰撞帧。经过训练后，两个神经网络被转移到Raspberry Pi 5上，这是一款价格实惠的单板计算机，连接到两个（一个用于Rx，一个用于Tx） ADALM-PLUTO SDR系统，使用2.4 GHz频段的空中信号进行基准测试。结合我们的方法和实验结果，本文还概述了目前的频谱预测建议和射频帧检测器。值得注意的是，据我们所知，该框架是第一个适合物联网的基于预测的频谱感知CR应用实现方法。
{"title":"Prediction-Based Spectrum Sensing Framework for Cognitive Radio","authors":"Andres Rojas;Gawen Follet;Gordana Jovanovic Dolecek;José M. De La Rosa;Gustavo Liñán-Cembrano","doi":"10.1109/OJCAS.2025.3592376","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3592376","url":null,"abstract":"This paper presents a hardware-software deep learning architecture for prediction-based spectrum sensing in Cognitive Radio (CR) applications. A convolutional neural network-based predictor for spectrum occupancy was trained using the band power from I/Q samples acquired by a softwaredefined radio (SDR). Additionally, a second neural engine was trained for radio frequency (RF) frame detection based on spectrograms. We implemented a transfer-learning solution using a You-Only-LookOnce version 8 nano model with a synthetic dataset comprising thousands of wireless signals, including Wi-Fi, Bluetooth, and collision frames. Once trained, the two neural networks were transferred to a Raspberry Pi 5 – an affordable single-board computer – connected to two (one for Rx, one for Tx) ADALM-PLUTO SDR systems for benchmarking using over-the-air signals in the 2.4 GHz band. Together with our methodology and experimental results, the paper also presents an overview of current spectrum prediction proposals and RF frame detectors. Remarkably, to the best of our knowledge, this proposed framework is the first approach towards an Internet of Things-suitable implementation of prediction-based spectrum sensing for CR applications.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"313-328"},"PeriodicalIF":2.4,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142737","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/OJCAS.2025.3602678
Chia Jen Cheng;Ethan Chen;Vanessa Chen
The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters' fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.
{"title":"Improving Neural Network Fault Tolerance Against Weight Attack","authors":"Chia Jen Cheng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJCAS.2025.3602678","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3602678","url":null,"abstract":"The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters' fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"383-392"},"PeriodicalIF":2.4,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142271","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-25DOI: 10.1109/OJCAS.2025.3602353
Andrew Ash;John Hu
In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.
{"title":"A Proxy ADC Framework for Side-Channel Secure ADC Analysis","authors":"Andrew Ash;John Hu","doi":"10.1109/OJCAS.2025.3602353","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3602353","url":null,"abstract":"In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"401-413"},"PeriodicalIF":2.4,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11138015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1109/OJCAS.2025.3598990
Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee
This paper introduces a highly efficient cross-coupled active rectifier with fast switching comparators for wireless power transfer (WPT) system. Wireless power transfer technology is increasingly being utilized in various applications. In our proposed design an active diode switches are introduced at lower side of power MOSFET to minimize the switching delay in power transistors and also reduces reverse leakage current to boost power conversion efficiency. The active diode is constructed from high-speed comparators and CMOS power switches. A cross-coupled technique is applied to the high side PMOS power transistors, in order to minimizing power consumption and optimizing current management. This enhancement not only improves the power efficiency of the cross-coupled active rectifier but also prolongs battery life and boosts the overall Efficiency. The cross-coupled architecture of the proposed rectifier enables high-speed switching, which is necessary for its design. This allows for fast response times and efficient signal processing. The presented cross-coupled active rectifier is designed using $0.18~mu $ m CMOS technology. It delivers 2.77 W of output power using a $1~mu $ F capacitor with a 0.3A load current, and it achieves a power efficiency of 92.4%.
{"title":"A High Efficient Cross-Coupled Active Rectifier by Using High Speed Switching Comparators for Wireless Power Receiver","authors":"Syed Adil Ali Shah;Young-Gun Pu;Young-Joon Kim;Kang-Yoon Lee","doi":"10.1109/OJCAS.2025.3598990","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3598990","url":null,"abstract":"This paper introduces a highly efficient cross-coupled active rectifier with fast switching comparators for wireless power transfer (WPT) system. Wireless power transfer technology is increasingly being utilized in various applications. In our proposed design an active diode switches are introduced at lower side of power MOSFET to minimize the switching delay in power transistors and also reduces reverse leakage current to boost power conversion efficiency. The active diode is constructed from high-speed comparators and CMOS power switches. A cross-coupled technique is applied to the high side PMOS power transistors, in order to minimizing power consumption and optimizing current management. This enhancement not only improves the power efficiency of the cross-coupled active rectifier but also prolongs battery life and boosts the overall Efficiency. The cross-coupled architecture of the proposed rectifier enables high-speed switching, which is necessary for its design. This allows for fast response times and efficient signal processing. The presented cross-coupled active rectifier is designed using <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m CMOS technology. It delivers 2.77 W of output power using a <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>F capacitor with a 0.3A load current, and it achieves a power efficiency of 92.4%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"393-400"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/OJCAS.2025.3574336
Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang
Ultra-low-supply-voltage (ULV) analog-to-digital converters (ADCs) operating at 0.21 V or lower are attractive for Internet-of-Things (IoT) and embedded applications due to their extremely low power consumption. This paper surveys state-of-the-art ULV ADCs to evaluate current trends and design strategies. Architectures, circuit implementations, and calibration techniques are analyzed and key trends are identified. Based on the observations, the paper provides recommendations for the circuit designer to make judicious design choices to obtain the desired performance for ULV ADCs. This paper further explores the VCO-based architecture and proposes a new topology to achieve high resolution for ULV ADCs.
{"title":"A Review on Sub-0.21-V Ultra-Low-Supply-Voltage Analog-to-Digital Converters","authors":"Eric Christie;Jared Marchant;Shea Smith;Long Kong;Chia-Hung Chen;Shiuh-Hua Wood Chiang","doi":"10.1109/OJCAS.2025.3574336","DOIUrl":"https://doi.org/10.1109/OJCAS.2025.3574336","url":null,"abstract":"Ultra-low-supply-voltage (ULV) analog-to-digital converters (ADCs) operating at 0.21 V or lower are attractive for Internet-of-Things (IoT) and embedded applications due to their extremely low power consumption. This paper surveys state-of-the-art ULV ADCs to evaluate current trends and design strategies. Architectures, circuit implementations, and calibration techniques are analyzed and key trends are identified. Based on the observations, the paper provides recommendations for the circuit designer to make judicious design choices to obtain the desired performance for ULV ADCs. This paper further explores the VCO-based architecture and proposes a new topology to achieve high resolution for ULV ADCs.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"6 ","pages":"228-240"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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